^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Intel MSIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/intel_msic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/intel_scu_ipc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MSIC_VENDOR(id) ((id >> 6) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MSIC_VERSION(id) (id & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MSIC_MAJOR(id) ('A' + ((id >> 3) & 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MSIC_MINOR(id) (id & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Since IRQ block starts from address 0x002 we need to subtract that from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the actual IRQ status register address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MSIC_IRQ_STATUS_ACCDET MSIC_IRQ_STATUS(INTEL_MSIC_ACCDET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * The SCU hardware has limitation of 16 bytes per read/write buffer on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Medfield.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCU_IPC_RWBUF_LIMIT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * struct intel_msic - an MSIC MFD instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @pdev: pointer to the platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @vendor: vendor ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @version: chip version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @irq_base: base address of the mapped MSIC SRAM interrupt tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct intel_msic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct resource msic_touch_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct resource msic_adc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct resource msic_battery_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct resource msic_gpio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct resource msic_audio_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEFINE_RES_IRQ_NAMED(0, "IRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * We will pass IRQ_BASE to the driver now but this can be removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * when/if the driver starts to use intel_msic_irq_read().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE_RES_MEM_NAMED(MSIC_IRQ_STATUS_ACCDET, 1, "IRQ_BASE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct resource msic_hdmi_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct resource msic_thermal_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct resource msic_power_btn_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct resource msic_ocd_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Devices that are part of the MSIC and are available via firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * populated SFI DEVS table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct mfd_cell msic_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [INTEL_MSIC_BLOCK_TOUCH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "msic_touch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .num_resources = ARRAY_SIZE(msic_touch_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .resources = msic_touch_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [INTEL_MSIC_BLOCK_ADC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = "msic_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .num_resources = ARRAY_SIZE(msic_adc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .resources = msic_adc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [INTEL_MSIC_BLOCK_BATTERY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "msic_battery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .num_resources = ARRAY_SIZE(msic_battery_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .resources = msic_battery_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [INTEL_MSIC_BLOCK_GPIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "msic_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .num_resources = ARRAY_SIZE(msic_gpio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .resources = msic_gpio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [INTEL_MSIC_BLOCK_AUDIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "msic_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .num_resources = ARRAY_SIZE(msic_audio_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .resources = msic_audio_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [INTEL_MSIC_BLOCK_HDMI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = "msic_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .num_resources = ARRAY_SIZE(msic_hdmi_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .resources = msic_hdmi_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [INTEL_MSIC_BLOCK_THERMAL] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = "msic_thermal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .num_resources = ARRAY_SIZE(msic_thermal_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .resources = msic_thermal_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [INTEL_MSIC_BLOCK_POWER_BTN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = "msic_power_btn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .num_resources = ARRAY_SIZE(msic_power_btn_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .resources = msic_power_btn_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [INTEL_MSIC_BLOCK_OCD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "msic_ocd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .num_resources = ARRAY_SIZE(msic_ocd_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .resources = msic_ocd_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Other MSIC related devices which are not directly available via SFI DEVS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * table. These can be pseudo devices, regulators etc. which are needed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * different purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * These devices appear only after the MSIC driver itself is initialized so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * we can guarantee that the SCU IPC interface is ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct mfd_cell msic_other_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Audio codec in the MSIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "sn95031",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * intel_msic_reg_read - read a single MSIC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @reg: register to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @val: register value is placed here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Read a single register from MSIC. Returns %0 on success and negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * errno in case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Function may sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int intel_msic_reg_read(unsigned short reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return intel_scu_ipc_ioread8(reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) EXPORT_SYMBOL_GPL(intel_msic_reg_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * intel_msic_reg_write - write a single MSIC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @reg: register to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @val: value to write to that register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Write a single MSIC register. Returns 0 on success and negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * errno in case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Function may sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int intel_msic_reg_write(unsigned short reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return intel_scu_ipc_iowrite8(reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) EXPORT_SYMBOL_GPL(intel_msic_reg_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * intel_msic_reg_update - update a single MSIC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @reg: register to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @val: value to write to the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @mask: specifies which of the bits are updated (%0 = don't update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * %1 = update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Perform an update to a register @reg. @mask is used to specify which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * bits are updated. Returns %0 in case of success and negative errno in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Function may sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return intel_scu_ipc_update_register(reg, val, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) EXPORT_SYMBOL_GPL(intel_msic_reg_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * intel_msic_bulk_read - read an array of registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @reg: array of register addresses to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @buf: array where the read values are placed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @count: number of registers to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Function reads @count registers from the MSIC using addresses passed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @reg. Read values are placed in @buf. Reads are performed atomically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * wrt. MSIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Returns %0 in case of success and negative errno in case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Function may sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return intel_scu_ipc_readv(reg, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) EXPORT_SYMBOL_GPL(intel_msic_bulk_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * intel_msic_bulk_write - write an array of values to the MSIC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @reg: array of registers to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @buf: values to write to each register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @count: number of registers to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Function writes @count registers in @buf to MSIC. Writes are performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * atomically wrt MSIC. Returns %0 in case of success and negative errno in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * case of failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Function may sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return intel_scu_ipc_writev(reg, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EXPORT_SYMBOL_GPL(intel_msic_bulk_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * intel_msic_irq_read - read a register from an MSIC interrupt tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @msic: MSIC instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @reg: interrupt register (between %INTEL_MSIC_IRQLVL1 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * %INTEL_MSIC_RESETIRQ2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @val: value of the register is placed here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * This function can be used by an MSIC subdevice interrupt handler to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * a register value from the MSIC interrupt tree. In this way subdevice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * drivers don't have to map in the interrupt tree themselves but can just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * call this function instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Function doesn't sleep and is callable from interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Returns %-EINVAL if @reg is outside of the allowed register region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (WARN_ON(reg < INTEL_MSIC_IRQLVL1 || reg > INTEL_MSIC_RESETIRQ2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) EXPORT_SYMBOL_GPL(intel_msic_irq_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int intel_msic_init_devices(struct intel_msic *msic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct platform_device *pdev = msic->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (pdata->gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct mfd_cell *cell = &msic_devs[INTEL_MSIC_BLOCK_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cell->platform_data = pdata->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) cell->pdata_size = sizeof(*pdata->gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (pdata->ocd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned gpio = pdata->ocd->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = devm_gpio_request_one(&pdev->dev, gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) GPIOF_IN, "ocd_gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(&pdev->dev, "failed to register OCD GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = gpio_to_irq(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(&pdev->dev, "no IRQ number for OCD GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Update the IRQ number for the OCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pdata->irq[INTEL_MSIC_BLOCK_OCD] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (i = 0; i < ARRAY_SIZE(msic_devs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!pdata->irq[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = mfd_add_devices(&pdev->dev, -1, &msic_devs[i], 1, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pdata->irq[i], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = mfd_add_devices(&pdev->dev, 0, msic_other_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ARRAY_SIZE(msic_other_devs), NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mfd_remove_devices(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void intel_msic_remove_devices(struct intel_msic *msic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct platform_device *pdev = msic->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mfd_remove_devices(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int intel_msic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct intel_msic *msic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 id0, id1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(&pdev->dev, "no platform data passed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* First validate that we have an MSIC in place */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID0, &id0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(&pdev->dev, "failed to identify the MSIC chip (ID0)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID1, &id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(&pdev->dev, "failed to identify the MSIC chip (ID1)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (MSIC_VENDOR(id0) != MSIC_VENDOR(id1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(&pdev->dev, "invalid vendor ID: %x, %x\n", id0, id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) msic = devm_kzalloc(&pdev->dev, sizeof(*msic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!msic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) msic->vendor = MSIC_VENDOR(id0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) msic->version = MSIC_VERSION(id0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) msic->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Map in the MSIC interrupt tree area in SRAM. This is exposed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * the clients via intel_msic_irq_read().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) msic->irq_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (IS_ERR(msic->irq_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return PTR_ERR(msic->irq_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) platform_set_drvdata(pdev, msic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = intel_msic_init_devices(msic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_err(&pdev->dev, "failed to initialize MSIC devices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_info(&pdev->dev, "Intel MSIC version %c%d (vendor %#x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MSIC_MAJOR(msic->version), MSIC_MINOR(msic->version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) msic->vendor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int intel_msic_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct intel_msic *msic = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) intel_msic_remove_devices(msic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct platform_driver intel_msic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .probe = intel_msic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .remove = intel_msic_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .name = "intel_msic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) builtin_platform_driver(intel_msic_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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