^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel MAX 10 Board Management Controller chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/intel-m10-bmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum m10bmc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) M10_N3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { .name = "n3000bmc-hwmon" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { .name = "n3000bmc-retimer" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { .name = "n3000bmc-secure" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct regmap_config intel_m10bmc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .max_register = M10BMC_MEM_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static ssize_t bmc_version_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct intel_m10bmc *ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret = m10bmc_sys_read(ddata, M10BMC_BUILD_VER, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return sprintf(buf, "0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static DEVICE_ATTR_RO(bmc_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static ssize_t bmcfw_version_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct intel_m10bmc *ddata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret = m10bmc_sys_read(ddata, NIOS2_FW_VERSION, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return sprintf(buf, "0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static DEVICE_ATTR_RO(bmcfw_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct attribute *m10bmc_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) &dev_attr_bmc_version.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) &dev_attr_bmcfw_version.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ATTRIBUTE_GROUPS(m10bmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int check_m10bmc_version(struct intel_m10bmc *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * This check is to filter out the very old legacy BMC versions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * M10BMC_LEGACY_SYS_BASE is the offset to this old block of mmio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * registers. In the old BMC chips, the BMC version info is stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * in this old version register (M10BMC_LEGACY_SYS_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * M10BMC_BUILD_VER), so its read out value would have not been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * LEGACY_INVALID (0xffffffff). But in new BMC chips that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * driver supports, the value of this register should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * LEGACY_INVALID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = m10bmc_raw_read(ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) M10BMC_LEGACY_SYS_BASE + M10BMC_BUILD_VER, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (v != M10BMC_VER_LEGACY_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(ddata->dev, "bad version M10BMC detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int intel_m10_bmc_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mfd_cell *cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct intel_m10bmc *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret, n_cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ddata->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ddata->regmap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) devm_regmap_init_spi_avmm(spi, &intel_m10bmc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (IS_ERR(ddata->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = PTR_ERR(ddata->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_err(dev, "Failed to allocate regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) spi_set_drvdata(spi, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = check_m10bmc_version(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_err(dev, "Failed to identify m10bmc hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) switch (id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case M10_N3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cells = m10bmc_pacn3000_subdevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) n_cell = ARRAY_SIZE(m10bmc_pacn3000_subdevs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, n_cell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_err(dev, "Failed to register sub-devices: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct spi_device_id m10bmc_spi_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { "m10-n3000", M10_N3000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct spi_driver intel_m10bmc_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "intel-m10-bmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .dev_groups = m10bmc_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .probe = intel_m10_bmc_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .id_table = m10bmc_spi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) module_spi_driver(intel_m10bmc_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MODULE_DESCRIPTION("Intel MAX 10 BMC Device Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_ALIAS("spi:intel-m10-bmc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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