^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Sunrisepoint LPSS core support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Heikki Krogerus <heikki.krogerus@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Jarkko Nikula <jarkko.nikula@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_qos.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/dma/idma64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "intel-lpss.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPSS_DEV_OFFSET 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPSS_DEV_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPSS_PRIV_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPSS_PRIV_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPSS_IDMA64_OFFSET 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPSS_IDMA64_SIZE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Offsets from lpss->priv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPSS_PRIV_RESETS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPSS_PRIV_RESETS_IDMA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPSS_PRIV_RESETS_FUNC 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPSS_PRIV_ACTIVELTR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPSS_PRIV_IDLELTR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LPSS_PRIV_LTR_REQ BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LPSS_PRIV_LTR_SCALE_1US (2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LPSS_PRIV_LTR_SCALE_32US (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LPSS_PRIV_SSP_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LPSS_PRIV_REMAP_ADDR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LPSS_PRIV_CAPS 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* This matches the type field in CAPS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) enum intel_lpss_dev_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LPSS_DEV_I2C = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) LPSS_DEV_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) LPSS_DEV_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct intel_lpss {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct intel_lpss_platform_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum intel_lpss_dev_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk_lookup *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct mfd_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 priv_ctx[LPSS_PRIV_REG_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 active_ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 idle_ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct resource intel_lpss_dev_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct resource intel_lpss_idma64_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DEFINE_RES_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Cells needs to be ordered so that the iDMA is created first. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * because we need to be sure the DMA is available when the host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * driver is probed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct mfd_cell intel_lpss_idma64_cell = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = LPSS_IDMA64_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .resources = intel_lpss_idma64_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct mfd_cell intel_lpss_i2c_cell = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "i2c_designware",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .resources = intel_lpss_dev_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct mfd_cell intel_lpss_uart_cell = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "dw-apb-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .resources = intel_lpss_dev_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct mfd_cell intel_lpss_spi_cell = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "pxa2xx-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .resources = intel_lpss_dev_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static DEFINE_IDA(intel_lpss_devid_ida);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct dentry *intel_lpss_debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct dentry *dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ERR(dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return PTR_ERR(dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Cache the values into lpss structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) intel_lpss_cache_ltr(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) lpss->debugfs = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) debugfs_remove_recursive(lpss->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void intel_lpss_ltr_set(struct device *dev, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct intel_lpss *lpss = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Program latency tolerance (LTR) accordingly what has been asked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * by the PM QoS layer or disable it in case we were passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * negative value or PM_QOS_LATENCY_ANY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (val == PM_QOS_LATENCY_ANY || val < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ltr &= ~LPSS_PRIV_LTR_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ltr |= LPSS_PRIV_LTR_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (val > LPSS_PRIV_LTR_VALUE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ltr == lpss->active_ltr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Cache the values into lpss structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) intel_lpss_cache_ltr(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_pm_qos_expose_latency_tolerance(lpss->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_pm_qos_hide_latency_tolerance(lpss->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) lpss->dev->power.set_latency_tolerance = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int intel_lpss_assign_devs(struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const struct mfd_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case LPSS_DEV_I2C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cell = &intel_lpss_i2c_cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case LPSS_DEV_UART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cell = &intel_lpss_uart_cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case LPSS_DEV_SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) cell = &intel_lpss_spi_cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!lpss->cell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) lpss->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) resource_size_t addr = lpss->info->mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Bring out the device from reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writel(value, lpss->priv + LPSS_PRIV_RESETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void intel_lpss_init_dev(const struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Set the device in reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(0, lpss->priv + LPSS_PRIV_RESETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) intel_lpss_deassert_reset(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) intel_lpss_set_remap_addr(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!intel_lpss_has_idma(lpss))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Make sure that SPI multiblock DMA transfers are re-enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (lpss->type == LPSS_DEV_SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void intel_lpss_unregister_clock_tree(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) while (clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) parent = clk_get_parent(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const char *devname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct clk **clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct clk *tmp = *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) snprintf(name, sizeof(name), "%s-enable", devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) lpss->priv, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (IS_ERR(tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return PTR_ERR(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) snprintf(name, sizeof(name), "%s-div", devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0, lpss->priv, 1, 15, 16, 15, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (IS_ERR(tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return PTR_ERR(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *clk = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) snprintf(name, sizeof(name), "%s-update", devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (IS_ERR(tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return PTR_ERR(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *clk = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int intel_lpss_register_clock(struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) const struct mfd_cell *cell = lpss->cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) char devname[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!lpss->info->clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Root clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) lpss->info->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Support for clock divider only if it has some preset value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Otherwise we assume that the divider is not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (lpss->type != LPSS_DEV_I2C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Clock for the host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!lpss->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) lpss->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) err_clk_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) intel_lpss_unregister_clock_tree(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (IS_ERR_OR_NULL(lpss->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clkdev_drop(lpss->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) intel_lpss_unregister_clock_tree(lpss->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int intel_lpss_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) const struct intel_lpss_platform_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct intel_lpss *lpss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!info || !info->mem || info->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!lpss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) LPSS_PRIV_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!lpss->priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) lpss->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) lpss->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_set_drvdata(dev, lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = intel_lpss_assign_devs(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) lpss->cell->properties = info->properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) intel_lpss_init_dev(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (lpss->devid < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return lpss->devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = intel_lpss_register_clock(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) intel_lpss_ltr_expose(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = intel_lpss_debugfs_add(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_warn(dev, "Failed to create debugfs entries\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (intel_lpss_has_idma(lpss)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 1, info->mem, info->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_warn(dev, "Failed to add %s, fallback to PIO\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) LPSS_IDMA64_DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 1, info->mem, info->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto err_remove_ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) err_remove_ltr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) intel_lpss_debugfs_remove(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) intel_lpss_ltr_hide(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) intel_lpss_unregister_clock(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) err_clk_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) EXPORT_SYMBOL_GPL(intel_lpss_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void intel_lpss_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct intel_lpss *lpss = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mfd_remove_devices(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) intel_lpss_debugfs_remove(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) intel_lpss_ltr_hide(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) intel_lpss_unregister_clock(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) EXPORT_SYMBOL_GPL(intel_lpss_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int resume_lpss_device(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pm_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int intel_lpss_prepare(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Resume both child devices before entering system sleep. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * ensures that they are in proper state before they get suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) device_for_each_child_reverse(dev, NULL, resume_lpss_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) EXPORT_SYMBOL_GPL(intel_lpss_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int intel_lpss_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct intel_lpss *lpss = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Save device context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * If the device type is not UART, then put the controller into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * reset. UART cannot be put into reset since S3/S0ix fail when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * no_console_suspend flag is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (lpss->type != LPSS_DEV_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) writel(0, lpss->priv + LPSS_PRIV_RESETS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) EXPORT_SYMBOL_GPL(intel_lpss_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int intel_lpss_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct intel_lpss *lpss = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) intel_lpss_deassert_reset(lpss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Restore device context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel(lpss->priv_ctx[i], lpss->priv + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) EXPORT_SYMBOL_GPL(intel_lpss_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int __init intel_lpss_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) module_init(intel_lpss_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void __exit intel_lpss_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ida_destroy(&intel_lpss_devid_ida);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) debugfs_remove(intel_lpss_debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) module_exit(intel_lpss_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_DESCRIPTION("Intel LPSS core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Ensure the DMA driver is loaded before the host controller device appears,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * so that the host controller driver can request its DMA channels as early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * If the DMA module is not there that's OK as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MODULE_SOFTDEP("pre: platform:" LPSS_IDMA64_DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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