^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel LPSS PCI support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "intel-lpss.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int intel_lpss_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct intel_lpss_platform_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ret = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) info->mem = &pdev->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) info->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pdev->d3cold_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Probably it is enough to set this for iDMA capable devices only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pci_try_set_mwi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ret = intel_lpss_probe(&pdev->dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pm_runtime_allow(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void intel_lpss_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pm_runtime_forbid(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) intel_lpss_remove(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static INTEL_LPSS_PM_OPS(intel_lpss_pci_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct intel_lpss_platform_info spt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .clk_rate = 120000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct property_entry spt_i2c_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 230),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct intel_lpss_platform_info spt_i2c_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .clk_rate = 120000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .properties = spt_i2c_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct property_entry uart_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PROPERTY_ENTRY_U32("reg-io-width", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PROPERTY_ENTRY_U32("reg-shift", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct intel_lpss_platform_info spt_uart_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .clk_rate = 120000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .clk_con_id = "baudclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .properties = uart_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct intel_lpss_platform_info bxt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .clk_rate = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct intel_lpss_platform_info bxt_uart_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .clk_rate = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .clk_con_id = "baudclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .properties = uart_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct property_entry bxt_i2c_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct intel_lpss_platform_info bxt_i2c_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .clk_rate = 133000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .properties = bxt_i2c_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct property_entry apl_i2c_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 207),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct intel_lpss_platform_info apl_i2c_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .clk_rate = 133000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .properties = apl_i2c_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct property_entry glk_i2c_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 313),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 290),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct intel_lpss_platform_info glk_i2c_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .clk_rate = 133000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .properties = glk_i2c_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct intel_lpss_platform_info cnl_i2c_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .clk_rate = 216000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .properties = spt_i2c_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct intel_lpss_platform_info ehl_i2c_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .clk_rate = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .properties = bxt_i2c_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct pci_device_id intel_lpss_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* CML-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { PCI_VDEVICE(INTEL, 0x02a8), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { PCI_VDEVICE(INTEL, 0x02a9), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { PCI_VDEVICE(INTEL, 0x02aa), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { PCI_VDEVICE(INTEL, 0x02ab), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { PCI_VDEVICE(INTEL, 0x02c5), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { PCI_VDEVICE(INTEL, 0x02c6), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { PCI_VDEVICE(INTEL, 0x02c7), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { PCI_VDEVICE(INTEL, 0x02e8), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { PCI_VDEVICE(INTEL, 0x02e9), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { PCI_VDEVICE(INTEL, 0x02ea), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { PCI_VDEVICE(INTEL, 0x02eb), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { PCI_VDEVICE(INTEL, 0x02fb), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* CML-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { PCI_VDEVICE(INTEL, 0x06a8), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { PCI_VDEVICE(INTEL, 0x06a9), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { PCI_VDEVICE(INTEL, 0x06aa), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { PCI_VDEVICE(INTEL, 0x06ab), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { PCI_VDEVICE(INTEL, 0x06c7), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { PCI_VDEVICE(INTEL, 0x06e8), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { PCI_VDEVICE(INTEL, 0x06e9), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { PCI_VDEVICE(INTEL, 0x06ea), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { PCI_VDEVICE(INTEL, 0x06eb), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { PCI_VDEVICE(INTEL, 0x06fb), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* BXT A-Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { PCI_VDEVICE(INTEL, 0x0aae), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { PCI_VDEVICE(INTEL, 0x0ab0), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { PCI_VDEVICE(INTEL, 0x0ab2), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { PCI_VDEVICE(INTEL, 0x0ab4), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { PCI_VDEVICE(INTEL, 0x0ab6), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { PCI_VDEVICE(INTEL, 0x0ab8), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { PCI_VDEVICE(INTEL, 0x0aba), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { PCI_VDEVICE(INTEL, 0x0abc), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { PCI_VDEVICE(INTEL, 0x0abe), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { PCI_VDEVICE(INTEL, 0x0ac0), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { PCI_VDEVICE(INTEL, 0x0ac2), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { PCI_VDEVICE(INTEL, 0x0ac4), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { PCI_VDEVICE(INTEL, 0x0ac6), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { PCI_VDEVICE(INTEL, 0x0aee), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* BXT B-Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { PCI_VDEVICE(INTEL, 0x1aac), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { PCI_VDEVICE(INTEL, 0x1aae), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { PCI_VDEVICE(INTEL, 0x1ab0), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { PCI_VDEVICE(INTEL, 0x1ab2), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { PCI_VDEVICE(INTEL, 0x1ab4), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { PCI_VDEVICE(INTEL, 0x1ab6), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { PCI_VDEVICE(INTEL, 0x1ab8), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { PCI_VDEVICE(INTEL, 0x1aba), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { PCI_VDEVICE(INTEL, 0x1abc), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { PCI_VDEVICE(INTEL, 0x1abe), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { PCI_VDEVICE(INTEL, 0x1ac0), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { PCI_VDEVICE(INTEL, 0x1ac2), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { PCI_VDEVICE(INTEL, 0x1ac4), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { PCI_VDEVICE(INTEL, 0x1ac6), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { PCI_VDEVICE(INTEL, 0x1aee), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* EBG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { PCI_VDEVICE(INTEL, 0x1bad), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { PCI_VDEVICE(INTEL, 0x1bae), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* GLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { PCI_VDEVICE(INTEL, 0x31ac), (kernel_ulong_t)&glk_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { PCI_VDEVICE(INTEL, 0x31ae), (kernel_ulong_t)&glk_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { PCI_VDEVICE(INTEL, 0x31b0), (kernel_ulong_t)&glk_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { PCI_VDEVICE(INTEL, 0x31b2), (kernel_ulong_t)&glk_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { PCI_VDEVICE(INTEL, 0x31b4), (kernel_ulong_t)&glk_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { PCI_VDEVICE(INTEL, 0x31b6), (kernel_ulong_t)&glk_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { PCI_VDEVICE(INTEL, 0x31b8), (kernel_ulong_t)&glk_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { PCI_VDEVICE(INTEL, 0x31ba), (kernel_ulong_t)&glk_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { PCI_VDEVICE(INTEL, 0x31bc), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { PCI_VDEVICE(INTEL, 0x31be), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { PCI_VDEVICE(INTEL, 0x31c0), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { PCI_VDEVICE(INTEL, 0x31c2), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { PCI_VDEVICE(INTEL, 0x31c4), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { PCI_VDEVICE(INTEL, 0x31c6), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { PCI_VDEVICE(INTEL, 0x31ee), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* ICL-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { PCI_VDEVICE(INTEL, 0x34a8), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { PCI_VDEVICE(INTEL, 0x34a9), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { PCI_VDEVICE(INTEL, 0x34aa), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { PCI_VDEVICE(INTEL, 0x34ab), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { PCI_VDEVICE(INTEL, 0x34c5), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { PCI_VDEVICE(INTEL, 0x34c6), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { PCI_VDEVICE(INTEL, 0x34c7), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { PCI_VDEVICE(INTEL, 0x34e8), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { PCI_VDEVICE(INTEL, 0x34e9), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { PCI_VDEVICE(INTEL, 0x34ea), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { PCI_VDEVICE(INTEL, 0x34eb), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { PCI_VDEVICE(INTEL, 0x34fb), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* TGL-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { PCI_VDEVICE(INTEL, 0x43a7), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { PCI_VDEVICE(INTEL, 0x43a8), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { PCI_VDEVICE(INTEL, 0x43a9), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { PCI_VDEVICE(INTEL, 0x43aa), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { PCI_VDEVICE(INTEL, 0x43ab), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { PCI_VDEVICE(INTEL, 0x43ad), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { PCI_VDEVICE(INTEL, 0x43ae), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { PCI_VDEVICE(INTEL, 0x43d8), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { PCI_VDEVICE(INTEL, 0x43da), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { PCI_VDEVICE(INTEL, 0x43e8), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { PCI_VDEVICE(INTEL, 0x43e9), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { PCI_VDEVICE(INTEL, 0x43ea), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { PCI_VDEVICE(INTEL, 0x43eb), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { PCI_VDEVICE(INTEL, 0x43fb), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { PCI_VDEVICE(INTEL, 0x43fd), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* EHL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { PCI_VDEVICE(INTEL, 0x4b28), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { PCI_VDEVICE(INTEL, 0x4b29), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { PCI_VDEVICE(INTEL, 0x4b2a), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { PCI_VDEVICE(INTEL, 0x4b2b), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { PCI_VDEVICE(INTEL, 0x4b37), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { PCI_VDEVICE(INTEL, 0x4b44), (kernel_ulong_t)&ehl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { PCI_VDEVICE(INTEL, 0x4b45), (kernel_ulong_t)&ehl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { PCI_VDEVICE(INTEL, 0x4b4b), (kernel_ulong_t)&ehl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { PCI_VDEVICE(INTEL, 0x4b4c), (kernel_ulong_t)&ehl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { PCI_VDEVICE(INTEL, 0x4b4d), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { PCI_VDEVICE(INTEL, 0x4b78), (kernel_ulong_t)&ehl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { PCI_VDEVICE(INTEL, 0x4b79), (kernel_ulong_t)&ehl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { PCI_VDEVICE(INTEL, 0x4b7a), (kernel_ulong_t)&ehl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { PCI_VDEVICE(INTEL, 0x4b7b), (kernel_ulong_t)&ehl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* JSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { PCI_VDEVICE(INTEL, 0x4da8), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { PCI_VDEVICE(INTEL, 0x4da9), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { PCI_VDEVICE(INTEL, 0x4daa), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { PCI_VDEVICE(INTEL, 0x4dab), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { PCI_VDEVICE(INTEL, 0x4dc5), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { PCI_VDEVICE(INTEL, 0x4dc6), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { PCI_VDEVICE(INTEL, 0x4dc7), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { PCI_VDEVICE(INTEL, 0x4de8), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { PCI_VDEVICE(INTEL, 0x4de9), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { PCI_VDEVICE(INTEL, 0x4dea), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { PCI_VDEVICE(INTEL, 0x4deb), (kernel_ulong_t)&bxt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { PCI_VDEVICE(INTEL, 0x4dfb), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* APL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { PCI_VDEVICE(INTEL, 0x5aac), (kernel_ulong_t)&apl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { PCI_VDEVICE(INTEL, 0x5aae), (kernel_ulong_t)&apl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { PCI_VDEVICE(INTEL, 0x5ab0), (kernel_ulong_t)&apl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { PCI_VDEVICE(INTEL, 0x5ab2), (kernel_ulong_t)&apl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { PCI_VDEVICE(INTEL, 0x5ab4), (kernel_ulong_t)&apl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { PCI_VDEVICE(INTEL, 0x5ab6), (kernel_ulong_t)&apl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { PCI_VDEVICE(INTEL, 0x5ab8), (kernel_ulong_t)&apl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { PCI_VDEVICE(INTEL, 0x5aba), (kernel_ulong_t)&apl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { PCI_VDEVICE(INTEL, 0x5abc), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { PCI_VDEVICE(INTEL, 0x5abe), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { PCI_VDEVICE(INTEL, 0x5ac0), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { PCI_VDEVICE(INTEL, 0x5ac2), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { PCI_VDEVICE(INTEL, 0x5ac4), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { PCI_VDEVICE(INTEL, 0x5ac6), (kernel_ulong_t)&bxt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { PCI_VDEVICE(INTEL, 0x5aee), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* LKF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { PCI_VDEVICE(INTEL, 0x98a8), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { PCI_VDEVICE(INTEL, 0x98a9), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { PCI_VDEVICE(INTEL, 0x98c7), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* SPT-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { PCI_VDEVICE(INTEL, 0x9d29), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { PCI_VDEVICE(INTEL, 0x9d2a), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { PCI_VDEVICE(INTEL, 0x9d60), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { PCI_VDEVICE(INTEL, 0x9d61), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { PCI_VDEVICE(INTEL, 0x9d62), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { PCI_VDEVICE(INTEL, 0x9d63), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { PCI_VDEVICE(INTEL, 0x9d64), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { PCI_VDEVICE(INTEL, 0x9d65), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { PCI_VDEVICE(INTEL, 0x9d66), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* CNL-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { PCI_VDEVICE(INTEL, 0x9da8), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { PCI_VDEVICE(INTEL, 0x9da9), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { PCI_VDEVICE(INTEL, 0x9daa), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { PCI_VDEVICE(INTEL, 0x9dab), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { PCI_VDEVICE(INTEL, 0x9dc7), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { PCI_VDEVICE(INTEL, 0x9de8), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* TGL-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { PCI_VDEVICE(INTEL, 0xa0a8), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { PCI_VDEVICE(INTEL, 0xa0a9), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { PCI_VDEVICE(INTEL, 0xa0aa), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { PCI_VDEVICE(INTEL, 0xa0ab), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { PCI_VDEVICE(INTEL, 0xa0c5), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { PCI_VDEVICE(INTEL, 0xa0c6), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { PCI_VDEVICE(INTEL, 0xa0c7), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { PCI_VDEVICE(INTEL, 0xa0d8), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { PCI_VDEVICE(INTEL, 0xa0d9), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { PCI_VDEVICE(INTEL, 0xa0da), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { PCI_VDEVICE(INTEL, 0xa0db), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { PCI_VDEVICE(INTEL, 0xa0dc), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { PCI_VDEVICE(INTEL, 0xa0dd), (kernel_ulong_t)&bxt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { PCI_VDEVICE(INTEL, 0xa0de), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { PCI_VDEVICE(INTEL, 0xa0df), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { PCI_VDEVICE(INTEL, 0xa0e8), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { PCI_VDEVICE(INTEL, 0xa0e9), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { PCI_VDEVICE(INTEL, 0xa0ea), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { PCI_VDEVICE(INTEL, 0xa0eb), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { PCI_VDEVICE(INTEL, 0xa0fb), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { PCI_VDEVICE(INTEL, 0xa0fd), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { PCI_VDEVICE(INTEL, 0xa0fe), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* SPT-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { PCI_VDEVICE(INTEL, 0xa129), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { PCI_VDEVICE(INTEL, 0xa12a), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { PCI_VDEVICE(INTEL, 0xa160), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { PCI_VDEVICE(INTEL, 0xa162), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* KBL-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* CNL-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { PCI_VDEVICE(INTEL, 0xa328), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { PCI_VDEVICE(INTEL, 0xa329), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { PCI_VDEVICE(INTEL, 0xa32a), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { PCI_VDEVICE(INTEL, 0xa32b), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { PCI_VDEVICE(INTEL, 0xa347), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&cnl_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { PCI_VDEVICE(INTEL, 0xa37b), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* CML-V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { PCI_VDEVICE(INTEL, 0xa3a7), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { PCI_VDEVICE(INTEL, 0xa3a8), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { PCI_VDEVICE(INTEL, 0xa3a9), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { PCI_VDEVICE(INTEL, 0xa3aa), (kernel_ulong_t)&spt_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { PCI_VDEVICE(INTEL, 0xa3e0), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { PCI_VDEVICE(INTEL, 0xa3e1), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { PCI_VDEVICE(INTEL, 0xa3e2), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { PCI_VDEVICE(INTEL, 0xa3e3), (kernel_ulong_t)&spt_i2c_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { PCI_VDEVICE(INTEL, 0xa3e6), (kernel_ulong_t)&spt_uart_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct pci_driver intel_lpss_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .name = "intel-lpss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .id_table = intel_lpss_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .probe = intel_lpss_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .remove = intel_lpss_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .pm = &intel_lpss_pci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) module_pci_driver(intel_lpss_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_DESCRIPTION("Intel LPSS PCI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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