^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device driver for MFD hi655x PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Hisilicon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Chen Feng <puck.chen@hisilicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Fei Wang <w.f@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/hi655x-pmic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct regmap_irq hi655x_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { .reg_offset = 0, .mask = OTMP_D1R_INT_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { .reg_offset = 0, .mask = VSYS_2P5_R_INT_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { .reg_offset = 0, .mask = VSYS_UV_D3R_INT_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { .reg_offset = 0, .mask = PWRON_D4SR_INT_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { .reg_offset = 0, .mask = PWRON_D20F_INT_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { .reg_offset = 0, .mask = PWRON_D20R_INT_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { .reg_offset = 0, .mask = RESERVE_INT_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct regmap_irq_chip hi655x_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .name = "hi655x-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .irqs = hi655x_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .num_regs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .num_irqs = ARRAY_SIZE(hi655x_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .status_base = HI655X_IRQ_STAT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .ack_base = HI655X_IRQ_STAT_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .mask_base = HI655X_IRQ_MASK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct regmap_config hi655x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .reg_stride = HI655X_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .max_register = HI655X_BUS_ADDR(0x400) - HI655X_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct resource pwrkey_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "down",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .start = PWRON_D20R_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .end = PWRON_D20R_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .start = PWRON_D20F_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .end = PWRON_D20F_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "hold 4s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .start = PWRON_D4SR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .end = PWRON_D4SR_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct mfd_cell hi655x_pmic_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .name = "hi65xx-powerkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .num_resources = ARRAY_SIZE(pwrkey_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .resources = &pwrkey_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .name = "hi655x-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { .name = "hi655x-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void hi655x_local_irq_clear(struct regmap *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regmap_write(map, HI655X_ANA_IRQM_BASE, HI655X_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) for (i = 0; i < HI655X_IRQ_ARRAY; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) regmap_write(map, HI655X_IRQ_STAT_BASE + i * HI655X_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) HI655X_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int hi655x_pmic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct hi655x_pmic *pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pmic->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pmic->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) base = devm_ioremap_resource(dev, pmic->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) &hi655x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (IS_ERR(pmic->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return PTR_ERR(pmic->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) regmap_read(pmic->regmap, HI655X_BUS_ADDR(HI655X_VER_REG), &pmic->ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if ((pmic->ver < PMU_VER_START) || (pmic->ver > PMU_VER_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_warn(dev, "PMU version %d unsupported\n", pmic->ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) hi655x_local_irq_clear(pmic->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pmic->gpio = of_get_named_gpio(np, "pmic-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!gpio_is_valid(pmic->gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_err(dev, "Failed to get the pmic-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = devm_gpio_request_one(dev, pmic->gpio, GPIOF_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "hi655x_pmic_irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_err(dev, "Failed to request gpio %d ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pmic->gpio, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = regmap_add_irq_chip(pmic->regmap, gpio_to_irq(pmic->gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IRQF_TRIGGER_LOW | IRQF_NO_SUSPEND, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &hi655x_irq_chip, &pmic->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(dev, "Failed to obtain 'hi655x_pmic_irq' %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) platform_set_drvdata(pdev, pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, hi655x_pmic_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ARRAY_SIZE(hi655x_pmic_devs), NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) regmap_irq_get_domain(pmic->irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(dev, "Failed to register device %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) regmap_del_irq_chip(gpio_to_irq(pmic->gpio), pmic->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int hi655x_pmic_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct hi655x_pmic *pmic = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_del_irq_chip(gpio_to_irq(pmic->gpio), pmic->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mfd_remove_devices(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct of_device_id hi655x_pmic_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .compatible = "hisilicon,hi655x-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_DEVICE_TABLE(of, hi655x_pmic_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct platform_driver hi655x_pmic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = "hi655x-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .of_match_table = of_match_ptr(hi655x_pmic_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .probe = hi655x_pmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .remove = hi655x_pmic_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) module_platform_driver(hi655x_pmic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MODULE_AUTHOR("Chen Feng <puck.chen@hisilicon.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_DESCRIPTION("Hisilicon hi655x PMIC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags