^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/imx25-tsadc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static struct regmap_config mx25_tsadc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .max_register = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void mx25_tsadc_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) regmap_read(tsadc->regs, MX25_TSC_TGSR, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (status & MX25_TGSR_GCQ_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) generic_handle_irq(irq_find_mapping(tsadc->domain, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (status & MX25_TGSR_TCQ_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) generic_handle_irq(irq_find_mapping(tsadc->domain, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int mx25_tsadc_domain_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct mx25_tsadc *tsadc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) irq_set_chip_data(irq, tsadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) irq_set_chip_and_handler(irq, &dummy_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct irq_domain_ops mx25_tsadc_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .map = mx25_tsadc_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int mx25_tsadc_setup_irq(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct mx25_tsadc *tsadc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tsadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (!tsadc->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_err(dev, "Failed to add irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) irq_set_chained_handler_and_data(irq, mx25_tsadc_irq_handler, tsadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void mx25_tsadc_setup_clk(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mx25_tsadc *tsadc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * According to the datasheet the ADC clock should never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * exceed 1,75 MHz. Base clock is the IPG and the ADC unit uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * a funny clock divider. To keep the ADC conversion time constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * adapt the ADC internal clock divider to the IPG clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_dbg(&pdev->dev, "Found master clock at %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clk_get_rate(tsadc->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* adc clock = IPG clock / (2 * div + 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk_div -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clk_div /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * the ADC clock divider changes its behaviour when values below 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * are used: it is fixed to "/ 10" in this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk_div = max_t(unsigned, 4, clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_dbg(&pdev->dev, "Resulting ADC conversion clock at %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clk_get_rate(tsadc->clk) / (2 * clk_div + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regmap_update_bits(tsadc->regs, MX25_TSC_TGCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MX25_TGCR_ADCCLKCFG(0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MX25_TGCR_ADCCLKCFG(clk_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int mx25_tsadc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mx25_tsadc *tsadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) tsadc = devm_kzalloc(dev, sizeof(*tsadc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!tsadc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) iomem = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (IS_ERR(iomem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return PTR_ERR(iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) tsadc->regs = devm_regmap_init_mmio(dev, iomem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) &mx25_tsadc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ERR(tsadc->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_err(dev, "Failed to initialize regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return PTR_ERR(tsadc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tsadc->clk = devm_clk_get(dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (IS_ERR(tsadc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(dev, "Failed to get ipg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return PTR_ERR(tsadc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* setup clock according to the datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mx25_tsadc_setup_clk(pdev, tsadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Enable clock and reset the component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_CLK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MX25_TGCR_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_TSC_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MX25_TGCR_TSC_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Setup powersaving mode, but enable internal reference voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_POWERMODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MX25_TGCR_POWERMODE_SAVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_INTREFEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MX25_TGCR_INTREFEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = mx25_tsadc_setup_irq(pdev, tsadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) platform_set_drvdata(pdev, tsadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return devm_of_platform_populate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int mx25_tsadc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct mx25_tsadc *tsadc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) irq_set_chained_handler_and_data(irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) irq_domain_remove(tsadc->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct of_device_id mx25_tsadc_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .compatible = "fsl,imx25-tsadc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_DEVICE_TABLE(of, mx25_tsadc_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct platform_driver mx25_tsadc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .name = "mx25-tsadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .of_match_table = of_match_ptr(mx25_tsadc_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .probe = mx25_tsadc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .remove = mx25_tsadc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) module_platform_driver(mx25_tsadc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_DESCRIPTION("MFD for ADC/TSC for Freescale mx25");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_ALIAS("platform:mx25-tsadc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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