^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Inha Song <ideal.song@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Sylwester Nawrocki <s.nawrocki@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Samsung Exynos SoC series Low Power Audio Subsystem driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This module provides regmap for the Top SFR region and instantiates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * devices for IP blocks like DMAC, I2S, UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/soc/samsung/exynos-regs-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* LPASS Top register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SFR_LPASS_CORE_SW_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPASS_SB_SW_RESET BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPASS_UART_SW_RESET BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPASS_PCM_SW_RESET BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPASS_I2S_SW_RESET BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPASS_WDT1_SW_RESET BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPASS_WDT0_SW_RESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPASS_TIMER_SW_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPASS_MEM_SW_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPASS_DMA_SW_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SFR_LPASS_INTR_CA5_MASK 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SFR_LPASS_INTR_CPU_MASK 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPASS_INTR_APM BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPASS_INTR_MIF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPASS_INTR_TIMER BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPASS_INTR_DMA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPASS_INTR_GPIO BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPASS_INTR_I2S BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPASS_INTR_PCM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LPASS_INTR_SLIMBUS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LPASS_INTR_UART BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LPASS_INTR_SFR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct exynos_lpass {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* pointer to the LPASS TOP regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct regmap *top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *sfr0_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void exynos_lpass_enable(struct exynos_lpass *lpass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) clk_prepare_enable(lpass->sfr0_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Unmask SFR, DMA and I2S interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) LPASS_INTR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void exynos_lpass_disable(struct exynos_lpass *lpass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Mask any unmasked IP interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) clk_disable_unprepare(lpass->sfr0_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct regmap_config exynos_lpass_reg_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .max_register = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int exynos_lpass_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct exynos_lpass *lpass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __iomem *base_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!lpass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) base_top = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (IS_ERR(base_top))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return PTR_ERR(base_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (IS_ERR(lpass->sfr0_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return PTR_ERR(lpass->sfr0_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) lpass->top = regmap_init_mmio(dev, base_top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &exynos_lpass_reg_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (IS_ERR(lpass->top)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) dev_err(dev, "LPASS top regmap initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return PTR_ERR(lpass->top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) platform_set_drvdata(pdev, lpass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) exynos_lpass_enable(lpass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return devm_of_platform_populate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int exynos_lpass_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct exynos_lpass *lpass = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) exynos_lpass_disable(lpass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) exynos_lpass_disable(lpass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) regmap_exit(lpass->top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int __maybe_unused exynos_lpass_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct exynos_lpass *lpass = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) exynos_lpass_disable(lpass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int __maybe_unused exynos_lpass_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct exynos_lpass *lpass = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) exynos_lpass_enable(lpass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct dev_pm_ops lpass_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct of_device_id exynos_lpass_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .compatible = "samsung,exynos5433-lpass" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct platform_driver exynos_lpass_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "exynos-lpass",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .pm = &lpass_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .of_match_table = exynos_lpass_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .probe = exynos_lpass_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .remove = exynos_lpass_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) module_platform_driver(exynos_lpass_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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