Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) STMicroelectronics 2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) ST-Ericsson SA 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * PRCM Unit registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef __DB8500_PRCMU_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define __DB8500_PRCMU_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PRCM_ACLK_MGT		(0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PRCM_SVAMMCSPCLK_MGT	(0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PRCM_SIAMMDSPCLK_MGT	(0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PRCM_SGACLK_MGT		(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PRCM_UARTCLK_MGT	(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PRCM_MSP02CLK_MGT	(0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PRCM_I2CCLK_MGT		(0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PRCM_SDMMCCLK_MGT	(0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PRCM_SLIMCLK_MGT	(0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PRCM_PER1CLK_MGT	(0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PRCM_PER2CLK_MGT	(0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PRCM_PER3CLK_MGT	(0x034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PRCM_PER5CLK_MGT	(0x038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PRCM_PER6CLK_MGT	(0x03C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PRCM_PER7CLK_MGT	(0x040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PRCM_LCDCLK_MGT		(0x044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PRCM_BMLCLK_MGT		(0x04C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PRCM_HSITXCLK_MGT	(0x050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PRCM_HSIRXCLK_MGT	(0x054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PRCM_HDMICLK_MGT	(0x058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PRCM_APEATCLK_MGT	(0x05C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PRCM_APETRACECLK_MGT	(0x060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PRCM_MCDECLK_MGT	(0x064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PRCM_IPI2CCLK_MGT	(0x068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PRCM_DSIALTCLK_MGT	(0x06C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PRCM_DMACLK_MGT		(0x074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PRCM_B2R2CLK_MGT	(0x078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PRCM_TVCLK_MGT		(0x07C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PRCM_UNIPROCLK_MGT	(0x278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PRCM_SSPCLK_MGT		(0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PRCM_RNGCLK_MGT		(0x284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PRCM_UICCCLK_MGT	(0x27C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PRCM_MSP1CLK_MGT	(0x288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PRCM_ARM_PLLDIVPS	(prcmu_base + 0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE		0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PRCM_ARM_PLLDIVPS_MAX_MASK		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PRCM_PLLARM_LOCKP       (prcmu_base + 0x0a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PRCM_ARM_CHGCLKREQ	(prcmu_base + 0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PRCM_PLLARM_ENABLE	(prcmu_base + 0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PRCM_ARMCLKFIX_MGT	(prcmu_base + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PRCM_A9PL_FORCE_CLKEN	(prcmu_base + 0x19C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PRCM_A9_RESETN_CLR	(prcmu_base + 0x1f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PRCM_A9_RESETN_SET	(prcmu_base + 0x1f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PRCM_ARM_LS_CLAMP	(prcmu_base + 0x30c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PRCM_SRAM_A9		(prcmu_base + 0x308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* CPU mailbox registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PRCM_MBOX_CPU_VAL	(prcmu_base + 0x0fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PRCM_MBOX_CPU_SET	(prcmu_base + 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PRCM_MBOX_CPU_CLR	(prcmu_base + 0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PRCM_HOSTACCESS_REQ	(prcmu_base + 0x334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PRCM_HOSTACCESS_REQ_WAKE_REQ	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define ARM_WAKEUP_MODEM	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PRCM_ARM_IT1_CLR	(prcmu_base + 0x48C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PRCM_ARM_IT1_VAL	(prcmu_base + 0x494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PRCM_HOLD_EVT		(prcmu_base + 0x174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define PRCM_MOD_AWAKE_STATUS	(prcmu_base + 0x4A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PRCM_ITSTATUS0		(prcmu_base + 0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PRCM_ITSTATUS1		(prcmu_base + 0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PRCM_ITSTATUS2		(prcmu_base + 0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PRCM_ITSTATUS3		(prcmu_base + 0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PRCM_ITSTATUS4		(prcmu_base + 0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PRCM_ITSTATUS5		(prcmu_base + 0x484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PRCM_ITCLEAR5		(prcmu_base + 0x488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PRCM_ARMIT_MASKXP70_IT	(prcmu_base + 0x1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* System reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PRCM_APE_SOFTRST	(prcmu_base + 0x228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Level shifter and clamp control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PRCM_MMIP_LS_CLAMP_SET     (prcmu_base + 0x420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PRCM_MMIP_LS_CLAMP_CLR     (prcmu_base + 0x424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI	BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* PRCMU clock/PLL/reset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PRCM_PLLSOC0_FREQ	   (prcmu_base + 0x080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PRCM_PLLSOC1_FREQ	   (prcmu_base + 0x084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PRCM_PLLARM_FREQ	   (prcmu_base + 0x088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PRCM_PLLDDR_FREQ	   (prcmu_base + 0x08C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PRCM_PLL_FREQ_D_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PRCM_PLL_FREQ_D_MASK	BITS(0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PRCM_PLL_FREQ_N_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PRCM_PLL_FREQ_N_MASK	BITS(8, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PRCM_PLL_FREQ_R_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PRCM_PLL_FREQ_R_MASK	BITS(16, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PRCM_PLL_FREQ_SELDIV2	BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PRCM_PLL_FREQ_DIV2EN	BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PRCM_PLLDSI_FREQ           (prcmu_base + 0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PRCM_PLLDSI_ENABLE         (prcmu_base + 0x504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PRCM_PLLDSI_LOCKP          (prcmu_base + 0x508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PRCM_DSI_PLLOUT_SEL        (prcmu_base + 0x530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PRCM_DSITVCLK_DIV          (prcmu_base + 0x52C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PRCM_PLLDSI_LOCKP          (prcmu_base + 0x508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PRCM_APE_RESETN_SET        (prcmu_base + 0x1E4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PRCM_APE_RESETN_CLR        (prcmu_base + 0x1E8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK	BITS(0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK	BITS(8, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PRCM_DSI_PLLOUT_SEL_OFF		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PRCM_DSI_PLLOUT_SEL_PHI		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PRCM_DSI_PLLOUT_SEL_PHI_2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PRCM_DSI_PLLOUT_SEL_PHI_4	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK		BITS(0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK		BITS(8, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK		BITS(16, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN		BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN		BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN		BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PRCM_CLKOCR		   (prcmu_base + 0x1CC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PRCM_CLKOCR_CLKOUT0_REF_CLK	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PRCM_CLKOCR_CLKOUT0_MASK	BITS(0, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PRCM_CLKOCR_CLKOUT1_REF_CLK	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PRCM_CLKOCR_CLKOUT1_MASK	BITS(16, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* ePOD and memory power signal control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PRCM_EPOD_C_SET            (prcmu_base + 0x410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PRCM_SRAM_LS_SLEEP         (prcmu_base + 0x304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Debug power control unit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PRCM_POWER_STATE_SET       (prcmu_base + 0x254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Miscellaneous unit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PRCM_DSI_SW_RESET          (prcmu_base + 0x324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PRCM_GPIOCR                (prcmu_base + 0x138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PRCM_GPIOCR_DBG_STM_MOD_CMD1            0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PRCM_GPIOCR_DBG_UARTMOD_CMD0            0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* PRCMU HW semaphore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PRCM_SEM                   (prcmu_base + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PRCM_SEM_PRCM_SEM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PRCM_TCR                   (prcmu_base + 0x1C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PRCM_TCR_TENSEL_MASK       BITS(0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PRCM_TCR_STOP_TIMERS       BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PRCM_TCR_DOZE_MODE         BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PRCM_CLKOCR_CLKODIV0_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PRCM_CLKOCR_CLKODIV0_MASK	BITS(0, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PRCM_CLKOCR_CLKOSEL0_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PRCM_CLKOCR_CLKOSEL0_MASK	BITS(6, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PRCM_CLKOCR_CLKODIV1_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PRCM_CLKOCR_CLKODIV1_MASK	BITS(16, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PRCM_CLKOCR_CLKOSEL1_SHIFT	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PRCM_CLKOCR_CLKOSEL1_MASK	BITS(22, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PRCM_CLKOCR_CLK1TYPE		BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PRCM_CLK_MGT_CLKPLLDIV_MASK		BITS(0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PRCM_CLK_MGT_CLKPLLSW_SOC0		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PRCM_CLK_MGT_CLKPLLSW_SOC1		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PRCM_CLK_MGT_CLKPLLSW_DDR		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PRCM_CLK_MGT_CLKPLLSW_MASK		BITS(5, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PRCM_CLK_MGT_CLKEN			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PRCM_CLK_MGT_CLK38			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PRCM_CLK_MGT_CLK38DIV			BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* GPIOCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PRCM_GPIOCR_SPI2_SELECT BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PRCM_DDR_SUBSYS_APE_MINBW	(prcmu_base + 0x438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PRCM_CGATING_BYPASS		(prcmu_base + 0x134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PRCM_CGATING_BYPASS_ICN2	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Miscellaneous unit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PRCM_RESOUTN_SET		(prcmu_base + 0x214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PRCM_RESOUTN_CLR		(prcmu_base + 0x218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* System reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PRCM_APE_SOFTRST		(prcmu_base + 0x228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif /* __DB8500_PRCMU_REGS_H */