Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DA9052 interrupt support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Fabio Estevam <fabio.estevam@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on arizona-irq.c, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright 2012 Wolfson Microelectronics plc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mfd/da9052/da9052.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/mfd/da9052/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DA9052_NUM_IRQ_REGS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DA9052_IRQ_MASK_POS_1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DA9052_IRQ_MASK_POS_2		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DA9052_IRQ_MASK_POS_3		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DA9052_IRQ_MASK_POS_4		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DA9052_IRQ_MASK_POS_5		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DA9052_IRQ_MASK_POS_6		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DA9052_IRQ_MASK_POS_7		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DA9052_IRQ_MASK_POS_8		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static const struct regmap_irq da9052_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	[DA9052_IRQ_DCIN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.mask = DA9052_IRQ_MASK_POS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	[DA9052_IRQ_VBUS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.mask = DA9052_IRQ_MASK_POS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	[DA9052_IRQ_DCINREM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.mask = DA9052_IRQ_MASK_POS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	[DA9052_IRQ_VBUSREM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.mask = DA9052_IRQ_MASK_POS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	[DA9052_IRQ_VDDLOW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.mask = DA9052_IRQ_MASK_POS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	[DA9052_IRQ_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.mask = DA9052_IRQ_MASK_POS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[DA9052_IRQ_SEQRDY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.mask = DA9052_IRQ_MASK_POS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	[DA9052_IRQ_COMP1V2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.reg_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.mask = DA9052_IRQ_MASK_POS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	[DA9052_IRQ_NONKEY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.mask = DA9052_IRQ_MASK_POS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	[DA9052_IRQ_IDFLOAT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.mask = DA9052_IRQ_MASK_POS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[DA9052_IRQ_IDGND] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.mask = DA9052_IRQ_MASK_POS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	[DA9052_IRQ_CHGEND] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.mask = DA9052_IRQ_MASK_POS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	[DA9052_IRQ_TBAT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.mask = DA9052_IRQ_MASK_POS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	[DA9052_IRQ_ADC_EOM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.mask = DA9052_IRQ_MASK_POS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	[DA9052_IRQ_PENDOWN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.mask = DA9052_IRQ_MASK_POS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[DA9052_IRQ_TSIREADY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.mask = DA9052_IRQ_MASK_POS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	[DA9052_IRQ_GPI0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.mask = DA9052_IRQ_MASK_POS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	[DA9052_IRQ_GPI1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.mask = DA9052_IRQ_MASK_POS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	[DA9052_IRQ_GPI2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.mask = DA9052_IRQ_MASK_POS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	[DA9052_IRQ_GPI3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.mask = DA9052_IRQ_MASK_POS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	[DA9052_IRQ_GPI4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.mask = DA9052_IRQ_MASK_POS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	[DA9052_IRQ_GPI5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.mask = DA9052_IRQ_MASK_POS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	[DA9052_IRQ_GPI6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.mask = DA9052_IRQ_MASK_POS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	[DA9052_IRQ_GPI7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.mask = DA9052_IRQ_MASK_POS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	[DA9052_IRQ_GPI8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.mask = DA9052_IRQ_MASK_POS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	[DA9052_IRQ_GPI9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.mask = DA9052_IRQ_MASK_POS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	[DA9052_IRQ_GPI10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.mask = DA9052_IRQ_MASK_POS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	[DA9052_IRQ_GPI11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.mask = DA9052_IRQ_MASK_POS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	[DA9052_IRQ_GPI12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.mask = DA9052_IRQ_MASK_POS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	[DA9052_IRQ_GPI13] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.mask = DA9052_IRQ_MASK_POS_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	[DA9052_IRQ_GPI14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.mask = DA9052_IRQ_MASK_POS_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	[DA9052_IRQ_GPI15] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.mask = DA9052_IRQ_MASK_POS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct regmap_irq_chip da9052_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.name = "da9052_irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.status_base = DA9052_EVENT_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.mask_base = DA9052_IRQ_MASK_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.ack_base = DA9052_EVENT_A_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.num_regs = DA9052_NUM_IRQ_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.irqs = da9052_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.num_irqs = ARRAY_SIZE(da9052_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int da9052_map_irq(struct da9052 *da9052, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return regmap_irq_get_virq(da9052->irq_data, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int da9052_enable_irq(struct da9052 *da9052, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	irq = da9052_map_irq(da9052, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) EXPORT_SYMBOL_GPL(da9052_enable_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int da9052_disable_irq(struct da9052 *da9052, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	irq = da9052_map_irq(da9052, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) EXPORT_SYMBOL_GPL(da9052_disable_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int da9052_disable_irq_nosync(struct da9052 *da9052, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	irq = da9052_map_irq(da9052, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) EXPORT_SYMBOL_GPL(da9052_disable_irq_nosync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			   irq_handler_t handler, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	irq = da9052_map_irq(da9052, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return request_threaded_irq(irq, NULL, handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				     IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				     name, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) EXPORT_SYMBOL_GPL(da9052_request_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void da9052_free_irq(struct da9052 *da9052, int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	irq = da9052_map_irq(da9052, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	free_irq(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) EXPORT_SYMBOL_GPL(da9052_free_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static irqreturn_t da9052_auxadc_irq(int irq, void *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct da9052 *da9052 = irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	complete(&da9052->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int da9052_irq_init(struct da9052 *da9052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ret = regmap_add_irq_chip(da9052->regmap, da9052->chip_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				  IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				  -1, &da9052_regmap_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				  &da9052->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		dev_err(da9052->dev, "regmap_add_irq_chip failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		goto regmap_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	enable_irq_wake(da9052->chip_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = da9052_request_irq(da9052, DA9052_IRQ_ADC_EOM, "adc-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			    da9052_auxadc_irq, da9052);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		dev_err(da9052->dev, "DA9052_IRQ_ADC_EOM failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		goto request_irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) request_irq_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) regmap_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int da9052_irq_exit(struct da9052 *da9052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	da9052_free_irq(da9052, DA9052_IRQ_ADC_EOM, da9052);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	regmap_del_irq_chip(da9052->chip_irq, da9052->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }