^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MFD core driver for the X-Powers' Power Management ICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * as well as configurable GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file contains the interface independent core functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2014 Carlo Caione
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Author: Carlo Caione <carlo@caione.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/axp20x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AXP20X_OFF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const char * const axp20x_model_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "AXP152",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "AXP202",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "AXP209",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "AXP221",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "AXP223",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "AXP288",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "AXP803",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "AXP806",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "AXP809",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "AXP813",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct regmap_range axp152_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct regmap_range axp152_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct regmap_access_table axp152_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .yes_ranges = axp152_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct regmap_access_table axp152_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .yes_ranges = axp152_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct regmap_range axp20x_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct regmap_range axp20x_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct regmap_access_table axp20x_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .yes_ranges = axp20x_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct regmap_access_table axp20x_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .yes_ranges = axp20x_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* AXP22x ranges are shared with the AXP809, as they cover the same range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct regmap_range axp22x_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) regmap_reg_range(AXP20X_CHRG_CTRL1, AXP22X_CHRG_CTRL3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct regmap_range axp22x_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) regmap_reg_range(AXP22X_PMIC_TEMP_H, AXP20X_IPSOUT_V_HIGH_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct regmap_access_table axp22x_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .yes_ranges = axp22x_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct regmap_access_table axp22x_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .yes_ranges = axp22x_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* AXP288 ranges are shared with the AXP803, as they cover the same range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct regmap_range axp288_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct regmap_range axp288_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regmap_reg_range(AXP22X_PWR_OUT_CTRL1, AXP22X_ALDO3_V_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) regmap_reg_range(AXP20X_GPIO1_CTRL, AXP22X_GPIO_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct regmap_access_table axp288_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .yes_ranges = axp288_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct regmap_access_table axp288_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .yes_ranges = axp288_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct regmap_range axp806_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct regmap_range axp806_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct regmap_access_table axp806_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .yes_ranges = axp806_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct regmap_access_table axp806_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .yes_ranges = axp806_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct resource axp152_pek_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct resource axp20x_ac_power_supply_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct resource axp20x_pek_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct resource axp20x_usb_power_supply_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct resource axp22x_usb_power_supply_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* AXP803 and AXP813/AXP818 share the same interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct resource axp803_usb_power_supply_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct resource axp22x_pek_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct resource axp288_power_button_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKP, "PEK_DBR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKN, "PEK_DBF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct resource axp288_fuel_gauge_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DEFINE_RES_IRQ(AXP288_IRQ_QWBTU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DEFINE_RES_IRQ(AXP288_IRQ_WBTU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DEFINE_RES_IRQ(AXP288_IRQ_QWBTO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DEFINE_RES_IRQ(AXP288_IRQ_WBTO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DEFINE_RES_IRQ(AXP288_IRQ_WL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DEFINE_RES_IRQ(AXP288_IRQ_WL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct resource axp803_pek_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct resource axp806_pek_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_RISE, "PEK_DBR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DEFINE_RES_IRQ_NAMED(AXP806_IRQ_POK_FALL, "PEK_DBF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct resource axp809_pek_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct regmap_config axp152_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .wr_table = &axp152_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .volatile_table = &axp152_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .max_register = AXP152_PWM1_DUTY_CYCLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct regmap_config axp20x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .wr_table = &axp20x_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .volatile_table = &axp20x_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct regmap_config axp22x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .wr_table = &axp22x_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .volatile_table = &axp22x_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .max_register = AXP22X_BATLOW_THRES1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const struct regmap_config axp288_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .wr_table = &axp288_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .volatile_table = &axp288_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .max_register = AXP288_FG_TUNE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct regmap_config axp806_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .wr_table = &axp806_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .volatile_table = &axp806_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .max_register = AXP806_REG_ADDR_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct regmap_irq axp152_regmap_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct regmap_irq axp20x_regmap_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct regmap_irq axp22x_regmap_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* some IRQs are compatible with axp20x models */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct regmap_irq axp288_regmap_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct regmap_irq axp803_regmap_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) INIT_REGMAP_IRQ(AXP803, ACIN_OVER_V, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) INIT_REGMAP_IRQ(AXP803, ACIN_PLUGIN, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) INIT_REGMAP_IRQ(AXP803, ACIN_REMOVAL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) INIT_REGMAP_IRQ(AXP803, VBUS_OVER_V, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) INIT_REGMAP_IRQ(AXP803, VBUS_PLUGIN, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) INIT_REGMAP_IRQ(AXP803, VBUS_REMOVAL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) INIT_REGMAP_IRQ(AXP803, BATT_PLUGIN, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) INIT_REGMAP_IRQ(AXP803, BATT_REMOVAL, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) INIT_REGMAP_IRQ(AXP803, BATT_ENT_ACT_MODE, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) INIT_REGMAP_IRQ(AXP803, BATT_EXIT_ACT_MODE, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) INIT_REGMAP_IRQ(AXP803, CHARG, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) INIT_REGMAP_IRQ(AXP803, CHARG_DONE, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_HIGH_END, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) INIT_REGMAP_IRQ(AXP803, BATT_CHG_TEMP_LOW_END, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_HIGH_END, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) INIT_REGMAP_IRQ(AXP803, BATT_ACT_TEMP_LOW_END, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) INIT_REGMAP_IRQ(AXP803, DIE_TEMP_HIGH, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) INIT_REGMAP_IRQ(AXP803, GPADC, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) INIT_REGMAP_IRQ(AXP803, LOW_PWR_LVL2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) INIT_REGMAP_IRQ(AXP803, TIMER, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) INIT_REGMAP_IRQ(AXP803, PEK_RIS_EDGE, 4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) INIT_REGMAP_IRQ(AXP803, PEK_FAL_EDGE, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) INIT_REGMAP_IRQ(AXP803, PEK_SHORT, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) INIT_REGMAP_IRQ(AXP803, PEK_LONG, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) INIT_REGMAP_IRQ(AXP803, PEK_OVER_OFF, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) INIT_REGMAP_IRQ(AXP803, GPIO1_INPUT, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) INIT_REGMAP_IRQ(AXP803, GPIO0_INPUT, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) INIT_REGMAP_IRQ(AXP803, BC_USB_CHNG, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) INIT_REGMAP_IRQ(AXP803, MV_CHNG, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct regmap_irq axp806_regmap_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) INIT_REGMAP_IRQ(AXP806, POK_LONG, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) INIT_REGMAP_IRQ(AXP806, POK_SHORT, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) INIT_REGMAP_IRQ(AXP806, POK_FALL, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) INIT_REGMAP_IRQ(AXP806, POK_RISE, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const struct regmap_irq axp809_regmap_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct regmap_irq_chip axp152_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .name = "axp152_irq_chip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .status_base = AXP152_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .ack_base = AXP152_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .mask_base = AXP152_IRQ1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .irqs = axp152_regmap_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .num_regs = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .name = "axp20x_irq_chip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .status_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .ack_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mask_base = AXP20X_IRQ1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .irqs = axp20x_regmap_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_regs = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "axp22x_irq_chip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .status_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .ack_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .mask_base = AXP20X_IRQ1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .irqs = axp22x_regmap_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .num_regs = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct regmap_irq_chip axp288_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .name = "axp288_irq_chip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .status_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .ack_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .mask_base = AXP20X_IRQ1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .irqs = axp288_regmap_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .num_regs = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct regmap_irq_chip axp803_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = "axp803",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .status_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .ack_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .mask_base = AXP20X_IRQ1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .irqs = axp803_regmap_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .num_irqs = ARRAY_SIZE(axp803_regmap_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .num_regs = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct regmap_irq_chip axp806_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .name = "axp806",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .status_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .ack_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .mask_base = AXP20X_IRQ1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .irqs = axp806_regmap_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const struct regmap_irq_chip axp809_regmap_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .name = "axp809",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .status_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .ack_base = AXP20X_IRQ1_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .mask_base = AXP20X_IRQ1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .mask_invert = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .init_ack_masked = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .irqs = axp809_regmap_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .num_regs = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct mfd_cell axp20x_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "axp20x-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .of_compatible = "x-powers,axp209-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .name = "axp20x-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .num_resources = ARRAY_SIZE(axp20x_pek_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .resources = axp20x_pek_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .name = "axp20x-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .name = "axp20x-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .of_compatible = "x-powers,axp209-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .of_compatible = "x-powers,axp209-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "axp20x-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .of_compatible = "x-powers,axp202-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .resources = axp20x_ac_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .name = "axp20x-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .of_compatible = "x-powers,axp202-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .resources = axp20x_usb_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const struct mfd_cell axp221_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .name = "axp221-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .num_resources = ARRAY_SIZE(axp22x_pek_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .resources = axp22x_pek_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .name = "axp20x-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .name = "axp22x-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .of_compatible = "x-powers,axp221-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = "axp20x-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .of_compatible = "x-powers,axp221-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .resources = axp20x_ac_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .of_compatible = "x-powers,axp221-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .name = "axp20x-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .of_compatible = "x-powers,axp221-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .resources = axp22x_usb_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const struct mfd_cell axp223_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = "axp221-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .num_resources = ARRAY_SIZE(axp22x_pek_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .resources = axp22x_pek_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .name = "axp22x-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .of_compatible = "x-powers,axp221-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .of_compatible = "x-powers,axp221-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .name = "axp20x-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .name = "axp20x-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .of_compatible = "x-powers,axp221-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .resources = axp20x_ac_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .name = "axp20x-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .of_compatible = "x-powers,axp223-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .resources = axp22x_usb_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const struct mfd_cell axp152_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .name = "axp20x-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .num_resources = ARRAY_SIZE(axp152_pek_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .resources = axp152_pek_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const struct resource axp288_adc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) DEFINE_RES_IRQ_NAMED(AXP288_IRQ_GPADC, "GPADC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const struct resource axp288_extcon_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) DEFINE_RES_IRQ(AXP288_IRQ_VBUS_FALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) DEFINE_RES_IRQ(AXP288_IRQ_VBUS_RISE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) DEFINE_RES_IRQ(AXP288_IRQ_MV_CHNG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) DEFINE_RES_IRQ(AXP288_IRQ_BC_USB_CHNG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct resource axp288_charger_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) DEFINE_RES_IRQ(AXP288_IRQ_OV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) DEFINE_RES_IRQ(AXP288_IRQ_DONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DEFINE_RES_IRQ(AXP288_IRQ_CHARGING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) DEFINE_RES_IRQ(AXP288_IRQ_SAFE_QUIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) DEFINE_RES_IRQ(AXP288_IRQ_SAFE_ENTER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) DEFINE_RES_IRQ(AXP288_IRQ_QCBTU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) DEFINE_RES_IRQ(AXP288_IRQ_CBTU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) DEFINE_RES_IRQ(AXP288_IRQ_QCBTO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) DEFINE_RES_IRQ(AXP288_IRQ_CBTO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const struct mfd_cell axp288_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .name = "axp288_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .num_resources = ARRAY_SIZE(axp288_adc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .resources = axp288_adc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "axp288_extcon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .num_resources = ARRAY_SIZE(axp288_extcon_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .resources = axp288_extcon_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .name = "axp288_charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .num_resources = ARRAY_SIZE(axp288_charger_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .resources = axp288_charger_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .name = "axp288_fuel_gauge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .resources = axp288_fuel_gauge_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "axp221-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .num_resources = ARRAY_SIZE(axp288_power_button_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .resources = axp288_power_button_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .name = "axp288_pmic_acpi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const struct mfd_cell axp803_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .name = "axp221-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .num_resources = ARRAY_SIZE(axp803_pek_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .resources = axp803_pek_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .name = "axp20x-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .of_compatible = "x-powers,axp813-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .name = "axp813-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .of_compatible = "x-powers,axp813-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .of_compatible = "x-powers,axp813-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .name = "axp20x-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .of_compatible = "x-powers,axp813-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .resources = axp20x_ac_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = "axp20x-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .resources = axp803_usb_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .of_compatible = "x-powers,axp813-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { .name = "axp20x-regulator" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct mfd_cell axp806_self_working_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .name = "axp221-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .num_resources = ARRAY_SIZE(axp806_pek_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .resources = axp806_pek_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { .name = "axp20x-regulator" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const struct mfd_cell axp806_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .name = "axp20x-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const struct mfd_cell axp809_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .name = "axp221-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .num_resources = ARRAY_SIZE(axp809_pek_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .resources = axp809_pek_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .name = "axp20x-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const struct mfd_cell axp813_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .name = "axp221-pek",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .num_resources = ARRAY_SIZE(axp803_pek_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .resources = axp803_pek_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .name = "axp20x-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .name = "axp20x-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .of_compatible = "x-powers,axp813-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .name = "axp813-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .of_compatible = "x-powers,axp813-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .of_compatible = "x-powers,axp813-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .name = "axp20x-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .of_compatible = "x-powers,axp813-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .resources = axp20x_ac_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .name = "axp20x-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .num_resources = ARRAY_SIZE(axp803_usb_power_supply_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .resources = axp803_usb_power_supply_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .of_compatible = "x-powers,axp813-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static struct axp20x_dev *axp20x_pm_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static void axp20x_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (axp20x_pm_power_off->variant == AXP288_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) AXP20X_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Give capacitors etc. time to drain to avoid kernel panic msg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int axp20x_match_device(struct axp20x_dev *axp20x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct device *dev = axp20x->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) const struct acpi_device_id *acpi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) of_id = of_match_device(dev->driver->of_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (!of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_err(dev, "Unable to match OF ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) axp20x->variant = (long)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!acpi_id || !acpi_id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_err(dev, "Unable to match ACPI ID and data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) axp20x->variant = (long)acpi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) switch (axp20x->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case AXP152_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) axp20x->cells = axp152_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) axp20x->regmap_cfg = &axp152_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case AXP202_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) case AXP209_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) axp20x->cells = axp20x_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) axp20x->regmap_cfg = &axp20x_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case AXP221_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) axp20x->nr_cells = ARRAY_SIZE(axp221_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) axp20x->cells = axp221_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) axp20x->regmap_cfg = &axp22x_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case AXP223_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) axp20x->nr_cells = ARRAY_SIZE(axp223_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) axp20x->cells = axp223_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) axp20x->regmap_cfg = &axp22x_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case AXP288_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) axp20x->cells = axp288_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) axp20x->regmap_cfg = &axp288_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) axp20x->irq_flags = IRQF_TRIGGER_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case AXP803_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) axp20x->nr_cells = ARRAY_SIZE(axp803_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) axp20x->cells = axp803_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) axp20x->regmap_cfg = &axp288_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case AXP806_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (of_property_read_bool(axp20x->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "x-powers,self-working-mode")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) axp20x->nr_cells = ARRAY_SIZE(axp806_self_working_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) axp20x->cells = axp806_self_working_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) axp20x->cells = axp806_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) axp20x->regmap_cfg = &axp806_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case AXP809_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) axp20x->cells = axp809_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) axp20x->regmap_cfg = &axp22x_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case AXP813_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) axp20x->nr_cells = ARRAY_SIZE(axp813_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) axp20x->cells = axp813_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) axp20x->regmap_cfg = &axp288_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * The IRQ table given in the datasheet is incorrect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * In IRQ enable/status registers 1, there are separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * IRQs for ACIN and VBUS, instead of bits [7:5] being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * the same as bits [4:2]. So it shares the same IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * as the AXP803, rather than the AXP288.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) axp20x->regmap_irq_chip = &axp803_regmap_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_info(dev, "AXP20x variant %s found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) axp20x_model_names[axp20x->variant]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) EXPORT_SYMBOL(axp20x_match_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) int axp20x_device_probe(struct axp20x_dev *axp20x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * The AXP806 supports either master/standalone or slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * Slave mode allows sharing the serial bus, even with multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * AXP806 which all have the same hardware address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * This is done with extra "serial interface address extension",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * or AXP806_BUS_ADDR_EXT, and "register address extension", or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * AXP806_REG_ADDR_EXT, registers. The former is read-only, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * 1 bit customizable at the factory, and 1 bit depending on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * state of an external pin. The latter is writable. The device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * will only respond to operations to its other registers when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * the these device addressing bits (in the upper 4 bits of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * registers) match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * By default we support an AXP806 chained to an AXP809 in slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * mode. Boards which use an AXP806 in master mode can set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * property "x-powers,master-mode" to override the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (axp20x->variant == AXP806_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (of_property_read_bool(axp20x->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "x-powers,master-mode") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) of_property_read_bool(axp20x->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) "x-powers,self-working-mode"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) regmap_write(axp20x->regmap, AXP806_REG_ADDR_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) axp20x->nr_cells, NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!pm_power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) axp20x_pm_power_off = axp20x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) pm_power_off = axp20x_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_info(axp20x->dev, "AXP20X driver loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) EXPORT_SYMBOL(axp20x_device_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int axp20x_device_remove(struct axp20x_dev *axp20x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (axp20x == axp20x_pm_power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) axp20x_pm_power_off = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) pm_power_off = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mfd_remove_devices(axp20x->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) EXPORT_SYMBOL(axp20x_device_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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