Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Atmel SMC (Static Memory Controller) helper functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2017 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mfd/syscon/atmel-smc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * atmel_smc_cs_conf_init - initialize a SMC CS conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * @conf: the SMC CS conf to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Set all fields to 0 so that one can start defining a new config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	memset(conf, 0, sizeof(*conf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *				 format expected by the SMC engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * @ncycles: number of MCK clk cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @msbpos: position of the MSB part of the timing field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * @msbwidth: width of the MSB part of the timing field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * @msbfactor: factor applied to the MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @encodedval: param used to store the encoding result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * This function encodes the @ncycles value as described in the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * helper which called with different parameter depending on the encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * If the @ncycles value is too big to be encoded, -ERANGE is returned and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * the encodedval is contains the maximum val. Otherwise, 0 is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int atmel_smc_cs_encode_ncycles(unsigned int ncycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				       unsigned int msbpos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				       unsigned int msbwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 				       unsigned int msbfactor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 				       unsigned int *encodedval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned int lsbmask = GENMASK(msbpos - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned int msbmask = GENMASK(msbwidth - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned int msb, lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	msb = ncycles / msbfactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	lsb = ncycles % msbfactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (lsb > lsbmask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		lsb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		msb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * Let's just put the maximum we can if the requested setting does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * not fit in the register field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * We still return -ERANGE in case the caller cares.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (msb > msbmask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		msb = msbmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		lsb = lsbmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		ret = -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	*encodedval = (msb << msbpos) | lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  *				  specific value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * @conf: SMC CS conf descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @shift: the position of the Txx field in the TIMINGS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * @ncycles: value (expressed in MCK clk cycles) to assign to this Txx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  *	     parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * This function encodes the @ncycles value as described in the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * (section "SMC Timings Register"), and then stores the result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * @conf->timings field at @shift position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * the field, and 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				 unsigned int shift, unsigned int ncycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	    shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	    shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	    shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	    shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * The formula described in atmel datasheets (section "HSMC Timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * Register"):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 * ncycles = (Txx[3] * 64) + Txx[2:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	conf->timings &= ~GENMASK(shift + 3, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	conf->timings |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *				 specific value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * @conf: SMC CS conf descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * @shift: the position of the xx_SETUP field in the SETUP register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *	     parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * This function encodes the @ncycles value as described in the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * (section "SMC Setup Register"), and then stores the result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * @conf->setup field at @shift position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * the field, and 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				unsigned int shift, unsigned int ncycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	    shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * The formula described in atmel datasheets (section "SMC Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * Register"):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 * ncycles = (128 * xx_SETUP[5]) + xx_SETUP[4:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	conf->setup &= ~GENMASK(shift + 7, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	conf->setup |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *				 specific value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * @conf: SMC CS conf descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * @shift: the position of the xx_PULSE field in the PULSE register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_PULSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *	     parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * This function encodes the @ncycles value as described in the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * (section "SMC Pulse Register"), and then stores the result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * @conf->setup field at @shift position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * the field, and 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				unsigned int shift, unsigned int ncycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	    shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * The formula described in atmel datasheets (section "SMC Pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * Register"):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 * ncycles = (256 * xx_PULSE[6]) + xx_PULSE[5:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	conf->pulse &= ~GENMASK(shift + 7, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	conf->pulse |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  *				 specific value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * @conf: SMC CS conf descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * @shift: the position of the xx_CYCLE field in the CYCLE register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_CYCLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  *	     parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * This function encodes the @ncycles value as described in the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * (section "SMC Cycle Register"), and then stores the result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * @conf->setup field at @shift position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * the field, and 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				unsigned int shift, unsigned int ncycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 * The formula described in atmel datasheets (section "SMC Cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 * Register"):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * ncycles = (xx_CYCLE[8:7] * 256) + xx_CYCLE[6:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	conf->cycle &= ~GENMASK(shift + 15, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	conf->cycle |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * atmel_smc_cs_conf_apply - apply an SMC CS conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * @regmap: the SMC regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * @cs: the CS id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * @conf: the SMC CS conf to apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * Applies an SMC CS configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * Only valid on at91sam9/avr32 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			     const struct atmel_smc_cs_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  * atmel_hsmc_cs_conf_apply - apply an SMC CS conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * @regmap: the HSMC regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * @cs: the CS id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * @layout: the layout of registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * @conf: the SMC CS conf to apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * Applies an SMC CS configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * Only valid on post-sama5 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			      const struct atmel_hsmc_reg_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			      int cs, const struct atmel_smc_cs_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * atmel_smc_cs_conf_get - retrieve the current SMC CS conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  * @regmap: the SMC regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * @cs: the CS id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * @conf: the SMC CS conf object to store the current conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * Retrieve the SMC CS configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * Only valid on at91sam9/avr32 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			   struct atmel_smc_cs_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  * atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  * @regmap: the HSMC regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  * @cs: the CS id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  * @layout: the layout of registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  * @conf: the SMC CS conf object to store the current conf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  * Retrieve the SMC CS configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * Only valid on post-sama5 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void atmel_hsmc_cs_conf_get(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			    const struct atmel_hsmc_reg_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			    int cs, struct atmel_smc_cs_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.timing_regs_offset = 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.timing_regs_offset = 0x700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct of_device_id atmel_smc_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	{ .compatible = "atmel,at91sam9260-smc", .data = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{ .compatible = "atmel,sama5d3-smc", .data = &sama5d3_reg_layout },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	{ .compatible = "atmel,sama5d2-smc", .data = &sama5d2_reg_layout },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  * atmel_hsmc_get_reg_layout - retrieve the layout of HSMC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  * @np: the HSMC regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  * Retrieve the layout of HSMC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  * Returns NULL in case of SMC, a struct atmel_hsmc_reg_layout pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  * in HSMC case, otherwise ERR_PTR(-EINVAL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) const struct atmel_hsmc_reg_layout *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) atmel_hsmc_get_reg_layout(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	match = of_match_node(atmel_smc_ids, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return match ? match->data : ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) EXPORT_SYMBOL_GPL(atmel_hsmc_get_reg_layout);