^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/atmel-hlcdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ATMEL_HLCDC_REG_MAX (0x4000 - 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct atmel_hlcdc_regmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct mfd_cell atmel_hlcdc_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .name = "atmel-hlcdc-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .of_compatible = "atmel,hlcdc-pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .name = "atmel-hlcdc-dc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .of_compatible = "atmel,hlcdc-display-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int regmap_atmel_hlcdc_reg_write(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct atmel_hlcdc_regmap *hregmap = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (reg <= ATMEL_HLCDC_DIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = readl_poll_timeout_atomic(hregmap->regs + ATMEL_HLCDC_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) !(status & ATMEL_HLCDC_SIP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dev_err(hregmap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "Timeout! Clock domain synchronization is in progress!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writel(val, hregmap->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int regmap_atmel_hlcdc_reg_read(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct atmel_hlcdc_regmap *hregmap = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *val = readl(hregmap->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct regmap_config atmel_hlcdc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .max_register = ATMEL_HLCDC_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .reg_write = regmap_atmel_hlcdc_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .reg_read = regmap_atmel_hlcdc_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int atmel_hlcdc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct atmel_hlcdc_regmap *hregmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct atmel_hlcdc *hlcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) hregmap = devm_kzalloc(dev, sizeof(*hregmap), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!hregmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hlcdc = devm_kzalloc(dev, sizeof(*hlcdc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!hlcdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) hregmap->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (IS_ERR(hregmap->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return PTR_ERR(hregmap->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) hregmap->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) hlcdc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (hlcdc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return hlcdc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) hlcdc->periph_clk = devm_clk_get(dev, "periph_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (IS_ERR(hlcdc->periph_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(dev, "failed to get peripheral clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return PTR_ERR(hlcdc->periph_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) hlcdc->sys_clk = devm_clk_get(dev, "sys_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (IS_ERR(hlcdc->sys_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_err(dev, "failed to get system clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return PTR_ERR(hlcdc->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) hlcdc->slow_clk = devm_clk_get(dev, "slow_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (IS_ERR(hlcdc->slow_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(dev, "failed to get slow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return PTR_ERR(hlcdc->slow_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) hlcdc->regmap = devm_regmap_init(dev, NULL, hregmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &atmel_hlcdc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (IS_ERR(hlcdc->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return PTR_ERR(hlcdc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_set_drvdata(dev, hlcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return devm_mfd_add_devices(dev, -1, atmel_hlcdc_cells,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ARRAY_SIZE(atmel_hlcdc_cells),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct of_device_id atmel_hlcdc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .compatible = "atmel,at91sam9n12-hlcdc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .compatible = "atmel,at91sam9x5-hlcdc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .compatible = "atmel,sama5d2-hlcdc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .compatible = "atmel,sama5d3-hlcdc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .compatible = "atmel,sama5d4-hlcdc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .compatible = "microchip,sam9x60-hlcdc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MODULE_DEVICE_TABLE(of, atmel_hlcdc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct platform_driver atmel_hlcdc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .probe = atmel_hlcdc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "atmel-hlcdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .of_match_table = atmel_hlcdc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) module_platform_driver(atmel_hlcdc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MODULE_ALIAS("platform:atmel-hlcdc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MODULE_DESCRIPTION("Atmel HLCDC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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