Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Core driver for ams AS3722 PMICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 AMS AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Florian Lobmaier <florian.lobmaier@ams.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mfd/as3722.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AS3722_DEVICE_ID	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const struct resource as3722_rtc_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.name = "as3722-rtc-alarm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.start = AS3722_IRQ_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.end = AS3722_IRQ_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static const struct resource as3722_adc_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.name = "as3722-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.start = AS3722_IRQ_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.end = AS3722_IRQ_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static const struct mfd_cell as3722_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.name = "as3722-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.name = "as3722-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.name = "as3722-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.num_resources = ARRAY_SIZE(as3722_rtc_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.resources = as3722_rtc_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.name = "as3722-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.num_resources = ARRAY_SIZE(as3722_adc_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.resources = as3722_adc_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.name = "as3722-power-off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.name = "as3722-wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static const struct regmap_irq as3722_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* INT1 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	[AS3722_IRQ_LID] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.mask = AS3722_INTERRUPT_MASK1_LID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	[AS3722_IRQ_ACOK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.mask = AS3722_INTERRUPT_MASK1_ACOK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[AS3722_IRQ_ENABLE1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.mask = AS3722_INTERRUPT_MASK1_ENABLE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	[AS3722_IRQ_OCCUR_ALARM_SD0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.mask = AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	[AS3722_IRQ_ONKEY_LONG_PRESS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.mask = AS3722_INTERRUPT_MASK1_ONKEY_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	[AS3722_IRQ_ONKEY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.mask = AS3722_INTERRUPT_MASK1_ONKEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	[AS3722_IRQ_OVTMP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.mask = AS3722_INTERRUPT_MASK1_OVTMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	[AS3722_IRQ_LOWBAT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.mask = AS3722_INTERRUPT_MASK1_LOWBAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/* INT2 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[AS3722_IRQ_SD0_LV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.mask = AS3722_INTERRUPT_MASK2_SD0_LV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	[AS3722_IRQ_SD1_LV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.mask = AS3722_INTERRUPT_MASK2_SD1_LV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	[AS3722_IRQ_SD2_LV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.mask = AS3722_INTERRUPT_MASK2_SD2345_LV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	[AS3722_IRQ_PWM1_OV_PROT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.mask = AS3722_INTERRUPT_MASK2_PWM1_OV_PROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	[AS3722_IRQ_PWM2_OV_PROT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.mask = AS3722_INTERRUPT_MASK2_PWM2_OV_PROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	[AS3722_IRQ_ENABLE2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.mask = AS3722_INTERRUPT_MASK2_ENABLE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	[AS3722_IRQ_SD6_LV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.mask = AS3722_INTERRUPT_MASK2_SD6_LV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	[AS3722_IRQ_RTC_REP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.mask = AS3722_INTERRUPT_MASK2_RTC_REP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* INT3 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	[AS3722_IRQ_RTC_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.mask = AS3722_INTERRUPT_MASK3_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	[AS3722_IRQ_GPIO1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.mask = AS3722_INTERRUPT_MASK3_GPIO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	[AS3722_IRQ_GPIO2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.mask = AS3722_INTERRUPT_MASK3_GPIO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	[AS3722_IRQ_GPIO3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.mask = AS3722_INTERRUPT_MASK3_GPIO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	[AS3722_IRQ_GPIO4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.mask = AS3722_INTERRUPT_MASK3_GPIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	[AS3722_IRQ_GPIO5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.mask = AS3722_INTERRUPT_MASK3_GPIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	[AS3722_IRQ_WATCHDOG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.mask = AS3722_INTERRUPT_MASK3_WATCHDOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	[AS3722_IRQ_ENABLE3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.mask = AS3722_INTERRUPT_MASK3_ENABLE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* INT4 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	[AS3722_IRQ_TEMP_SD0_SHUTDOWN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	[AS3722_IRQ_TEMP_SD1_SHUTDOWN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	[AS3722_IRQ_TEMP_SD2_SHUTDOWN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	[AS3722_IRQ_TEMP_SD0_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	[AS3722_IRQ_TEMP_SD1_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	[AS3722_IRQ_TEMP_SD6_ALARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	[AS3722_IRQ_OCCUR_ALARM_SD6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.mask = AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	[AS3722_IRQ_ADC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.mask = AS3722_INTERRUPT_MASK4_ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct regmap_irq_chip as3722_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.name = "as3722",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.irqs = as3722_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.num_irqs = ARRAY_SIZE(as3722_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.num_regs = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.status_base = AS3722_INTERRUPT_STATUS1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.mask_base = AS3722_INTERRUPT_MASK1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int as3722_check_device_id(struct as3722 *as3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* Check that this is actually a AS3722 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ret = as3722_read(as3722, AS3722_ASIC_ID1_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_err(as3722->dev, "ASIC_ID1 read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (val != AS3722_DEVICE_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		dev_err(as3722->dev, "Device is not AS3722, ID is 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ret = as3722_read(as3722, AS3722_ASIC_ID2_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		dev_err(as3722->dev, "ASIC_ID2 read failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	dev_info(as3722->dev, "AS3722 with revision 0x%x found\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int as3722_configure_pullups(struct as3722 *as3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (as3722->en_intern_int_pullup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		val |= AS3722_INT_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (as3722->en_intern_i2c_pullup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		val |= AS3722_I2C_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ret = as3722_update_bits(as3722, AS3722_IOVOLTAGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			AS3722_INT_PULL_UP | AS3722_I2C_PULL_UP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		dev_err(as3722->dev, "IOVOLTAGE_REG update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct regmap_range as3722_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_SD6_VOLTAGE_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	regmap_reg_range(AS3722_GPIO0_CONTROL_REG, AS3722_LDO7_VOLTAGE_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	regmap_reg_range(AS3722_LDO9_VOLTAGE_REG, AS3722_REG_SEQU_MOD3_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	regmap_reg_range(AS3722_SD_PHSW_CTRL_REG, AS3722_PWM_CONTROL_H_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	regmap_reg_range(AS3722_WATCHDOG_TIMER_REG, AS3722_WATCHDOG_TIMER_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	regmap_reg_range(AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 					AS3722_BATTERY_VOLTAGE_MONITOR2_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_PWM_VCONTROL4_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	regmap_reg_range(AS3722_BB_CHARGER_REG, AS3722_SRAM_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	regmap_reg_range(AS3722_RTC_ACCESS_REG, AS3722_RTC_ACCESS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	regmap_reg_range(AS3722_RTC_STATUS_REG, AS3722_TEMP_STATUS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	regmap_reg_range(AS3722_ADC0_CONTROL_REG, AS3722_ADC_CONFIGURATION_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	regmap_reg_range(AS3722_ASIC_ID1_REG, AS3722_ASIC_ID2_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	regmap_reg_range(AS3722_LOCK_REG, AS3722_LOCK_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	regmap_reg_range(AS3722_FUSE7_REG, AS3722_FUSE7_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct regmap_access_table as3722_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.yes_ranges = as3722_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.n_yes_ranges = ARRAY_SIZE(as3722_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct regmap_range as3722_writable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_SD6_VOLTAGE_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	regmap_reg_range(AS3722_GPIO0_CONTROL_REG, AS3722_LDO7_VOLTAGE_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	regmap_reg_range(AS3722_LDO9_VOLTAGE_REG, AS3722_GPIO_SIGNAL_OUT_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	regmap_reg_range(AS3722_REG_SEQU_MOD1_REG, AS3722_REG_SEQU_MOD3_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	regmap_reg_range(AS3722_SD_PHSW_CTRL_REG, AS3722_PWM_CONTROL_H_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	regmap_reg_range(AS3722_WATCHDOG_TIMER_REG, AS3722_WATCHDOG_TIMER_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	regmap_reg_range(AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 					AS3722_BATTERY_VOLTAGE_MONITOR2_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_PWM_VCONTROL4_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	regmap_reg_range(AS3722_BB_CHARGER_REG, AS3722_SRAM_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	regmap_reg_range(AS3722_INTERRUPT_MASK1_REG, AS3722_TEMP_STATUS_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	regmap_reg_range(AS3722_ADC0_CONTROL_REG, AS3722_ADC1_CONTROL_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	regmap_reg_range(AS3722_ADC1_THRESHOLD_HI_MSB_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 					AS3722_ADC_CONFIGURATION_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	regmap_reg_range(AS3722_LOCK_REG, AS3722_LOCK_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct regmap_access_table as3722_writable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.yes_ranges = as3722_writable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.n_yes_ranges = ARRAY_SIZE(as3722_writable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct regmap_range as3722_cacheable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	regmap_reg_range(AS3722_SD0_VOLTAGE_REG, AS3722_LDO11_VOLTAGE_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	regmap_reg_range(AS3722_SD_CONTROL_REG, AS3722_LDOCONTROL1_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct regmap_access_table as3722_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.no_ranges = as3722_cacheable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.n_no_ranges = ARRAY_SIZE(as3722_cacheable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct regmap_config as3722_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.max_register = AS3722_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.rd_table = &as3722_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.wr_table = &as3722_writable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.volatile_table = &as3722_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int as3722_i2c_of_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			struct as3722 *as3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct device_node *np = i2c->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct irq_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		dev_err(&i2c->dev, "Device Tree not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	irq_data = irq_get_irq_data(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (!irq_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	as3722->en_intern_int_pullup = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 					"ams,enable-internal-int-pullup");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	as3722->en_intern_i2c_pullup = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					"ams,enable-internal-i2c-pullup");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	as3722->en_ac_ok_pwr_on = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 					"ams,enable-ac-ok-power-on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	as3722->irq_flags = irqd_get_trigger_type(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	dev_dbg(&i2c->dev, "IRQ flags are 0x%08lx\n", as3722->irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int as3722_i2c_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct as3722 *as3722;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	as3722 = devm_kzalloc(&i2c->dev, sizeof(struct as3722), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (!as3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	as3722->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	as3722->chip_irq = i2c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	i2c_set_clientdata(i2c, as3722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	ret = as3722_i2c_of_probe(i2c, as3722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	as3722->regmap = devm_regmap_init_i2c(i2c, &as3722_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (IS_ERR(as3722->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ret = PTR_ERR(as3722->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		dev_err(&i2c->dev, "regmap init failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	ret = as3722_check_device_id(as3722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	irq_flags = as3722->irq_flags | IRQF_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	ret = devm_regmap_add_irq_chip(as3722->dev, as3722->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 				       as3722->chip_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 				       irq_flags, -1, &as3722_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 				       &as3722->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		dev_err(as3722->dev, "Failed to add regmap irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	ret = as3722_configure_pullups(as3722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (as3722->en_ac_ok_pwr_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		val = AS3722_CTRL_SEQU1_AC_OK_PWR_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	ret = as3722_update_bits(as3722, AS3722_CTRL_SEQU1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			AS3722_CTRL_SEQU1_AC_OK_PWR_ON, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		dev_err(as3722->dev, "CTRLsequ1 update failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	ret = devm_mfd_add_devices(&i2c->dev, -1, as3722_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 				   ARRAY_SIZE(as3722_devs), NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 				   regmap_irq_get_domain(as3722->irq_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		dev_err(as3722->dev, "Failed to add MFD devices: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	device_init_wakeup(as3722->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	dev_dbg(as3722->dev, "AS3722 core driver initialized successfully\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int __maybe_unused as3722_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	struct as3722 *as3722 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		enable_irq_wake(as3722->chip_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	disable_irq(as3722->chip_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int __maybe_unused as3722_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	struct as3722 *as3722 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	enable_irq(as3722->chip_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		disable_irq_wake(as3722->chip_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct of_device_id as3722_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	{ .compatible = "ams,as3722", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_DEVICE_TABLE(of, as3722_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct i2c_device_id as3722_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{ "as3722", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_DEVICE_TABLE(i2c, as3722_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct dev_pm_ops as3722_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	SET_SYSTEM_SLEEP_PM_OPS(as3722_i2c_suspend, as3722_i2c_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct i2c_driver as3722_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		.name = "as3722",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		.of_match_table = as3722_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		.pm = &as3722_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	.probe = as3722_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	.id_table = as3722_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) module_i2c_driver(as3722_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_DESCRIPTION("I2C support for AS3722 PMICs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_AUTHOR("Florian Lobmaier <florian.lobmaier@ams.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MODULE_LICENSE("GPL");