^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Altera Arria10 DevKit System Resource MFD Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Thor Thayer <tthayer@opensource.altera.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * SPI access for Altera Arria10 MAX5 System Resource Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Adapted from DA9052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/altera-a10sr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mfd_cell altr_a10sr_subdev_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .name = "altr_a10sr_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .of_compatible = "altr,a10sr-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .name = "altr_a10sr_reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .of_compatible = "altr,a10sr-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) case ALTR_A10SR_VERSION_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) case ALTR_A10SR_LED_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) case ALTR_A10SR_PBDSW_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) case ALTR_A10SR_PBDSW_IRQ_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) case ALTR_A10SR_PWR_GOOD1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) case ALTR_A10SR_PWR_GOOD2_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) case ALTR_A10SR_PWR_GOOD3_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case ALTR_A10SR_FMCAB_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) case ALTR_A10SR_HPS_RST_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case ALTR_A10SR_USB_QSPI_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case ALTR_A10SR_SFPA_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case ALTR_A10SR_SFPB_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case ALTR_A10SR_I2C_M_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case ALTR_A10SR_WARM_RST_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case ALTR_A10SR_WR_KEY_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case ALTR_A10SR_PMBUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case ALTR_A10SR_LED_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case ALTR_A10SR_PBDSW_IRQ_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) case ALTR_A10SR_FMCAB_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case ALTR_A10SR_HPS_RST_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case ALTR_A10SR_USB_QSPI_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case ALTR_A10SR_SFPA_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case ALTR_A10SR_SFPB_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case ALTR_A10SR_WARM_RST_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case ALTR_A10SR_WR_KEY_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case ALTR_A10SR_PMBUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case ALTR_A10SR_PBDSW_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case ALTR_A10SR_PBDSW_IRQ_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case ALTR_A10SR_PWR_GOOD1_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case ALTR_A10SR_PWR_GOOD2_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case ALTR_A10SR_PWR_GOOD3_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case ALTR_A10SR_HPS_RST_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case ALTR_A10SR_I2C_M_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case ALTR_A10SR_WARM_RST_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case ALTR_A10SR_WR_KEY_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case ALTR_A10SR_PMBUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct regmap_config altr_a10sr_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .use_single_read = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .read_flag_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .write_flag_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .max_register = ALTR_A10SR_WR_KEY_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .readable_reg = altr_a10sr_reg_readable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .writeable_reg = altr_a10sr_reg_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .volatile_reg = altr_a10sr_reg_volatile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int altr_a10sr_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct altr_a10sr *a10sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!a10sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spi->mode = SPI_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) a10sr->dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spi_set_drvdata(spi, a10sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (IS_ERR(a10sr->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = PTR_ERR(a10sr->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(&spi->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = devm_mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) altr_a10sr_subdev_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ARRAY_SIZE(altr_a10sr_subdev_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_err(a10sr->dev, "Failed to register sub-devices: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct of_device_id altr_a10sr_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { .compatible = "altr,a10sr" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct spi_driver altr_a10sr_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .probe = altr_a10sr_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "altr_a10sr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .of_match_table = of_match_ptr(altr_a10sr_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) builtin_driver(altr_a10sr_spi_driver, spi_register_driver)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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