Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Base driver for Marvell 88PM805
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Haojian Zhuang <haojian.zhuang@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Joseph(Yossi) Hanin <yhanin@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Qiao Zhou <zhouqiao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Public License. See the file "COPYING" in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/mfd/88pm80x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static const struct i2c_device_id pm80x_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{"88PM805", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	{} /* NULL terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* Interrupt Number in 88PM805 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	PM805_IRQ_LDO_OFF,	/*0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	PM805_IRQ_SRC_DPLL_LOCK,	/*1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	PM805_IRQ_CLIP_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	PM805_IRQ_MIC_CONFLICT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	PM805_IRQ_HP2_SHRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	PM805_IRQ_HP1_SHRT,	/*5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	PM805_IRQ_FINE_PLL_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	PM805_IRQ_RAW_PLL_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	PM805_IRQ_VOLP_BTN_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	PM805_IRQ_VOLM_BTN_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	PM805_IRQ_SHRT_BTN_DET,	/*10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	PM805_IRQ_MIC_DET,	/*11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	PM805_MAX_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static struct resource codec_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 /* Headset microphone insertion or removal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 .name = "micin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 .start = PM805_IRQ_MIC_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 .end = PM805_IRQ_MIC_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 /* Audio short HP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 .name = "audio-short1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 .start = PM805_IRQ_HP1_SHRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 .end = PM805_IRQ_HP1_SHRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 /* Audio short HP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 .name = "audio-short2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 .start = PM805_IRQ_HP2_SHRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 .end = PM805_IRQ_HP2_SHRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const struct mfd_cell codec_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 .name = "88pm80x-codec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 .num_resources = ARRAY_SIZE(codec_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 .resources = &codec_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static struct regmap_irq pm805_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	[PM805_IRQ_LDO_OFF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.mask = PM805_INT1_HP1_SHRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[PM805_IRQ_SRC_DPLL_LOCK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.mask = PM805_INT1_HP2_SHRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	[PM805_IRQ_CLIP_FAULT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.mask = PM805_INT1_MIC_CONFLICT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	[PM805_IRQ_MIC_CONFLICT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.mask = PM805_INT1_CLIP_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	[PM805_IRQ_HP2_SHRT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.mask = PM805_INT1_LDO_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[PM805_IRQ_HP1_SHRT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.mask = PM805_INT1_SRC_DPLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	[PM805_IRQ_FINE_PLL_FAULT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.mask = PM805_INT2_MIC_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	[PM805_IRQ_RAW_PLL_FAULT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.mask = PM805_INT2_SHRT_BTN_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	[PM805_IRQ_VOLP_BTN_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.mask = PM805_INT2_VOLM_BTN_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	[PM805_IRQ_VOLM_BTN_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.mask = PM805_INT2_VOLP_BTN_DET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	[PM805_IRQ_SHRT_BTN_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.mask = PM805_INT2_RAW_PLL_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	[PM805_IRQ_MIC_DET] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.mask = PM805_INT2_FINE_PLL_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int device_irq_init_805(struct pm80x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct regmap *map = chip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned long flags = IRQF_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	int data, mask, ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (!map || !chip->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		dev_err(chip->dev, "incorrect parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * irq_mode defines the way of clearing interrupt. it's read-clear by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 * default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	    PM805_STATUS0_INT_CLEAR | PM805_STATUS0_INV_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	    PM800_STATUS0_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	data = PM805_STATUS0_INT_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ret = regmap_update_bits(map, PM805_INT_STATUS0, mask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * PM805_INT_STATUS is under 32K clock domain, so need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * add proper delay before the next I2C register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	usleep_range(1000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	    regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				chip->regmap_irq_chip, &chip->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void device_irq_exit_805(struct pm80x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	regmap_del_irq_chip(chip->irq, chip->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct regmap_irq_chip pm805_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.name = "88pm805",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.irqs = pm805_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.num_irqs = ARRAY_SIZE(pm805_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.num_regs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.status_base = PM805_INT_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.mask_base = PM805_INT_MASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.ack_base = PM805_INT_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int device_805_init(struct pm80x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct regmap *map = chip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_err(chip->dev, "regmap is invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	chip->regmap_irq_chip = &pm805_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ret = device_irq_init_805(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		dev_err(chip->dev, "Failed to init pm805 irq!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		goto out_irq_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ret = mfd_add_devices(chip->dev, 0, &codec_devs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			      ARRAY_SIZE(codec_devs), &codec_resources[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			      NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		dev_err(chip->dev, "Failed to add codec subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		goto out_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		dev_info(chip->dev, "[%s]:Added mfd codec_devs\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) out_codec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	device_irq_exit_805(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) out_irq_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int pm805_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct pm80x_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct pm80x_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ret = pm80x_init(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		dev_err(&client->dev, "pm805_init fail!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		goto out_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	chip = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ret = device_805_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		dev_err(chip->dev, "Failed to initialize 88pm805 devices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		goto err_805_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (pdata && pdata->plat_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		pdata->plat_config(chip, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) err_805_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	pm80x_deinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) out_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int pm805_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct pm80x_chip *chip = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mfd_remove_devices(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	device_irq_exit_805(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	pm80x_deinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct i2c_driver pm805_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.name = "88PM805",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.pm = &pm80x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.probe = pm805_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.remove = pm805_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.id_table = pm80x_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int __init pm805_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return i2c_add_driver(&pm805_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) subsys_initcall(pm805_i2c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void __exit pm805_i2c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	i2c_del_driver(&pm805_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) module_exit(pm805_i2c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM805");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_LICENSE("GPL");