Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Base driver for Marvell 88PM800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Haojian Zhuang <haojian.zhuang@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Joseph(Yossi) Hanin <yhanin@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Qiao Zhou <zhouqiao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Public License. See the file "COPYING" in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/mfd/88pm80x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Interrupt Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PM800_INT_STATUS1		(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PM800_ONKEY_INT_STS1		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PM800_EXTON_INT_STS1		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PM800_CHG_INT_STS1			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PM800_BAT_INT_STS1			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PM800_RTC_INT_STS1			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PM800_CLASSD_OC_INT_STS1	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PM800_INT_STATUS2		(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PM800_VBAT_INT_STS2		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PM800_VSYS_INT_STS2		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PM800_VCHG_INT_STS2		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PM800_TINT_INT_STS2		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PM800_GPADC0_INT_STS2	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PM800_TBAT_INT_STS2		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PM800_GPADC2_INT_STS2	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PM800_GPADC3_INT_STS2	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PM800_INT_STATUS3		(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PM800_INT_STATUS4		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PM800_GPIO0_INT_STS4		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PM800_GPIO1_INT_STS4		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PM800_GPIO2_INT_STS4		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PM800_GPIO3_INT_STS4		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PM800_GPIO4_INT_STS4		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PM800_INT_ENA_1		(0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PM800_ONKEY_INT_ENA1		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PM800_EXTON_INT_ENA1		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PM800_CHG_INT_ENA1			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PM800_BAT_INT_ENA1			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PM800_RTC_INT_ENA1			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PM800_CLASSD_OC_INT_ENA1	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PM800_INT_ENA_2		(0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PM800_VBAT_INT_ENA2		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PM800_VSYS_INT_ENA2		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PM800_VCHG_INT_ENA2		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PM800_TINT_INT_ENA2		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PM800_INT_ENA_3		(0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PM800_GPADC0_INT_ENA3		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PM800_GPADC1_INT_ENA3		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PM800_GPADC2_INT_ENA3		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PM800_GPADC3_INT_ENA3		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PM800_GPADC4_INT_ENA3		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PM800_INT_ENA_4		(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PM800_GPIO0_INT_ENA4		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PM800_GPIO1_INT_ENA4		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PM800_GPIO2_INT_ENA4		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PM800_GPIO3_INT_ENA4		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define PM800_GPIO4_INT_ENA4		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* number of INT_ENA & INT_STATUS regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PM800_INT_REG_NUM			(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* Interrupt Number in 88PM800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	PM800_IRQ_ONKEY,	/*EN1b0 *//*0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	PM800_IRQ_EXTON,	/*EN1b1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	PM800_IRQ_CHG,		/*EN1b2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	PM800_IRQ_BAT,		/*EN1b3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	PM800_IRQ_RTC,		/*EN1b4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	PM800_IRQ_CLASSD,	/*EN1b5 *//*5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	PM800_IRQ_VBAT,		/*EN2b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	PM800_IRQ_VSYS,		/*EN2b1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	PM800_IRQ_VCHG,		/*EN2b2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	PM800_IRQ_TINT,		/*EN2b3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	PM800_IRQ_GPADC0,	/*EN3b0 *//*10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	PM800_IRQ_GPADC1,	/*EN3b1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	PM800_IRQ_GPADC2,	/*EN3b2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	PM800_IRQ_GPADC3,	/*EN3b3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	PM800_IRQ_GPADC4,	/*EN3b4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	PM800_IRQ_GPIO0,	/*EN4b0 *//*15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	PM800_IRQ_GPIO1,	/*EN4b1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	PM800_IRQ_GPIO2,	/*EN4b2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	PM800_IRQ_GPIO3,	/*EN4b3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	PM800_IRQ_GPIO4,	/*EN4b4 *//*19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	PM800_MAX_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* PM800: generation identification number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PM800_CHIP_GEN_ID_NUM	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct i2c_device_id pm80x_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{"88PM800", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{} /* NULL terminated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct resource rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 .name = "88pm80x-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 .start = PM800_IRQ_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 .end = PM800_IRQ_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct mfd_cell rtc_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 .name = "88pm80x-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 .resources = &rtc_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct resource onkey_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 .name = "88pm80x-onkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 .start = PM800_IRQ_ONKEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 .end = PM800_IRQ_ONKEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct mfd_cell onkey_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 .name = "88pm80x-onkey",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 .resources = &onkey_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct mfd_cell regulator_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 .name = "88pm80x-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct regmap_irq pm800_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* INT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	[PM800_IRQ_ONKEY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.mask = PM800_ONKEY_INT_ENA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	[PM800_IRQ_EXTON] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.mask = PM800_EXTON_INT_ENA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	[PM800_IRQ_CHG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.mask = PM800_CHG_INT_ENA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	[PM800_IRQ_BAT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.mask = PM800_BAT_INT_ENA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	[PM800_IRQ_RTC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.mask = PM800_RTC_INT_ENA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	[PM800_IRQ_CLASSD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.mask = PM800_CLASSD_OC_INT_ENA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/* INT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	[PM800_IRQ_VBAT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.mask = PM800_VBAT_INT_ENA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	[PM800_IRQ_VSYS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.mask = PM800_VSYS_INT_ENA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	[PM800_IRQ_VCHG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.mask = PM800_VCHG_INT_ENA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	[PM800_IRQ_TINT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.reg_offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.mask = PM800_TINT_INT_ENA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* INT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	[PM800_IRQ_GPADC0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.mask = PM800_GPADC0_INT_ENA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	[PM800_IRQ_GPADC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.mask = PM800_GPADC1_INT_ENA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	[PM800_IRQ_GPADC2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.mask = PM800_GPADC2_INT_ENA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	[PM800_IRQ_GPADC3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.mask = PM800_GPADC3_INT_ENA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	[PM800_IRQ_GPADC4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.reg_offset = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.mask = PM800_GPADC4_INT_ENA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* INT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	[PM800_IRQ_GPIO0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.mask = PM800_GPIO0_INT_ENA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	[PM800_IRQ_GPIO1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.mask = PM800_GPIO1_INT_ENA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	[PM800_IRQ_GPIO2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.mask = PM800_GPIO2_INT_ENA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	[PM800_IRQ_GPIO3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.mask = PM800_GPIO3_INT_ENA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	[PM800_IRQ_GPIO4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.reg_offset = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.mask = PM800_GPIO4_INT_ENA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int device_gpadc_init(struct pm80x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				       struct pm80x_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct pm80x_subchip *subchip = chip->subchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct regmap *map = subchip->regmap_gpadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	int data = 0, mask = 0, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		dev_warn(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			 "Warning: gpadc regmap is not available!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 * initialize GPADC without activating it turn on GPADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * measurments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = regmap_update_bits(map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				 PM800_GPADC_MISC_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				 PM800_GPADC_MISC_GPFSM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				 PM800_GPADC_MISC_GPFSM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 * This function configures the ADC as requires for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 * CP implementation.CP does not "own" the ADC configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 * registers and relies on AP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 * Reason: enable automatic ADC measurements needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	 * for CP to get VBAT and RF temperature readings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				 PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				 (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				 (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * the defult of PM800 is GPADC operates at 100Ks/s rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 * and Number of GPADC slots with active current bias prior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 * to GPADC sampling = 1 slot for all GPADCs set for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 * Temprature mesurmants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (pdata && (pdata->batt_det == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			PM800_GPADC_GP_BIAS_EN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int device_onkey_init(struct pm80x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				struct pm80x_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			      ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			      NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		dev_err(chip->dev, "Failed to add onkey subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int device_rtc_init(struct pm80x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 				struct pm80x_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		rtc_devs[0].platform_data = pdata->rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		rtc_devs[0].pdata_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				pdata->rtc ? sizeof(struct pm80x_rtc_pdata) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			      ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		dev_err(chip->dev, "Failed to add rtc subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int device_regulator_init(struct pm80x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 					   struct pm80x_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	ret = mfd_add_devices(chip->dev, 0, &regulator_devs[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			      ARRAY_SIZE(regulator_devs), NULL, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		dev_err(chip->dev, "Failed to add regulator subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int device_irq_init_800(struct pm80x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	struct regmap *map = chip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	unsigned long flags = IRQF_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	int data, mask, ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (!map || !chip->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		dev_err(chip->dev, "incorrect parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	 * irq_mode defines the way of clearing interrupt. it's read-clear by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 * default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	    PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	    PM800_WAKEUP2_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	data = PM800_WAKEUP2_INT_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	    regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 				chip->regmap_irq_chip, &chip->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void device_irq_exit_800(struct pm80x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	regmap_del_irq_chip(chip->irq, chip->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static struct regmap_irq_chip pm800_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.name = "88pm800",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.irqs = pm800_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.num_irqs = ARRAY_SIZE(pm800_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.num_regs = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.status_base = PM800_INT_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.mask_base = PM800_INT_ENA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.ack_base = PM800_INT_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.mask_invert = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int pm800_pages_init(struct pm80x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	struct pm80x_subchip *subchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	struct i2c_client *client = chip->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	subchip = chip->subchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	if (!subchip || !subchip->power_page_addr || !subchip->gpadc_page_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	/* PM800 block power page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	subchip->power_page = i2c_new_dummy_device(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 					    subchip->power_page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (IS_ERR(subchip->power_page)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		ret = PTR_ERR(subchip->power_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 						     &pm80x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if (IS_ERR(subchip->regmap_power)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		ret = PTR_ERR(subchip->regmap_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 			"Failed to allocate regmap_power: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	i2c_set_clientdata(subchip->power_page, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	/* PM800 block GPADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	subchip->gpadc_page = i2c_new_dummy_device(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 					    subchip->gpadc_page_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (IS_ERR(subchip->gpadc_page)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		ret = PTR_ERR(subchip->gpadc_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 						     &pm80x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	if (IS_ERR(subchip->regmap_gpadc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		ret = PTR_ERR(subchip->regmap_gpadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 			"Failed to allocate regmap_gpadc: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	i2c_set_clientdata(subchip->gpadc_page, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void pm800_pages_exit(struct pm80x_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	struct pm80x_subchip *subchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	subchip = chip->subchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	if (subchip && subchip->power_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		i2c_unregister_device(subchip->power_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	if (subchip && subchip->gpadc_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		i2c_unregister_device(subchip->gpadc_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int device_800_init(struct pm80x_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 				     struct pm80x_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	 * alarm wake up bit will be clear in device_irq_init(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	 * read before that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	if (val & PM800_ALARM_WAKEUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		if (pdata && pdata->rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 			pdata->rtc->rtc_wakeup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	ret = device_gpadc_init(chip, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	chip->regmap_irq_chip = &pm800_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	ret = device_irq_init_800(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	ret = device_onkey_init(chip, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		dev_err(chip->dev, "Failed to add onkey subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		goto out_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	ret = device_rtc_init(chip, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		dev_err(chip->dev, "Failed to add rtc subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	ret = device_regulator_init(chip, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		dev_err(chip->dev, "Failed to add regulators subdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) out_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	mfd_remove_devices(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	device_irq_exit_800(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int pm800_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 				 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	struct pm80x_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	struct pm80x_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	struct pm80x_subchip *subchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	ret = pm80x_init(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		dev_err(&client->dev, "pm800_init fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		goto out_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	chip = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	/* init subchip for PM800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	subchip =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	    devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 			 GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	if (!subchip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		goto err_subchip_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	/* pm800 has 2 addtional pages to support power and gpadc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	subchip->power_page_addr = client->addr + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	subchip->gpadc_page_addr = client->addr + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	chip->subchip = subchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	ret = pm800_pages_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		dev_err(&client->dev, "pm800_pages_init failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		goto err_device_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	ret = device_800_init(chip, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		dev_err(chip->dev, "Failed to initialize 88pm800 devices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 		goto err_device_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	if (pdata && pdata->plat_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 		pdata->plat_config(chip, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) err_device_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	pm800_pages_exit(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) err_subchip_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	pm80x_deinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) out_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int pm800_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	struct pm80x_chip *chip = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	mfd_remove_devices(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	device_irq_exit_800(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	pm800_pages_exit(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	pm80x_deinit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static struct i2c_driver pm800_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 		.name = "88PM800",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 		.pm = &pm80x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	.probe = pm800_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	.remove = pm800_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	.id_table = pm80x_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int __init pm800_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	return i2c_add_driver(&pm800_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) subsys_initcall(pm800_i2c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static void __exit pm800_i2c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	i2c_del_driver(&pm800_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) module_exit(pm800_i2c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MODULE_LICENSE("GPL");