^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/drivers/message/fusion/mptbase.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This is the Fusion MPT base driver which supports multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (SCSI + LAN) specialized protocol drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * For use with LSI PCI chip/adapter(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * running LSI Fusion MPT (Message Passing Technology) firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 1999-2008 LSI Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (mailto:DL-MPTFusionLinux@lsi.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) NO WARRANTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) solely responsible for determining the appropriateness of using and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) distributing the Program and assumes all risks associated with its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) exercise of rights under this Agreement, including but not limited to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) the risks and costs of program errors, damage to or loss of data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) programs or equipment, and unavailability or interruption of operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DISCLAIMER OF LIABILITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/kdev_t.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/interrupt.h> /* needed for in_interrupt() proto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <scsi/scsi_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include "mptbase.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include "lsi/mpi_log_fc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define my_NAME "Fusion MPT base driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define my_VERSION MPT_LINUX_VERSION_COMMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MYNAM "mptbase"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_AUTHOR(MODULEAUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MODULE_DESCRIPTION(my_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MODULE_VERSION(my_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * cmd line parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int mpt_msi_enable_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) module_param(mpt_msi_enable_spi, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_PARM_DESC(mpt_msi_enable_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) " Enable MSI Support for SPI controllers (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int mpt_msi_enable_fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) module_param(mpt_msi_enable_fc, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_PARM_DESC(mpt_msi_enable_fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) " Enable MSI Support for FC controllers (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int mpt_msi_enable_sas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) module_param(mpt_msi_enable_sas, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODULE_PARM_DESC(mpt_msi_enable_sas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) " Enable MSI Support for SAS controllers (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int mpt_channel_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) module_param(mpt_channel_mapping, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int mpt_debug_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int mpt_set_debug_level(const char *val, const struct kernel_param *kp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) &mpt_debug_level, 0600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MODULE_PARM_DESC(mpt_debug_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) " debug level - refer to mptdebug.h - (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int mpt_fwfault_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) EXPORT_SYMBOL(mpt_fwfault_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) module_param(mpt_fwfault_debug, int, 0600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_PARM_DESC(mpt_fwfault_debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [MPT_MAX_CALLBACKNAME_LEN+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef MFCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int mfcounter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PRINT_MF_COUNT 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Public data...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define WHOINIT_UNKNOWN 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Private data...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Adapter link list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) LIST_HEAD(ioc_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Callback lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Protocol driver class lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Event handler lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Reset handler lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct proc_dir_entry *mpt_proc_root_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Driver Callback Index's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static u8 last_drv_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Forward protos...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static irqreturn_t mpt_interrupt(int irq, void *bus_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MPT_FRAME_HDR *reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 *req, int replyBytes, u16 *u16reply, int maxwait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void mpt_adapter_disable(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void mpt_adapter_dispose(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int PrimeIocFifos(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int GetLanConfigPages(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int GetIoUnitPage2(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int mpt_summary_proc_show(struct seq_file *m, void *v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int mpt_version_proc_show(struct seq_file *m, void *v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int mpt_iocinfo_proc_show(struct seq_file *m, void *v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int ProcessEventNotification(MPT_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EventNotificationReply_t *evReply, int *evHandlers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* module entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int __init fusion_init (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void __exit fusion_exit (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CHIPREG_READ32(addr) readl_relaxed(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CHIPREG_READ32_dmasync(addr) readl(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CHIPREG_WRITE32(addr,val) writel(val, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pci_disable_io_access(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u16 command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) command_reg &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pci_write_config_word(pdev, PCI_COMMAND, command_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pci_enable_io_access(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u16 command_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) command_reg |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pci_write_config_word(pdev, PCI_COMMAND, command_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int mpt_set_debug_level(const char *val, const struct kernel_param *kp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int ret = param_set_int(val, kp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MPT_ADAPTER *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) list_for_each_entry(ioc, &ioc_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ioc->debug_level = mpt_debug_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * mpt_get_cb_idx - obtain cb_idx for registered driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @dclass: class driver enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Returns cb_idx, or zero means it wasn't found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (MptDriverClass[cb_idx] == dclass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * mpt_is_discovery_complete - determine if discovery has completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @ioc: per adatper instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * Returns 1 when discovery completed, else zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mpt_is_discovery_complete(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ConfigExtendedPageHeader_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SasIOUnitPage0_t *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) memset(&cfg, 0, sizeof(CONFIGPARMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cfg.cfghdr.ehdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if ((mpt_config(ioc, &cfg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!hdr.ExtPageLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) &dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) cfg.physAddr = dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if ((mpt_config(ioc, &cfg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) goto out_free_consistent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!(buffer->PhyData[0].PortFlags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) out_free_consistent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) buffer, dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * mpt_remove_dead_ioc_func - kthread context to remove dead ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * @arg: input argument, used to derive ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Return 0 if controller is removed from pci subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Return -1 for other case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int mpt_remove_dead_ioc_func(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pdev = ioc->pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pci_stop_and_remove_bus_device_locked(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * mpt_fault_reset_work - work performed on workq after ioc fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @work: input argument, used to derive ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mpt_fault_reset_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MPT_ADAPTER *ioc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) container_of(work, MPT_ADAPTER, fault_reset_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 ioc_raw_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MPT_SCSI_HOST *hd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct task_struct *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ioc->ioc_reset_in_progress || !ioc->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ioc_raw_state = mpt_GetIocState(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ioc->name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Call mptscsih_flush_pending_cmds callback so that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * flush all pending commands back to OS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * This call is required to aovid deadlock at block layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Dead IOC will fail to do diag reset,and this call is safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * since dead ioc will never return any command back from HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hd = shost_priv(ioc->sh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ioc->schedule_dead_ioc_flush_running_cmds(hd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*Remove the Dead Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) p = kthread_run(mpt_remove_dead_ioc_func, ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "mpt_dead_ioc_%d", ioc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (IS_ERR(p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "%s: Running mpt_dead_ioc thread failed !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ioc->name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "%s: Running mpt_dead_ioc thread success !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ioc->name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return; /* don't rearm timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if ((ioc_raw_state & MPI_IOC_STATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) == MPI_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ioc->name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) __func__, (rc == 0) ? "success" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ioc_raw_state = mpt_GetIocState(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "reset (%04xh)\n", ioc->name, ioc_raw_state &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MPI_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if ((mpt_is_discovery_complete(ioc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "discovery_quiesce_io flag\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ioc->sas_discovery_quiesce_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Take turns polling alternate controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ioc = ioc->alt_ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* rearm the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ioc->reset_work_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msecs_to_jiffies(MPT_POLLING_INTERVAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Process turbo (context) reply...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MPT_FRAME_HDR *mf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MPT_FRAME_HDR *mr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u16 req_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ioc->name, pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) req_idx = pa & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) cb_idx = (pa & 0x00FF0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case MPI_CONTEXT_REPLY_TYPE_LAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Blind set of mf to NULL here was fatal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * after lan_reply says "freeme"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Fix sort of combined with an optimization here;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * added explicit check for case where lan_reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * was just returning 1 and doing nothing else.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * For this case skip the callback, but set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * proper mf value first here:-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if ((pa & 0x58000000) == 0x58000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) req_idx = pa & 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mpt_free_msg_frame(ioc, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cb_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Check for (valid) IO callback! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MptCallbacks[cb_idx] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __func__, ioc->name, cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (MptCallbacks[cb_idx](ioc, mf, mr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mpt_free_msg_frame(ioc, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mpt_reply(MPT_ADAPTER *ioc, u32 pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MPT_FRAME_HDR *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MPT_FRAME_HDR *mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u16 req_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int freeme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 reply_dma_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u16 ioc_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* non-TURBO reply! Hmmm, something may be up...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Newest turbo reply mechanism; get address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Map DMA address of reply header to cpu address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * pa is 32 bits - but the dma address may be 32 or 64 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * get offset based only only the low addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reply_dma_low = (pa <<= 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) (reply_dma_low - ioc->reply_frames_low_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Check/log IOC log info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ioc->bus_type == FC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mpt_fc_log_info(ioc, log_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) else if (ioc->bus_type == SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mpt_spi_log_info(ioc, log_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) else if (ioc->bus_type == SAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mpt_sas_log_info(ioc, log_info, cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ioc_stat & MPI_IOCSTATUS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Check for (valid) IO callback! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MptCallbacks[cb_idx] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) __func__, ioc->name, cb_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) freeme = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) freeme = MptCallbacks[cb_idx](ioc, mf, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Flush (non-TURBO) reply with a WRITE! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (freeme)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mpt_free_msg_frame(ioc, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * @irq: irq number (not used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * This routine is registered via the request_irq() kernel API call,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * and handles all interrupts generated from a specific MPT adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * (also referred to as a IO Controller or IOC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * This routine must clear the interrupt from the adapter and does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * so by reading the reply FIFO. Multiple replies may be processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * per single call to this routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * This routine handles register-level access of the adapter but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * dispatches (calls) a protocol-specific callback routine to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * the protocol-specific details of the MPT request completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mpt_interrupt(int irq, void *bus_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MPT_ADAPTER *ioc = bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (pa == 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Drain the reply FIFO!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (pa & MPI_ADDRESS_REPLY_A_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mpt_reply(ioc, pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mpt_turbo_reply(ioc, pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) } while (pa != 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * mptbase_reply - MPT base driver's callback routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * @req: Pointer to original MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * @reply: Pointer to MPT reply frame (NULL if TurboReply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * MPT base driver's callback routine; all base driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * "internal" request/reply processing is routed here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Currently used for EventNotification and EventAck handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Returns 1 indicating original alloc'd request frame ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * should be freed, or 0 if it shouldn't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) EventNotificationReply_t *pEventReply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int evHandlers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int freereq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) switch (reply->u.hdr.Function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) case MPI_FUNCTION_EVENT_NOTIFICATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pEventReply = (EventNotificationReply_t *)reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) evHandlers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ProcessEventNotification(ioc, pEventReply, &evHandlers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) event = le32_to_cpu(pEventReply->Event) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) freereq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (event != MPI_EVENT_EVENT_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case MPI_FUNCTION_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case MPI_FUNCTION_SAS_IO_UNIT_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) memcpy(ioc->mptbase_cmds.reply, reply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) min(MPT_DEFAULT_FRAME_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 4 * reply->u.reply.MsgLength));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) complete(&ioc->mptbase_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) freereq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) freereq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case MPI_FUNCTION_EVENT_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "EventAck reply received\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "Unexpected msg function (=%02Xh) reply received!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ioc->name, reply->u.hdr.Function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Conditionally tell caller to free the original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * EventNotification/EventAck/unexpected request frame!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return freereq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * mpt_register - Register protocol-specific main callback handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * @cbfunc: callback function pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * @func_name: call function's name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * This routine is called by a protocol-specific driver (SCSI host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * LAN, SCSI target) to register its reply callback routine. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * protocol-specific driver must do this before it will be able to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * use any IOC resources, such as obtaining request frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * NOTES: The SCSI protocol driver currently calls this routine thrice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * in order to register separate callbacks; one for "normal" SCSI IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * one for MptScsiTaskMgmt requests; one for Scan/DV requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * Returns u8 valued "handle" in the range (and S.O.D. order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * {N,...,7,6,5,...,1} if successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * considered an error by the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * Search for empty callback slot in this order: {N,...,7,6,5,...,1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * (slot/handle 0 is reserved!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (MptCallbacks[cb_idx] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MptCallbacks[cb_idx] = cbfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MptDriverClass[cb_idx] = dclass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MptEvHandlers[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) last_drv_idx = cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) strlcpy(MptCallbacksName[cb_idx], func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) MPT_MAX_CALLBACKNAME_LEN+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return last_drv_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * mpt_deregister - Deregister a protocol drivers resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * @cb_idx: previously registered callback handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * Each protocol-specific driver should call this routine when its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * module is unloaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mpt_deregister(u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) MptCallbacks[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) MptEvHandlers[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) last_drv_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * mpt_event_register - Register protocol-specific event callback handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * @cb_idx: previously registered (via mpt_register) callback handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * @ev_cbfunc: callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * This routine can be called by one or more protocol-specific drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * if/when they choose to be notified of MPT events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Returns 0 for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) MptEvHandlers[cb_idx] = ev_cbfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * mpt_event_deregister - Deregister protocol-specific event callback handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * @cb_idx: previously registered callback handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * Each protocol-specific driver should call this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * when it does not (or can no longer) handle events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * or when its module is unloaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mpt_event_deregister(u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) MptEvHandlers[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * mpt_reset_register - Register protocol-specific IOC reset handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * @cb_idx: previously registered (via mpt_register) callback handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * @reset_func: reset function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * This routine can be called by one or more protocol-specific drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * if/when they choose to be notified of IOC resets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * Returns 0 for success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) MptResetHandlers[cb_idx] = reset_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * mpt_reset_deregister - Deregister protocol-specific IOC reset handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * @cb_idx: previously registered callback handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * Each protocol-specific driver should call this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * when it does not (or can no longer) handle IOC reset handling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * or when its module is unloaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mpt_reset_deregister(u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) MptResetHandlers[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * mpt_device_driver_register - Register device driver hooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * @dd_cbfunc: driver callbacks struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * @cb_idx: MPT protocol driver index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) MPT_ADAPTER *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) const struct pci_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* call per pci device probe entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) list_for_each_entry(ioc, &ioc_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) id = ioc->pcidev->driver ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ioc->pcidev->driver->id_table : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (dd_cbfunc->probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dd_cbfunc->probe(ioc->pcidev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * mpt_device_driver_deregister - DeRegister device driver hooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * @cb_idx: MPT protocol driver index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) mpt_device_driver_deregister(u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct mpt_pci_driver *dd_cbfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) MPT_ADAPTER *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) list_for_each_entry(ioc, &ioc_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (dd_cbfunc->remove)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dd_cbfunc->remove(ioc->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) MptDeviceDriverHandlers[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * mpt_get_msg_frame - Obtain an MPT request frame from the pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * @cb_idx: Handle of registered MPT protocol driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * Obtain an MPT request frame from the pool (of 1024) that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * allocated per MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * Returns pointer to a MPT request frame or %NULL if none are available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * or IOC is not active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MPT_FRAME_HDR*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) MPT_FRAME_HDR *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u16 req_idx; /* Request index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* validate handle and ioc identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #ifdef MFCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (!ioc->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "returning NULL!\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* If interrupts are not attached, do not return a request frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!ioc->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) spin_lock_irqsave(&ioc->FreeQlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!list_empty(&ioc->FreeQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int req_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u.frame.linkage.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) list_del(&mf->u.frame.linkage.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) mf->u.frame.linkage.arg1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* u16! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) req_idx = req_offset / ioc->req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* Default, will be changed if necessary in SG generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #ifdef MFCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ioc->mfcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) spin_unlock_irqrestore(&ioc->FreeQlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #ifdef MFCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (mf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ioc->req_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) mfcounter++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (mfcounter == PRINT_MF_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ioc->mfcnt, ioc->req_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ioc->name, cb_idx, ioc->id, mf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * @cb_idx: Handle of registered MPT protocol driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * @mf: Pointer to MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * This routine posts an MPT request frame to the request post FIFO of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * specific MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u32 mf_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int req_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u16 req_idx; /* Request index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* ensure values are reset properly! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* u16! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) req_idx = req_offset / ioc->req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ioc->RequestNB[req_idx]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * @cb_idx: Handle of registered MPT protocol driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * @mf: Pointer to MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * Send a protocol-specific MPT request frame to an IOC using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * hi-priority request queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * This routine posts an MPT request frame to the request post FIFO of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * specific MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u32 mf_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int req_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u16 req_idx; /* Request index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* ensure values are reset properly! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) req_idx = req_offset / ioc->req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ioc->name, mf_dma_addr, req_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * mpt_free_msg_frame - Place MPT request frame back on FreeQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * @mf: Pointer to MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * This routine places a MPT request frame back on the MPT adapter's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * FreeQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Put Request back on FreeQ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) spin_lock_irqsave(&ioc->FreeQlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* signature to know if this mf is freed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) list_add(&mf->u.frame.linkage.list, &ioc->FreeQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #ifdef MFCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ioc->mfcnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) spin_unlock_irqrestore(&ioc->FreeQlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * mpt_add_sge - Place a simple 32 bit SGE at address pAddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * @pAddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * @flagslength: SGE flags and data transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * @dma_addr: Physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * This routine places a MPT request frame back on the MPT adapter's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * FreeQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pSge->FlagsLength = cpu_to_le32(flagslength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) pSge->Address = cpu_to_le32(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * @pAddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * @flagslength: SGE flags and data transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * @dma_addr: Physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * This routine places a MPT request frame back on the MPT adapter's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * FreeQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pSge->Address.Low = cpu_to_le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) (lower_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) pSge->Address.High = cpu_to_le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) (upper_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pSge->FlagsLength = cpu_to_le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * @pAddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * @flagslength: SGE flags and data transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * @dma_addr: Physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * This routine places a MPT request frame back on the MPT adapter's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * FreeQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pSge->Address.Low = cpu_to_le32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) (lower_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) tmp = (u32)(upper_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * 1078 errata workaround for the 36GB limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) flagslength |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) tmp |= (1<<31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (mpt_debug_level & MPT_DEBUG_36GB_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) printk(KERN_DEBUG "1078 P0M2 addressing for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "addr = 0x%llx len = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) (unsigned long long)dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) MPI_SGE_LENGTH(flagslength));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) pSge->Address.High = cpu_to_le32(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pSge->FlagsLength = cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * mpt_add_chain - Place a 32 bit chain SGE at address pAddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * @pAddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * @next: nextChainOffset value (u32's)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * @length: length of next SGL segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * @dma_addr: Physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) SGEChain32_t *pChain = (SGEChain32_t *) pAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) pChain->Length = cpu_to_le16(length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) pChain->NextChainOffset = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pChain->Address = cpu_to_le32(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * @pAddr: virtual address for SGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * @next: nextChainOffset value (u32's)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * @length: length of next SGL segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * @dma_addr: Physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) SGEChain64_t *pChain = (SGEChain64_t *) pAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 tmp = dma_addr & 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) pChain->Length = cpu_to_le16(length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) MPI_SGE_FLAGS_64_BIT_ADDRESSING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pChain->NextChainOffset = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) pChain->Address.Low = cpu_to_le32(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) tmp = (u32)(upper_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) pChain->Address.High = cpu_to_le32(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * mpt_send_handshake_request - Send MPT request via doorbell handshake method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * @cb_idx: Handle of registered MPT protocol driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * @reqBytes: Size of the request in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * @req: Pointer to MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * This routine is used exclusively to send MptScsiTaskMgmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * requests since they are required to be sent via doorbell handshake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * NOTE: It is the callers responsibility to byte-swap fields in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * request which are greater than 1 byte in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u8 *req_as_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* State is known to be good upon entering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * this function so issue the bus reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * Emulate what mpt_put_msg_frame() does /wrt to sanity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * setting cb_idx/req_idx. But ONLY if this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * is in proper (pre-alloc'd) request buffer range...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* Make sure there are no doorbells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) CHIPREG_WRITE32(&ioc->chip->Doorbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* Wait for IOC doorbell int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Read doorbell and check for active bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return -5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ioc->name, ii));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* Send request via doorbell handshake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) req_as_bytes = (u8 *) req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) for (ii = 0; ii < reqBytes/4; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) word = ((req_as_bytes[(ii*4) + 0] << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) (req_as_bytes[(ii*4) + 1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) (req_as_bytes[(ii*4) + 2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) (req_as_bytes[(ii*4) + 3] << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) r = -3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) r = -4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* Make sure there are no doorbells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * mpt_host_page_access_control - control the IOC's Host Page Buffer access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * @access_control_value: define bits below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * Provides mechanism for the host driver to control the IOC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * Host Page Buffer access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * Access Control Value - bits[15:12]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * 0h Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* return if in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (CHIPREG_READ32(&ioc->chip->Doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) & MPI_DOORBELL_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) CHIPREG_WRITE32(&ioc->chip->Doorbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) <<MPI_DOORBELL_FUNCTION_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) (access_control_value<<12)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* Wait for IOC to clear Doorbell Status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * mpt_host_page_alloc - allocate system memory for the fw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * @ioc: Pointer to pointer to IOC adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * @ioc_init: Pointer to ioc init config page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * If we already allocated memory in past, then resend the same pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) char *psge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) int flags_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) u32 host_page_buffer_sz=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if(!ioc->HostPageBuffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) host_page_buffer_sz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if(!host_page_buffer_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return 0; /* fw doesn't need any host buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* spin till we get enough memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) while (host_page_buffer_sz > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ioc->HostPageBuffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dma_alloc_coherent(&ioc->pcidev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) host_page_buffer_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &ioc->HostPageBuffer_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ioc->HostPageBuffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ioc->name, ioc->HostPageBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) (u32)ioc->HostPageBuffer_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) host_page_buffer_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ioc->alloc_total += host_page_buffer_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ioc->HostPageBuffer_sz = host_page_buffer_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) host_page_buffer_sz -= (4*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if(!ioc->HostPageBuffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) "Failed to alloc memory for host_page_buffer!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return -999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) psge = (char *)&ioc_init->HostPageBufferSGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) MPI_SGE_FLAGS_SYSTEM_ADDRESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) MPI_SGE_FLAGS_HOST_TO_IOC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) MPI_SGE_FLAGS_END_OF_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) flags_length |= ioc->HostPageBuffer_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * @iocid: IOC unique identifier (integer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * @iocpp: Pointer to pointer to IOC adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * Given a unique IOC identifier, set pointer to the associated MPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * Returns iocid and sets iocpp if iocid is found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * Returns -1 if iocid is not found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) MPT_ADAPTER *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) list_for_each_entry(ioc,&ioc_list,list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (ioc->id == iocid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) *iocpp =ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return iocid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) *iocpp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * mpt_get_product_name - returns product string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * @vendor: pci vendor id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * @device: pci device id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * @revision: pci revision id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * Returns product string displayed when driver loads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static const char*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mpt_get_product_name(u16 vendor, u16 device, u8 revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) char *product_str = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (vendor == PCI_VENDOR_ID_BROCADE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) switch (device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) case MPI_MANUFACTPAGE_DEVICEID_FC949E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) product_str = "BRE040 A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) product_str = "BRE040 A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) product_str = "BRE040";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) switch (device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case MPI_MANUFACTPAGE_DEVICEID_FC909:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) product_str = "LSIFC909 B1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) case MPI_MANUFACTPAGE_DEVICEID_FC919:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) product_str = "LSIFC919 B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) case MPI_MANUFACTPAGE_DEVICEID_FC929:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) product_str = "LSIFC929 B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) case MPI_MANUFACTPAGE_DEVICEID_FC919X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (revision < 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) product_str = "LSIFC919X A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) product_str = "LSIFC919XL A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) case MPI_MANUFACTPAGE_DEVICEID_FC929X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (revision < 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) product_str = "LSIFC929X A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) product_str = "LSIFC929XL A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) case MPI_MANUFACTPAGE_DEVICEID_FC939X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) product_str = "LSIFC939X A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) case MPI_MANUFACTPAGE_DEVICEID_FC949X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) product_str = "LSIFC949X A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) case MPI_MANUFACTPAGE_DEVICEID_FC949E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) product_str = "LSIFC949E A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) product_str = "LSIFC949E A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) product_str = "LSIFC949E";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) case MPI_MANUFACTPAGE_DEVID_53C1030:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) product_str = "LSI53C1030 A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) product_str = "LSI53C1030 B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) product_str = "LSI53C1030 B1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) case 0x07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) product_str = "LSI53C1030 B2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) case 0x08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) product_str = "LSI53C1030 C0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) case 0x80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) product_str = "LSI53C1030T A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) case 0x83:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) product_str = "LSI53C1030T A2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case 0x87:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) product_str = "LSI53C1030T A3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) case 0xc1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) product_str = "LSI53C1020A A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) product_str = "LSI53C1030";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) product_str = "LSI53C1035 A2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) product_str = "LSI53C1035 B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) product_str = "LSI53C1035";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) case MPI_MANUFACTPAGE_DEVID_SAS1064:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) product_str = "LSISAS1064 A1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) product_str = "LSISAS1064 A2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) product_str = "LSISAS1064 A3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) product_str = "LSISAS1064 A4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) product_str = "LSISAS1064";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) case MPI_MANUFACTPAGE_DEVID_SAS1064E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) product_str = "LSISAS1064E A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) product_str = "LSISAS1064E B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) product_str = "LSISAS1064E B1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) product_str = "LSISAS1064E B2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) case 0x08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) product_str = "LSISAS1064E B3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) product_str = "LSISAS1064E";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) case MPI_MANUFACTPAGE_DEVID_SAS1068:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) product_str = "LSISAS1068 A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) product_str = "LSISAS1068 B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) product_str = "LSISAS1068 B1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) product_str = "LSISAS1068";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) case MPI_MANUFACTPAGE_DEVID_SAS1068E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) product_str = "LSISAS1068E A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) product_str = "LSISAS1068E B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) product_str = "LSISAS1068E B1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) product_str = "LSISAS1068E B2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case 0x08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) product_str = "LSISAS1068E B3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) product_str = "LSISAS1068E";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) case MPI_MANUFACTPAGE_DEVID_SAS1078:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) switch (revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) product_str = "LSISAS1078 A0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) product_str = "LSISAS1078 B0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) product_str = "LSISAS1078 C0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) product_str = "LSISAS1078 C1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) product_str = "LSISAS1078 C2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) product_str = "LSISAS1078";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return product_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * mpt_mapresources - map in memory mapped io
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * @ioc: Pointer to pointer to IOC adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) mpt_mapresources(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) u8 __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) resource_size_t mem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) u32 msize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) u32 psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) int r = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) pdev = ioc->pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (pci_enable_device_mem(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) "failed\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) "MEM failed\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) goto out_pci_disable_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (sizeof(dma_addr_t) > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) const uint64_t required_mask = dma_get_required_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) (&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (required_mask > DMA_BIT_MASK(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) && !pci_set_consistent_dma_mask(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ioc->dma_mask = DMA_BIT_MASK(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) && !pci_set_consistent_dma_mask(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ioc->dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ioc->name, pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) goto out_pci_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) && !pci_set_consistent_dma_mask(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) ioc->dma_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ioc->name, pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) goto out_pci_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) mem_phys = msize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) port = psize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (psize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* Get I/O space! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) port = pci_resource_start(pdev, ii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) psize = pci_resource_len(pdev, ii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (msize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) /* Get memmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) mem_phys = pci_resource_start(pdev, ii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) msize = pci_resource_len(pdev, ii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) ioc->mem_size = msize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) mem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* Get logical ptr for PciMem0 space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) /*mem = ioremap(mem_phys, msize);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) mem = ioremap(mem_phys, msize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (mem == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) " memory!\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) r = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) goto out_pci_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ioc->memmap = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) ioc->name, mem, (unsigned long long)mem_phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) ioc->mem_phys = mem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) ioc->chip = (SYSIF_REGS __iomem *)mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* Save Port IO values in case we need to do downloadboot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ioc->pio_mem_phys = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ioc->pio_chip = (SYSIF_REGS __iomem *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) out_pci_release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) pci_release_selected_regions(pdev, ioc->bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) out_pci_disable_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * mpt_attach - Install a PCI intelligent MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * @pdev: Pointer to pci_dev structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * @id: PCI device ID information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * This routine performs all the steps necessary to bring the IOC of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) * a MPT adapter to a OPERATIONAL state. This includes registering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * memory regions, registering the interrupt, and allocating request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) * and reply memory pools.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) * This routine also pre-fetches the LAN MAC address of a Fibre Channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * TODO: Add support for polled controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) MPT_ADAPTER *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) int r = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) u8 pcixcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static int mpt_ids = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct proc_dir_entry *dent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (ioc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) ioc->id = mpt_ids++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) sprintf(ioc->name, "ioc%d", ioc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * set initial debug level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * (refer to mptdebug.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ioc->debug_level = mpt_debug_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (mpt_debug_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ioc->pcidev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (mpt_mapresources(ioc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) goto out_free_ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * Setting up proper handlers for scatter gather handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (ioc->dma_mask == DMA_BIT_MASK(64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ioc->add_sge = &mpt_add_sge_64bit_1078;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) ioc->add_sge = &mpt_add_sge_64bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ioc->add_chain = &mpt_add_chain_64bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ioc->sg_addr_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ioc->add_sge = &mpt_add_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ioc->add_chain = &mpt_add_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ioc->sg_addr_size = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ioc->alloc_total = sizeof(MPT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) spin_lock_init(&ioc->taskmgmt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) mutex_init(&ioc->internal_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) init_completion(&ioc->internal_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) mutex_init(&ioc->mptbase_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) init_completion(&ioc->mptbase_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) mutex_init(&ioc->taskmgmt_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) init_completion(&ioc->taskmgmt_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* Initialize the event logging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ioc->eventTypes = 0; /* None */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ioc->eventContext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ioc->eventLogSize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) ioc->events = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #ifdef MFCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ioc->mfcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ioc->sh = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ioc->cached_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /* Initialize SCSI Config Data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* Initialize the fc rport list head.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) INIT_LIST_HEAD(&ioc->fc_rports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /* Find lookup slot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) INIT_LIST_HEAD(&ioc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* Initialize workqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) "mpt_poll_%d", ioc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) WQ_MEM_RECLAIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (!ioc->reset_work_q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) goto out_unmap_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ioc->name, &ioc->facts, &ioc->pfacts[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) pdev->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) switch (pdev->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) case MPI_MANUFACTPAGE_DEVICEID_FC939X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) case MPI_MANUFACTPAGE_DEVICEID_FC949X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ioc->errata_flag_1064 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) case MPI_MANUFACTPAGE_DEVICEID_FC909:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) case MPI_MANUFACTPAGE_DEVICEID_FC929:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) case MPI_MANUFACTPAGE_DEVICEID_FC919:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) case MPI_MANUFACTPAGE_DEVICEID_FC949E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ioc->bus_type = FC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) case MPI_MANUFACTPAGE_DEVICEID_FC929X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (pdev->revision < XL_929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* 929X Chip Fix. Set Split transactions level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * for PCIX. Set MOST bits to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) pci_read_config_byte(pdev, 0x6a, &pcixcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) pcixcmd &= 0x8F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) pci_write_config_byte(pdev, 0x6a, pcixcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* 929XL Chip Fix. Set MMRBC to 0x08.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) pci_read_config_byte(pdev, 0x6a, &pcixcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) pcixcmd |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) pci_write_config_byte(pdev, 0x6a, pcixcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ioc->bus_type = FC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) case MPI_MANUFACTPAGE_DEVICEID_FC919X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* 919X Chip Fix. Set Split transactions level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) * for PCIX. Set MOST bits to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) pci_read_config_byte(pdev, 0x6a, &pcixcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) pcixcmd &= 0x8F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) pci_write_config_byte(pdev, 0x6a, pcixcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ioc->bus_type = FC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) case MPI_MANUFACTPAGE_DEVID_53C1030:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /* 1030 Chip Fix. Disable Split transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (pdev->revision < C0_1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) pci_read_config_byte(pdev, 0x6a, &pcixcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) pcixcmd &= 0x8F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) pci_write_config_byte(pdev, 0x6a, pcixcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ioc->bus_type = SPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) case MPI_MANUFACTPAGE_DEVID_SAS1064:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) case MPI_MANUFACTPAGE_DEVID_SAS1068:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ioc->errata_flag_1064 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ioc->bus_type = SAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) case MPI_MANUFACTPAGE_DEVID_SAS1064E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) case MPI_MANUFACTPAGE_DEVID_SAS1068E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) case MPI_MANUFACTPAGE_DEVID_SAS1078:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ioc->bus_type = SAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) switch (ioc->bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) case SAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ioc->msi_enable = mpt_msi_enable_sas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) case SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ioc->msi_enable = mpt_msi_enable_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) case FC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ioc->msi_enable = mpt_msi_enable_fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ioc->msi_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ioc->fw_events_off = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (ioc->errata_flag_1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) pci_disable_io_access(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) spin_lock_init(&ioc->FreeQlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) /* Disable all! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ioc->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) /* Set IOC ptr in the pcidev's driver data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) pci_set_drvdata(ioc->pcidev, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /* Set lookup ptr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) list_add_tail(&ioc->list, &ioc_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) mpt_detect_bound_ports(ioc, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) INIT_LIST_HEAD(&ioc->fw_event_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) spin_lock_init(&ioc->fw_event_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) WQ_MEM_RECLAIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (!ioc->fw_event_q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) r = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) goto out_remove_ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) CAN_SLEEP)) != 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ioc->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) destroy_workqueue(ioc->fw_event_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) ioc->fw_event_q = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) list_del(&ioc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ioc->alt_ioc->alt_ioc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) iounmap(ioc->memmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) if (pci_is_enabled(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (r != -5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) pci_release_selected_regions(pdev, ioc->bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) destroy_workqueue(ioc->reset_work_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ioc->reset_work_q = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) kfree(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* call per device driver probe entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if(MptDeviceDriverHandlers[cb_idx] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) MptDeviceDriverHandlers[cb_idx]->probe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) MptDeviceDriverHandlers[cb_idx]->probe(pdev,id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (dent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) proc_create_single_data("info", S_IRUGO, dent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) mpt_iocinfo_proc_show, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) proc_create_single_data("summary", S_IRUGO, dent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) mpt_summary_proc_show, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (!ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) msecs_to_jiffies(MPT_POLLING_INTERVAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) out_remove_ioc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) list_del(&ioc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ioc->alt_ioc->alt_ioc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) destroy_workqueue(ioc->reset_work_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ioc->reset_work_q = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) out_unmap_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) iounmap(ioc->memmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) pci_release_selected_regions(pdev, ioc->bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) out_free_ioc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) kfree(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) * mpt_detach - Remove a PCI intelligent MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) * @pdev: Pointer to pci_dev structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) mpt_detach(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) char pname[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) * Stop polling ioc for fault condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) wq = ioc->reset_work_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ioc->reset_work_q = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) cancel_delayed_work(&ioc->fault_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) destroy_workqueue(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) spin_lock_irqsave(&ioc->fw_event_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) wq = ioc->fw_event_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) ioc->fw_event_q = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) destroy_workqueue(wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) remove_proc_entry(pname, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) remove_proc_entry(pname, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) remove_proc_entry(pname, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) /* call per device driver remove entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if(MptDeviceDriverHandlers[cb_idx] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) MptDeviceDriverHandlers[cb_idx]->remove) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) MptDeviceDriverHandlers[cb_idx]->remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) /* Disable interrupts! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ioc->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) synchronize_irq(pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) /* Clear any lingering interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) CHIPREG_READ32(&ioc->chip->IntStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) mpt_adapter_dispose(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) * Power Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) * mpt_suspend - Fusion MPT base driver suspend routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * @pdev: Pointer to pci_dev structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) * @state: new state to enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) mpt_suspend(struct pci_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) u32 device_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) device_state = pci_choose_state(pdev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* put ioc into READY_STATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) "pci-suspend: IOC msg unit reset failed!\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ioc->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) /* Clear any lingering interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) free_irq(ioc->pci_irq, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (ioc->msi_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) pci_disable_msi(ioc->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ioc->pci_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) pci_release_selected_regions(pdev, ioc->bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) pci_set_power_state(pdev, device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) * mpt_resume - Fusion MPT base driver resume routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) * @pdev: Pointer to pci_dev structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) mpt_resume(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) u32 device_state = pdev->current_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) int recovery_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) device_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) pci_enable_wake(pdev, PCI_D0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) ioc->pcidev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) err = mpt_mapresources(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) if (ioc->dma_mask == DMA_BIT_MASK(64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) ioc->add_sge = &mpt_add_sge_64bit_1078;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ioc->add_sge = &mpt_add_sge_64bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) ioc->add_chain = &mpt_add_chain_64bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ioc->sg_addr_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ioc->add_sge = &mpt_add_sge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ioc->add_chain = &mpt_add_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) ioc->sg_addr_size = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) CHIPREG_READ32(&ioc->chip->Doorbell));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * Errata workaround for SAS pci express:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * Upon returning to the D0 state, the contents of the doorbell will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) * stale data, and this will incorrectly signal to the host driver that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) * the firmware is ready to process mpt commands. The workaround is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) * to issue a diagnostic reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (ioc->bus_type == SAS && (pdev->device ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /* bring ioc to operational state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) CAN_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (recovery_state != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) "error:[%x]\n", ioc->name, recovery_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) "pci-resume: success\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) if ((MptDriverClass[index] == MPTSPI_DRIVER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) ioc->bus_type != SPI) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) (MptDriverClass[index] == MPTFC_DRIVER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) ioc->bus_type != FC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) (MptDriverClass[index] == MPTSAS_DRIVER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) ioc->bus_type != SAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) /* make sure we only call the relevant reset handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) * for the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) return (MptResetHandlers[index])(ioc, reset_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) * mpt_do_ioc_recovery - Initialize or recover MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * @reason: Event word / reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) * This routine performs all the steps necessary to bring the IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) * to a OPERATIONAL state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) * This routine also pre-fetches the LAN MAC address of a Fibre Channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) * MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) * 0 for success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) * -1 if failed to get board READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) * -2 if READY but IOCFacts Failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) * -3 if READY but PrimeIOCFifos Failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) * -4 if READY but IOCInit Failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) * -5 if failed to enable_device and/or request_selected_regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) * -6 if failed to upload firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) int hard_reset_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) int alt_ioc_ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) int hard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) int rc=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) int reset_alt_ioc_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) int irq_allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) u8 *a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) /* Disable reply interrupts (also blocks FreeQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ioc->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) if (ioc->alt_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) if (ioc->alt_ioc->active ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) reason == MPT_HOSTEVENT_IOC_RECOVER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) reset_alt_ioc_active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) /* Disable alt-IOC's reply interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) * (and FreeQ) for a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ioc->alt_ioc->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) hard = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) hard = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) if (hard_reset_done == -4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) if (reset_alt_ioc_active && ioc->alt_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) dprintk(ioc, printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ioc->alt_ioc->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) "NOT READY WARNING!\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) /* hard_reset_done = 0 if a soft reset was performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) * and 1 if a hard reset was performed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) alt_ioc_ready = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ": alt-ioc Not ready WARNING!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) ioc->alt_ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) for (ii=0; ii<5; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) /* Get IOC facts! Allow 5 retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) if (ii == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) "Retry IocFacts failed rc=%x\n", ioc->name, rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) ret = -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) MptDisplayIocCapabilities(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (alt_ioc_ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) "Initial Alt IocFacts failed rc=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) ioc->name, rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /* Retry - alt IOC was initialized once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) alt_ioc_ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) reset_alt_ioc_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) MptDisplayIocCapabilities(ioc->alt_ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) pci_release_selected_regions(ioc->pcidev, ioc->bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) IORESOURCE_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (pci_enable_device(ioc->pcidev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) return -5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) "mpt"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) return -5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) * Device is reset now. It must have de-asserted the interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) * (if it was asserted) and it should be safe to register for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) * interrupt now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) ioc->pci_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (ioc->pcidev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) ioc->msi_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) IRQF_SHARED, ioc->name, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) printk(MYIOC_s_ERR_FMT "Unable to allocate "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) "interrupt %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) ioc->name, ioc->pcidev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) if (ioc->msi_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) pci_disable_msi(ioc->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) irq_allocated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ioc->pci_irq = ioc->pcidev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) pci_set_master(ioc->pcidev); /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) pci_set_drvdata(ioc->pcidev, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) "installed at interrupt %d\n", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) ioc->pcidev->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) /* Prime reply & request queues!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) * (mucho alloc's) Must be done prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) * init as upper addresses are needed for init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) * If fails, continue with alt-ioc processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) ret = -3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* May need to check/upload firmware & data here!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) * If fails, continue with alt-ioc processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) ret = -4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) // NEW!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) ioc->alt_ioc->name, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) alt_ioc_ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) reset_alt_ioc_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) if (alt_ioc_ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) alt_ioc_ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) reset_alt_ioc_active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ": alt-ioc: (%d) init failure WARNING!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ioc->alt_ioc->name, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) if (ioc->upload_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) "firmware upload required!\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* Controller is not operational, cannot do upload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) rc = mpt_do_upload(ioc, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (rc == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) * Maintain only one pointer to FW memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) * so there will not be two attempt to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) * downloadboot onboard dual function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) * chips (mpt_adapter_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) * mpt_diag_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) "mpt_upload: alt_%s has cached_fw=%p \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) ioc->cached_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) "firmware upload failure!\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) ret = -6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* Enable MPT base driver management of EventNotification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) * and EventAck handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) if ((ret == 0) && (!ioc->facts.EventState)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) "SendEventNotification\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) /* Enable! (reply interrupt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) ioc->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if (rc == 0) { /* alt ioc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) if (reset_alt_ioc_active && ioc->alt_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* (re)Enable alt-IOC! (reply interrupt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) "reply irq re-enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) ioc->alt_ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) MPI_HIM_DIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) ioc->alt_ioc->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) /* Add additional "reason" check before call to GetLanConfigPages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) * (combined with GetIoUnitPage2 call). This prevents a somewhat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) * recursive scenario; GetLanConfigPages times out, timer expired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) * routine calls HardResetHandler, which calls into here again,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) * and we try GetLanConfigPages again...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) * Initialize link list for inactive raid volumes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) mutex_init(&ioc->raid_data.inactive_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) switch (ioc->bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) case SAS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) /* clear persistency table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) if(ioc->facts.IOCExceptions &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) ret = mptbase_sas_persist_operation(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) MPI_SAS_OP_CLEAR_NOT_PRESENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) if(ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) /* Find IM volumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) mpt_findImVolumes(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) /* Check, and possibly reset, the coalescing value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) mpt_read_ioc_pg_1(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) case FC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) if ((ioc->pfacts[0].ProtocolFlags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) MPI_PORTFACTS_PROTOCOL_LAN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) * Pre-fetch the ports LAN MAC address!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) * (LANPage1_t stuff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) (void) GetLanConfigPages(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) "LanAddr = %pMR\n", ioc->name, a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) case SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) /* Get NVRAM and adapter maximums from SPP 0 and 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) mpt_GetScsiPortSettings(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) /* Get version and length of SDP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) mpt_readScsiDevicePageHeaders(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /* Find IM volumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) mpt_findImVolumes(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) /* Check, and possibly reset, the coalescing value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) mpt_read_ioc_pg_1(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) mpt_read_ioc_pg_4(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) GetIoUnitPage2(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) mpt_get_manufacturing_pg_0(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if ((ret != 0) && irq_allocated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) free_irq(ioc->pci_irq, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if (ioc->msi_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) pci_disable_msi(ioc->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) * mpt_detect_bound_ports - Search for matching PCI bus/dev_function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) * @pdev: Pointer to (struct pci_dev) structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) * Search for PCI bus/dev_function which matches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) * PCI bus/dev_function (+/-1) for newly discovered 929,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) * 929X, 1030 or 1035.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) * If match on PCI dev_function +/-1 is found, bind the two MPT adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * using alt_ioc pointer fields in their %MPT_ADAPTER structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) struct pci_dev *peer=NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) unsigned int slot = PCI_SLOT(pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) unsigned int func = PCI_FUNC(pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) MPT_ADAPTER *ioc_srch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) " searching for devfn match on %x or %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) ioc->name, pci_name(pdev), pdev->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) pdev->devfn, func-1, func+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (!peer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (!peer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) list_for_each_entry(ioc_srch, &ioc_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) struct pci_dev *_pcidev = ioc_srch->pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if (_pcidev == peer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) /* Paranoia checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) if (ioc->alt_ioc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) "Oops, already bound (%s <==> %s)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) ioc->name, ioc->name, ioc->alt_ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) } else if (ioc_srch->alt_ioc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) "Oops, already bound (%s <==> %s)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) ioc_srch->name, ioc_srch->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) ioc_srch->alt_ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) "FOUND! binding %s <==> %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) ioc->name, ioc->name, ioc_srch->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) ioc_srch->alt_ioc = ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) ioc->alt_ioc = ioc_srch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) pci_dev_put(peer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) * mpt_adapter_disable - Disable misbehaving MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) mpt_adapter_disable(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (ioc->cached_fw != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) "%s: Pushing FW onto adapter\n", __func__, ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) ioc->cached_fw, CAN_SLEEP)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) ": firmware downloadboot failure (%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) ioc->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) * Put the controller into ready state (if its not already)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) CAN_SLEEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) printk(MYIOC_s_ERR_FMT "%s: IOC msg unit "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) "reset failed to put ioc in ready state!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) ioc->name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) "failed!\n", ioc->name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /* Disable adapter interrupts! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) synchronize_irq(ioc->pcidev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) ioc->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) /* Clear any lingering interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) CHIPREG_READ32(&ioc->chip->IntStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) if (ioc->alloc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) sz = ioc->alloc_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) ioc->name, ioc->alloc, ioc->alloc_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) ioc->alloc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) ioc->reply_frames = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) ioc->req_frames = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) ioc->alloc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) ioc->alloc_total -= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) if (ioc->sense_buf_pool != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) ioc->sense_buf_pool_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) ioc->sense_buf_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) ioc->alloc_total -= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) if (ioc->events != NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) kfree(ioc->events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) ioc->events = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) ioc->alloc_total -= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) mpt_free_fw_memory(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) kfree(ioc->spi_data.nvram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) mpt_inactive_raid_list_free(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) kfree(ioc->raid_data.pIocPg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) kfree(ioc->raid_data.pIocPg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) ioc->spi_data.nvram = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) ioc->raid_data.pIocPg3 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) if (ioc->spi_data.pIocPg4 != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) sz = ioc->spi_data.IocPg4Sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) pci_free_consistent(ioc->pcidev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) ioc->spi_data.pIocPg4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) ioc->spi_data.IocPg4_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) ioc->spi_data.pIocPg4 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) ioc->alloc_total -= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) if (ioc->ReqToChain != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) kfree(ioc->ReqToChain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) kfree(ioc->RequestNB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) ioc->ReqToChain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) kfree(ioc->ChainToChain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) ioc->ChainToChain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) if (ioc->HostPageBuffer != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) if((ret = mpt_host_page_access_control(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) ": %s: host page buffers free failed (%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) ioc->name, __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) "HostPageBuffer free @ %p, sz=%d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) ioc->name, ioc->HostPageBuffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) ioc->HostPageBuffer_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) dma_free_coherent(&ioc->pcidev->dev, ioc->HostPageBuffer_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) ioc->HostPageBuffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) ioc->HostPageBuffer_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ioc->alloc_total -= ioc->HostPageBuffer_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) pci_set_drvdata(ioc->pcidev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) * mpt_adapter_dispose - Free all resources associated with an MPT adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) * This routine unregisters h/w resources and frees all alloc'd memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) * associated with a MPT adapter structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) mpt_adapter_dispose(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) int sz_first, sz_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) if (ioc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) sz_first = ioc->alloc_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) mpt_adapter_disable(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) if (ioc->pci_irq != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) free_irq(ioc->pci_irq, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) if (ioc->msi_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) pci_disable_msi(ioc->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) ioc->pci_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) if (ioc->memmap != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) iounmap(ioc->memmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) ioc->memmap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) pci_disable_device(ioc->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) pci_release_selected_regions(ioc->pcidev, ioc->bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) /* Zap the adapter lookup ptr! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) list_del(&ioc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) sz_last = ioc->alloc_total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) ioc->alt_ioc->alt_ioc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) kfree(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) * MptDisplayIocCapabilities - Disply IOC's capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) * @ioc: Pointer to MPT adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) printk(KERN_INFO "%s: ", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) if (ioc->prod_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) pr_cont("%s: ", ioc->prod_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) pr_cont("Capabilities={");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) pr_cont("Initiator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) pr_cont("%sTarget", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) pr_cont("%sLAN", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) * This would probably evoke more questions than it's worth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) pr_cont("%sLogBusAddr", i ? "," : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) pr_cont("}\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) * MakeIocReady - Get IOC to a READY state, using KickStart if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) * @force: Force hard KickStart of IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) * 1 - DIAG reset and READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) * 0 - READY initially OR soft reset and READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) * -1 - Any failure on KickStart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) * -2 - Msg Unit Reset Failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) * -3 - IO Unit Reset Failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) * -4 - IOC owned by a PEER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) int statefault = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) int cntdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) int hard_reset_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) int whoinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) /* Get current [raw] IOC state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) ioc_state = mpt_GetIocState(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) * Check to see if IOC got left/stuck in doorbell handshake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) * grip of death. If so, hard reset the IOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) if (ioc_state & MPI_DOORBELL_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) statefault = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) /* Is it already READY? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) if (!statefault &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) "IOC is in READY state\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * Check to see if IOC is in FAULT state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) statefault = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) * Hmmm... Did it get left operational?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) /* Check WhoInit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) * If PCI Peer, exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) * Else, if no fault conditions are present, issue a MessageUnitReset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) * Else, fall through to KickStart case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) "whoinit 0x%x statefault %d force %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) ioc->name, whoinit, statefault, force));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) if (whoinit == MPI_WHOINIT_PCI_PEER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) return -4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) if ((statefault == 0 ) && (force == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) statefault = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (hard_reset_done < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) * Loop here waiting for IOC to come READY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) ii = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) * BIOS or previous driver load left IOC in OP state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) * Reset messaging FIFOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) return -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) } else if (ioc_state == MPI_IOC_STATE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) * Something is wrong. Try to get IOC back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) * to a known state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) return -3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) ii++; cntdn--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) if (!cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) "Wait IOC_READY state (0x%x) timeout(%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) ioc->name, ioc_state, (int)((ii+5)/HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) mdelay (1); /* 1 msec delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) if (statefault < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) statefault == 1 ? "stuck handshake" : "IOC FAULT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) return hard_reset_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) * mpt_GetIocState - Get the current state of a MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) * @cooked: Request raw or cooked IOC state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) * Returns all IOC Doorbell register bits if cooked==0, else just the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) * Doorbell bits in MPI_IOC_STATE_MASK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) u32 s, sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) /* Get! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) s = CHIPREG_READ32(&ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) sc = s & MPI_IOC_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) /* Save! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) ioc->last_state = sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) return cooked ? sc : s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) * GetIocFacts - Send IOCFacts request to MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) * @reason: If recovery, only update facts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) IOCFacts_t get_facts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) IOCFactsReply_t *facts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) int req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) int reply_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) u32 status, vv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) u8 shiftFactor=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) /* IOC *must* NOT be in RESET state! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) if (ioc->last_state == MPI_IOC_STATE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) printk(KERN_ERR MYNAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) ioc->name, ioc->last_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) return -44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) facts = &ioc->facts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) /* Destination (reply area)... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) reply_sz = sizeof(*facts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) memset(facts, 0, reply_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) /* Request area (get_facts on the stack right now!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) req_sz = sizeof(get_facts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) memset(&get_facts, 0, req_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) get_facts.Function = MPI_FUNCTION_IOC_FACTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) /* Assert: All other get_facts fields are zero! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) ioc->name, req_sz, reply_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) /* No non-zero fields in the get_facts request are greater than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) * 1 byte in size, so we can just fire it off as is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) * Now byte swap (GRRR) the necessary fields before any further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) * inspection of reply contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) * But need to do some sanity checks on MsgLength (byte) field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) * to make sure we don't zero IOC's req_sz!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) /* Did we get a valid reply? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) * If not been here, done that, save off first WhoInit value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) ioc->FirstWhoInit = facts->WhoInit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) facts->MsgContext = le32_to_cpu(facts->MsgContext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) status = le16_to_cpu(facts->IOCStatus) & MPI_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) /* CHECKME! IOCStatus, IOCLogInfo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) * FC f/w version changed between 1.1 and 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) * Old: u16{Major(4),Minor(4),SubMinor(8)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) * New: u32{Major(8),Minor(8),Unit(8),Dev(8)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) if (facts->MsgVersion < MPI_VERSION_01_02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) * Handle old FC f/w style, convert to new...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) facts->FWVersion.Word =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) ((oldv<<12) & 0xFF000000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) ((oldv<<8) & 0x000FFF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) facts->ProductID = le16_to_cpu(facts->ProductID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) ioc->ir_firmware = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) facts->CurrentHostMfaHighAddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) le32_to_cpu(facts->CurrentHostMfaHighAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) facts->CurrentSenseBufferHighAddr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) le32_to_cpu(facts->CurrentSenseBufferHighAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) facts->CurReplyFrameSize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) le16_to_cpu(facts->CurReplyFrameSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) * Older MPI-1.00.xx struct had 13 dwords, and enlarged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) * to 14 in MPI-1.01.0x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) facts->MsgVersion > MPI_VERSION_01_00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) facts->FWImageSize = ALIGN(facts->FWImageSize, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) if (!facts->RequestFrameSize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) /* Something is wrong! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) return -55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) r = sz = facts->BlockSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) vv = ((63 / (sz * 4)) + 1) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) ioc->NB_for_64_byte_frame = vv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) while ( sz )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) shiftFactor++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) sz = sz >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) ioc->NBShiftFactor = shiftFactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) ioc->name, vv, shiftFactor, r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) * Set values for this IOC's request & reply frame sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) * and request & reply queue depths...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) ioc->name, ioc->reply_sz, ioc->reply_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) ioc->name, ioc->req_sz, ioc->req_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) /* Get port facts! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) RequestFrameSize)/sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) return -66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) * GetPortFacts - Send PortFacts request to MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) * @portnum: Port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) PortFacts_t get_pfacts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) PortFactsReply_t *pfacts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) int req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) int reply_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) int max_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) /* IOC *must* NOT be in RESET state! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) if (ioc->last_state == MPI_IOC_STATE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) ioc->name, ioc->last_state );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) return -4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) pfacts = &ioc->pfacts[portnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) /* Destination (reply area)... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) reply_sz = sizeof(*pfacts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) memset(pfacts, 0, reply_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) /* Request area (get_pfacts on the stack right now!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) req_sz = sizeof(get_pfacts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) memset(&get_pfacts, 0, req_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) get_pfacts.PortNumber = portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) /* Assert: All other get_pfacts fields are zero! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) ioc->name, portnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) /* No non-zero fields in the get_pfacts request are greater than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) * 1 byte in size, so we can just fire it off as is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) if (ii != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) return ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) /* Did we get a valid reply? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) /* Now byte swap the necessary fields in the response. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) pfacts->MaxDevices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) * Place all the devices on channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) * (for debuging)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) if (mpt_channel_mapping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) ioc->devices_per_bus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) * SendIocInit - Send IOCInit request to MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) IOCInit_t ioc_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) MPIDefaultReply_t init_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) int cntdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) memset(&ioc_init, 0, sizeof(ioc_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) memset(&init_reply, 0, sizeof(init_reply));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) ioc_init.Function = MPI_FUNCTION_IOC_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) /* If we are in a recovery mode and we uploaded the FW image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) * then this pointer is not NULL. Skip the upload a second time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) * Set this flag if cached_fw set for either IOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) ioc->upload_fw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) ioc->upload_fw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) ioc->name, ioc->upload_fw, ioc->facts.Flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) ioc_init.MaxBuses = (U8)ioc->number_of_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) ioc->name, ioc->facts.MsgVersion));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) // set MsgVersion and HeaderVersion host driver was built with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) } else if(mpt_host_page_alloc(ioc, &ioc_init))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) return -99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) if (ioc->sg_addr_size == sizeof(u64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) /* Save the upper 32-bits of the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) * (reply) and sense buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) /* Force 32-bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) ioc_init.HostMfaHighAddr = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) ioc->facts.MaxDevices = ioc_init.MaxDevices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) ioc->facts.MaxBuses = ioc_init.MaxBuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) ioc->name, &ioc_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) if (r != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) /* No need to byte swap the multibyte fields in the reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) * since we don't even look at its contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) ioc->name, &ioc_init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) /* YIKES! SUPER IMPORTANT!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) * Poll IocState until _OPERATIONAL while IOC is doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) * LoopInit and TargetDiscovery!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) state = mpt_GetIocState(ioc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) if (!cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) ioc->name, (int)((count+5)/HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) return -9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) state = mpt_GetIocState(ioc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) ioc->name, count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) ioc->aen_event_read_flag=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) * SendPortEnable - Send PortEnable request to MPT adapter port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) * @portnum: Port number to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) * Send PortEnable to bring IOC to OPERATIONAL state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) PortEnable_t port_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) MPIDefaultReply_t reply_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) int req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) int reply_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) /* Destination... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) reply_sz = sizeof(MPIDefaultReply_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) memset(&reply_buf, 0, reply_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) req_sz = sizeof(PortEnable_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) memset(&port_enable, 0, req_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) port_enable.PortNumber = portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) /* port_enable.ChainOffset = 0; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) /* port_enable.MsgFlags = 0; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) /* port_enable.MsgContext = 0; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) ioc->name, portnum, &port_enable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) /* RAID FW may take a long time to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) if (ioc->ir_firmware || ioc->bus_type == SAS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) rc = mpt_handshake_req_reply_wait(ioc, req_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) 300 /*seconds*/, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) rc = mpt_handshake_req_reply_wait(ioc, req_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) 30 /*seconds*/, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) * mpt_alloc_fw_memory - allocate firmware memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) * @size: total FW bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) * If memory has already been allocated, the same (cached) value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) * is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) * Return 0 if successful, or non-zero for failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) if (ioc->cached_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) rc = 0; /* use already allocated memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) if (!ioc->cached_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) rc = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) ioc->alloc_total += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) * mpt_free_fw_memory - free firmware memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) * If alt_img is NULL, delete from ioc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) * Else, delete a secondary image in same format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) mpt_free_fw_memory(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) if (!ioc->cached_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) sz = ioc->facts.FWImageSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) ioc->alloc_total -= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) ioc->cached_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) * Returns 0 for success, >0 for handshake failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) * <0 for fw upload failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) * Remark: If bound IOC and a successful FWUpload was performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) * on the bound IOC, the second image is discarded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) * and memory is free'd. Both channels must upload to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) * IOC from running in degraded mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) u8 reply[sizeof(FWUploadReply_t)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) FWUpload_t *prequest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) FWUploadReply_t *preply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) FWUploadTCSGE_t *ptcsge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) u32 flagsLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) int ii, sz, reply_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) int cmdStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) int request_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) /* If the image size is 0, we are done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) if ((sz = ioc->facts.FWImageSize) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) kzalloc(ioc->req_sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) if (!prequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) "while allocating memory \n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) mpt_free_fw_memory(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) preply = (FWUploadReply_t *)&reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) reply_sz = sizeof(reply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) memset(preply, 0, reply_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) prequest->Function = MPI_FUNCTION_FW_UPLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) ptcsge->DetailsLength = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) ptcsge->ImageSize = cpu_to_le32(sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) ptcsge++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) ioc->SGE_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) ioc->facts.FWImageSize, request_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) "rc=%x \n", ioc->name, ii));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) cmdStatus = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) if (ii == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) /* Handshake transfer was complete and successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) * Check the Reply Frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) status = le16_to_cpu(preply->IOCStatus) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) MPI_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) if (status == MPI_IOCSTATUS_SUCCESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) ioc->facts.FWImageSize ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) le32_to_cpu(preply->ActualImageSize))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) cmdStatus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) ioc->name, cmdStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) if (cmdStatus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) "freeing image \n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) mpt_free_fw_memory(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) kfree(prequest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) return cmdStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) * mpt_downloadboot - DownloadBoot code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) * @pFwHeader: Pointer to firmware header info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) * FwDownloadBoot requires Programmed IO access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) * Returns 0 for success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) * -1 FW Image size is 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) * -2 No valid cached_fw Pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) * <0 for fw upload failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) MpiExtImageHeader_t *pExtImage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) u32 fwSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) u32 diag0val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) u32 *ptrFw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) u32 diagRwData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) u32 nextImage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) u32 load_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) u32 ioc_state=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) /* wait 1 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) mdelay (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) for (count = 0; count < 30; count ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) ioc->name, count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) /* wait .1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) msleep (100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) mdelay (100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) if ( count == 30 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) ioc->name, diag0val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) return -3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) /* Set the DiagRwEn and Disable ARM bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) fwSize = (pFwHeader->ImageSize + 3)/4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) ptrFw = (u32 *) pFwHeader;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) /* Write the LoadStartAddress to the DiagRw Address Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) * using Programmed IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) if (ioc->errata_flag_1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) pci_enable_io_access(ioc->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) ioc->name, pFwHeader->LoadStartAddress));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) ioc->name, fwSize*4, ptrFw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) while (fwSize--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) nextImage = pFwHeader->NextImageHeaderOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) while (nextImage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) load_addr = pExtImage->LoadStartAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) fwSize = (pExtImage->ImageSize + 3) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) ptrFw = (u32 *)pExtImage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) while (fwSize--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) nextImage = pExtImage->NextImageHeaderOffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) /* Write the IopResetVectorRegAddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) /* Write the IopResetVectorValue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) /* Clear the internal flash bad bit - autoincrementing register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) * so must do two writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) if (ioc->bus_type == SPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) * 1030 and 1035 H/W errata, workaround to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) * the ClearFlashBadSignatureBit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) diagRwData |= 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) MPI_DIAG_CLEAR_FLASH_BAD_SIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) /* wait 1 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) msleep (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) mdelay (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) if (ioc->errata_flag_1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) pci_disable_io_access(ioc->pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) ioc->name, diag0val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) ioc->name, diag0val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) /* Write 0xFF to reset the sequencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) if (ioc->bus_type == SAS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) ioc_state = mpt_GetIocState(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) if ( (GetIocFacts(ioc, sleepFlag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) ioc->name, ioc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) for (count=0; count<HZ*20; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) "downloadboot successful! (count=%d) IocState=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) ioc->name, count, ioc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) if (ioc->bus_type == SAS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) if ((SendIocInit(ioc, sleepFlag)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) "downloadboot: SendIocInit failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) "downloadboot: SendIocInit successful\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) msleep (10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) mdelay (10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) "downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) * KickStart - Perform hard reset of MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) * @force: Force hard reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) * This routine places MPT adapter in diagnostic mode via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) * WriteSequence register, and then performs a hard reset of adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) * via the Diagnostic register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) * or NO_SLEEP (interrupt thread, use mdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) * force - 1 if doorbell active, board fault state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) * board operational, IOC_RECOVERY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) * IOC_BRINGUP and there is an alt_ioc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) * 0 else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) * 1 - hard reset, READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) * 0 - no reset due to History bit, READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) * -1 - no reset due to History bit but not READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) * OR reset but failed to come READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) * -2 - no reset, could not enter DIAG mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) * -3 - reset but bad FW bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) int hard_reset_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) u32 ioc_state=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) int cnt,cntdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) if (ioc->bus_type == SPI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) /* Always issue a Msg Unit Reset first. This will clear some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) * SCSI bus hang conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) msleep (1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) mdelay (1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) if (hard_reset_done < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) return hard_reset_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) for (cnt=0; cnt<cntdn; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) ioc_state = mpt_GetIocState(ioc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) ioc->name, cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) return hard_reset_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) msleep (10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) mdelay (10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) ioc->name, mpt_GetIocState(ioc, 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) * mpt_diag_reset - Perform hard reset of the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) * @ignore: Set if to honor and clear to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) * the reset history bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) * else set to NO_SLEEP (use mdelay instead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) * This routine places the adapter in diagnostic mode via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) * WriteSequence register and then performs a hard reset of adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) * via the Diagnostic register. Adapter should be in ready state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) * upon successful completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) * Returns: 1 hard reset successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) * 0 no reset performed because reset history bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) * -2 enabling diagnostic mode failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) * -3 diagnostic reset failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) u32 diag0val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) int hard_reset_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) u32 diag1val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) MpiFwHeader_t *cached_fw; /* Pointer to FW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) /* Clear any existing interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) if (!ignore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) "address=%p\n", ioc->name, __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) &ioc->chip->Doorbell, &ioc->chip->Reset_1078));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) if (sleepFlag == CAN_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) * Call each currently registered protocol IOC reset handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) * with pre-reset indication.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) * NOTE: If we're doing _IOC_BRINGUP, there can be no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) * MptResetHandlers[] registered yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) if (MptResetHandlers[cb_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) (*(MptResetHandlers[cb_idx]))(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) MPT_IOC_PRE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) for (count = 0; count < 60; count ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) doorbell &= MPI_IOC_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) "looking for READY STATE: doorbell=%x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) " count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) ioc->name, doorbell, count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) if (doorbell == MPI_IOC_STATE_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) /* wait 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) if (sleepFlag == CAN_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) msleep(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) /* Use "Diagnostic reset" method! (only thing available!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) if (ioc->debug_level & MPT_DEBUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) ioc->name, diag0val, diag1val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) /* Do the reset if we are told to ignore the reset history
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) * or if the reset history is 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) while ((diag0val & MPI_DIAG_DRWE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) /* Write magic sequence to WriteSequence register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) * Loop until in diagnostic mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) /* wait 100 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) msleep (100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) mdelay (100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) if (count > 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) ioc->name, diag0val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) return -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) ioc->name, diag0val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) if (ioc->debug_level & MPT_DEBUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) ioc->name, diag0val, diag1val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) * Disable the ARM (Bug fix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) * Now hit the reset bit in the Diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) * (THE BIG HAMMER!) (Clears DRWE bit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) hard_reset_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) * Call each currently registered protocol IOC reset handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) * with pre-reset indication.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) * NOTE: If we're doing _IOC_BRINGUP, there can be no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) * MptResetHandlers[] registered yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) if (MptResetHandlers[cb_idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) mpt_signal_reset(cb_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) ioc, MPT_IOC_PRE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) if (ioc->alt_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) mpt_signal_reset(cb_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) ioc->alt_ioc, MPT_IOC_PRE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) if (ioc->cached_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) cached_fw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) if (cached_fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) /* If the DownloadBoot operation fails, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) * IOC will be left unusable. This is a fatal error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) * case. _diag_reset will return < 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) for (count = 0; count < 30; count ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) ioc->name, diag0val, count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) /* wait 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) msleep (1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) mdelay (1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) "firmware downloadboot failure (%d)!\n", ioc->name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) /* Wait for FW to reload and for board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) * to go to the READY state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) * Maximum wait is 60 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) * If fail, no error will check again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) * with calling program.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) for (count = 0; count < 60; count ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) doorbell &= MPI_IOC_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) "looking for READY STATE: doorbell=%x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) " count=%d\n", ioc->name, doorbell, count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) if (doorbell == MPI_IOC_STATE_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) /* wait 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) msleep (1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) mdelay (1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) if (doorbell != MPI_IOC_STATE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) printk(MYIOC_s_ERR_FMT "Failed to come READY "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) "after reset! IocState=%x", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) if (ioc->debug_level & MPT_DEBUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) ioc->name, diag0val, diag1val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) /* Clear RESET_HISTORY bit! Place board in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) * diagnostic mode to update the diag register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) while ((diag0val & MPI_DIAG_DRWE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) /* Write magic sequence to WriteSequence register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) * Loop until in diagnostic mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) /* wait 100 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) msleep (100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) mdelay (100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) if (count > 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) ioc->name, diag0val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) diag0val &= ~MPI_DIAG_RESET_HISTORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) if (diag0val & MPI_DIAG_RESET_HISTORY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) /* Disable Diagnostic Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) /* Check FW reload status flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) ioc->name, diag0val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) return -3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) if (ioc->debug_level & MPT_DEBUG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) ioc->name, diag0val, diag1val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) * Reset flag that says we've enabled event notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) ioc->facts.EventState = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) ioc->alt_ioc->facts.EventState = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) return hard_reset_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) * SendIocReset - Send IOCReset request to MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) * @reset_type: reset type, expected values are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) * Send IOCReset request to the MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) int cntdn, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) ioc->name, reset_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) /* FW ACK'd request, wait for READY state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) cntdn--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) if (!cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) if (sleepFlag != CAN_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) count *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) "Wait IOC_READY state (0x%x) timeout(%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) ioc->name, state, (int)((count+5)/HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) mdelay (1); /* 1 msec delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) /* TODO!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) * Cleanup all event stuff for this IOC; re-issue EventNotification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) * request if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) if (ioc->facts.Function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) ioc->facts.EventState = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) * initChainBuffers - Allocate memory for and initialize chain buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) * Allocates memory for and initializes chain buffers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) * chain buffer control arrays and spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) initChainBuffers(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) u8 *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) int sz, ii, num_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) int scale, num_sge, numSGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) /* ReqToChain size must equal the req_depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) * index = req_idx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) if (ioc->ReqToChain == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) sz = ioc->req_depth * sizeof(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) mem = kmalloc(sz, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) if (mem == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) ioc->ReqToChain = (int *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) ioc->name, mem, sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) mem = kmalloc(sz, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) if (mem == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) ioc->RequestNB = (int *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) ioc->name, mem, sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) for (ii = 0; ii < ioc->req_depth; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) /* ChainToChain size must equal the total number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) * of chain buffers to be allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) * index = chain_idx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) * Calculate the number of chain buffers needed(plus 1) per I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) * then multiply the maximum number of simultaneous cmds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) * num_sge = num sge in request frame + last chain buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) * scale = num sge per chain buffer if no chain element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) scale = ioc->req_sz / ioc->SGE_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) if (ioc->sg_addr_size == sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) if (ioc->sg_addr_size == sizeof(u64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) (ioc->req_sz - 60) / ioc->SGE_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) scale + (ioc->req_sz - 64) / ioc->SGE_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) ioc->name, num_sge, numSGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) if (ioc->bus_type == FC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) if (numSGE > MPT_SCSI_FC_SG_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) numSGE = MPT_SCSI_FC_SG_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) if (numSGE > MPT_SCSI_SG_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) numSGE = MPT_SCSI_SG_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) num_chain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) while (numSGE - num_sge > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) num_chain++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) num_sge += (scale - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) num_chain++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) ioc->name, numSGE, num_sge, num_chain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) if (ioc->bus_type == SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) num_chain *= MPT_SCSI_CAN_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) else if (ioc->bus_type == SAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) num_chain *= MPT_SAS_CAN_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) num_chain *= MPT_FC_CAN_QUEUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) ioc->num_chain = num_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) sz = num_chain * sizeof(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) if (ioc->ChainToChain == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) mem = kmalloc(sz, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) if (mem == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) ioc->ChainToChain = (int *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) ioc->name, mem, sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) mem = (u8 *) ioc->ChainToChain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) memset(mem, 0xFF, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) return num_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) * PrimeIocFifos - Initialize IOC request and reply FIFOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) * This routine allocates memory for the MPT reply and request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) * pools (if necessary), and primes the IOC reply FIFO with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) * reply frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) PrimeIocFifos(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) MPT_FRAME_HDR *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) dma_addr_t alloc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) u8 *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) int i, reply_sz, sz, total_size, num_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) u64 dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) dma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) /* Prime reply FIFO... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) if (ioc->reply_frames == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) if ( (num_chain = initChainBuffers(ioc)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) * 1078 errata workaround for the 36GB limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) ioc->dma_mask > DMA_BIT_MASK(35)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) && !pci_set_consistent_dma_mask(ioc->pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) dma_mask = DMA_BIT_MASK(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) "setting 35 bit addressing for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) "Request/Reply/Chain and Sense Buffers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) /*Reseting DMA mask to 64 bit*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) pci_set_dma_mask(ioc->pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) pci_set_consistent_dma_mask(ioc->pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) printk(MYIOC_s_ERR_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) "failed setting 35 bit addressing for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) "Request/Reply/Chain and Sense Buffers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) ioc->name, ioc->reply_sz, ioc->reply_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) ioc->name, reply_sz, reply_sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) sz = (ioc->req_sz * ioc->req_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) ioc->name, ioc->req_sz, ioc->req_depth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) ioc->name, sz, sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) total_size += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) sz = num_chain * ioc->req_sz; /* chain buffer pool size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) ioc->name, ioc->req_sz, num_chain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) ioc->name, sz, sz, num_chain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) total_size += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) mem = dma_alloc_coherent(&ioc->pcidev->dev, total_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) &alloc_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) if (mem == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) memset(mem, 0, total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) ioc->alloc_total += total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) ioc->alloc = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) ioc->alloc_dma = alloc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) ioc->alloc_sz = total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) ioc->reply_frames = (MPT_FRAME_HDR *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) alloc_dma += reply_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) mem += reply_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) /* Request FIFO - WE manage this! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) ioc->req_frames = (MPT_FRAME_HDR *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) ioc->req_frames_dma = alloc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) ioc->name, mem, (void *)(ulong)alloc_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) for (i = 0; i < ioc->req_depth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) alloc_dma += ioc->req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) mem += ioc->req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) ioc->ChainBuffer = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) ioc->ChainBufferDMA = alloc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) /* Initialize the free chain Q.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) INIT_LIST_HEAD(&ioc->FreeChainQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) /* Post the chain buffers to the FreeChainQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) mem = (u8 *)ioc->ChainBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) for (i=0; i < num_chain; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) mf = (MPT_FRAME_HDR *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) mem += ioc->req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) /* Initialize Request frames linked list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) alloc_dma = ioc->req_frames_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) mem = (u8 *) ioc->req_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) spin_lock_irqsave(&ioc->FreeQlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) INIT_LIST_HEAD(&ioc->FreeQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) for (i = 0; i < ioc->req_depth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) mf = (MPT_FRAME_HDR *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) /* Queue REQUESTs *internally*! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) mem += ioc->req_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) spin_unlock_irqrestore(&ioc->FreeQlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) ioc->sense_buf_pool = dma_alloc_coherent(&ioc->pcidev->dev, sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) &ioc->sense_buf_pool_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) if (ioc->sense_buf_pool == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) goto out_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) ioc->alloc_total += sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) /* Post Reply frames to FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) alloc_dma = ioc->alloc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) for (i = 0; i < ioc->reply_depth; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) /* Write each address to the IOC! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) alloc_dma += ioc->reply_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) ioc->dma_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) "restoring 64 bit addressing\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) out_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) if (ioc->alloc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) sz = ioc->alloc_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) ioc->alloc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) ioc->reply_frames = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) ioc->req_frames = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) ioc->alloc_total -= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) if (ioc->sense_buf_pool != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) ioc->sense_buf_pool_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) ioc->sense_buf_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) DMA_BIT_MASK(64)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) "restoring 64 bit addressing\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) * mpt_handshake_req_reply_wait - Send MPT request to and receive reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) * from IOC via doorbell handshake method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) * @reqBytes: Size of the request in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) * @req: Pointer to MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) * @replyBytes: Expected size of the reply in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) * @u16reply: Pointer to area where reply should be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) * @maxwait: Max wait time for a reply (in seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) * NOTES: It is the callers responsibility to byte-swap fields in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) * request which are greater than 1 byte in size. It is also the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) * callers responsibility to byte-swap response fields which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) * greater than 1 byte in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) MPIDefaultReply_t *mptReply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) int failcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) * Get ready to cache a handshake reply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) ioc->hs_reply_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) mptReply->MsgLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) * Make sure there are no doorbells (WRITE 0 to IntStatus reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) * then tell IOC that we want to handshake a request of N words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) * (WRITE u32val to Doorbell reg).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) CHIPREG_WRITE32(&ioc->chip->Doorbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) * Wait for IOC's doorbell handshake int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) failcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) /* Read doorbell and check for active bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) * Clear doorbell int (WRITE 0 to IntStatus reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) * then wait for IOC to ACKnowledge that it's ready for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) * our handshake request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) failcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) if (!failcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) u8 *req_as_bytes = (u8 *) req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) * Stuff request words via doorbell handshake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) * with ACK from IOC for each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) u32 word = ((req_as_bytes[(ii*4) + 0] << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) (req_as_bytes[(ii*4) + 1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) (req_as_bytes[(ii*4) + 2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) (req_as_bytes[(ii*4) + 3] << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) failcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) * Wait for completion of doorbell handshake reply from the IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) failcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) * Copy out the cached reply...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) u16reply[ii] = ioc->hs_reply[ii];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) return -99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) return -failcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) * @howlong: How long to wait (in seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) * This routine waits (up to ~2 seconds max) for IOC doorbell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) * bit in its IntStatus register being clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) * Returns a negative value on failure, else wait loop count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) int cntdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) u32 intstat=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) cntdn = 1000 * howlong;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) while (--cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) msleep (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) while (--cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) udelay (1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) if (cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) ioc->name, count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) ioc->name, count, intstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) * @howlong: How long to wait (in seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) * Returns a negative value on failure, else wait loop count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) int cntdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) u32 intstat=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) cntdn = 1000 * howlong;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) if (sleepFlag == CAN_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) while (--cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) while (--cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) udelay (1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) if (cntdn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) ioc->name, count, howlong));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) ioc->name, count, intstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) * WaitForDoorbellReply - Wait for and capture an IOC handshake reply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) * @howlong: How long to wait (in seconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) * This routine polls the IOC for a handshake reply, 16 bits at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) * Reply is cached to IOC private area large enough to hold a maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) * of 128 bytes of reply data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) * Returns a negative value on failure, else size of reply in WORDS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) int u16cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) int failcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) u16 *hs_reply = ioc->hs_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) u16 hword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) * Get first two u16's so we can look at IOC's intended reply MsgLength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) u16cnt=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) failcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) failcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) * If no error (and IOC said MsgLength is > 0), piece together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) * reply 16 bits at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) failcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) /* don't overflow our IOC hs_reply[] buffer! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) hs_reply[u16cnt] = hword;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) failcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) if (failcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) return -failcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) else if (u16cnt != (2 * mptReply->MsgLength)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) return -101;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) return -102;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) ioc->name, t, u16cnt/2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) return u16cnt/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) * GetLanConfigPages - Fetch LANConfig pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) * Return: 0 for success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) * -ENOMEM if no memory available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) * -EPERM if not allowed due to ISR context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) * -EAGAIN if no msg frames currently available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) * -EFAULT for non-successful reply or no reply (timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) GetLanConfigPages(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) ConfigPageHeader_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) LANPage0_t *ppage0_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) dma_addr_t page0_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) LANPage1_t *ppage1_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) dma_addr_t page1_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) int data_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) int copy_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) /* Get LAN Page 0 header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) hdr.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) hdr.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) hdr.PageNumber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) cfg.cfghdr.hdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) cfg.pageAddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) cfg.timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) if ((rc = mpt_config(ioc, &cfg)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) if (hdr.PageLength > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) data_sz = hdr.PageLength * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) ppage0_alloc = (LANPage0_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) if (ppage0_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) memset((u8 *)ppage0_alloc, 0, data_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) cfg.physAddr = page0_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) if ((rc = mpt_config(ioc, &cfg)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) /* save the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) /* FIXME!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) * Normalize endianness of structure data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) * by byte-swapping all > 1 byte fields!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) /* Get LAN Page 1 header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) hdr.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) hdr.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) hdr.PageNumber = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) cfg.cfghdr.hdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) cfg.pageAddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) if ((rc = mpt_config(ioc, &cfg)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) if (hdr.PageLength == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) data_sz = hdr.PageLength * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) ppage1_alloc = (LANPage1_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) if (ppage1_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) memset((u8 *)ppage1_alloc, 0, data_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) cfg.physAddr = page1_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) if ((rc = mpt_config(ioc, &cfg)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) /* save the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) /* FIXME!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) * Normalize endianness of structure data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) * by byte-swapping all > 1 byte fields!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) * @persist_opcode: see below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) * =============================== ======================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) * MPI_SAS_OP_CLEAR_NOT_PRESENT Free all persist TargetID mappings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) * devices not currently present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) * MPI_SAS_OP_CLEAR_ALL_PERSISTENT Clear al persist TargetID mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) * =============================== ======================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) * NOTE: Don't use not this function during interrupt time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) * Returns 0 for success, non-zero error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) SasIoUnitControlRequest_t *sasIoUnitCntrReq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) SasIoUnitControlReply_t *sasIoUnitCntrReply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) MPT_FRAME_HDR *mf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) MPIHeader_t *mpi_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) unsigned long timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) mutex_lock(&ioc->mptbase_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) /* init the internal cmd struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) /* insure garbage is not sent to fw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) switch(persist_opcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) case MPI_SAS_OP_CLEAR_NOT_PRESENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) printk(KERN_DEBUG "%s: persist_opcode=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) __func__, persist_opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) /* Get a MF for this command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) printk(KERN_DEBUG "%s: no msg frames!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) mpi_hdr = (MPIHeader_t *) mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) sasIoUnitCntrReq->Operation = persist_opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) mpt_put_msg_frame(mpt_base_index, ioc, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) ret = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) printk(KERN_DEBUG "%s: failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) if (!timeleft) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) "Issuing Reset from %s!!, doorbell=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) ioc->name, __func__, mpt_GetIocState(ioc, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) mpt_free_msg_frame(ioc, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) sasIoUnitCntrReply =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) __func__, sasIoUnitCntrReply->IOCStatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) sasIoUnitCntrReply->IOCLogInfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) printk(KERN_DEBUG "%s: failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) printk(KERN_DEBUG "%s: success\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) mutex_unlock(&ioc->mptbase_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) MpiEventDataRaid_t * pRaidEventData)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) int volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) int reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) int disk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) volume = pRaidEventData->VolumeID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) reason = pRaidEventData->ReasonCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) disk = pRaidEventData->PhysDiskNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) status = le32_to_cpu(pRaidEventData->SettingsStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) flags = (status >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) state = (status >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) ioc->name, disk, volume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) ioc->name, volume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) switch(reason) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) case MPI_EVENT_RAID_RC_VOLUME_CREATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) printk(MYIOC_s_INFO_FMT " volume has been created\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) case MPI_EVENT_RAID_RC_VOLUME_DELETED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) printk(MYIOC_s_INFO_FMT " volume has been deleted\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) printk(MYIOC_s_INFO_FMT " volume settings have been changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) ? "optimal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) ? "degraded"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) ? "failed"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) : "state unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) ? ", enabled" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) ? ", quiesced" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) ? ", resync in progress" : "" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) ioc->name, disk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) state == MPI_PHYSDISK0_STATUS_ONLINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) ? "online"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) : state == MPI_PHYSDISK0_STATUS_MISSING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) ? "missing"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) ? "not compatible"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) : state == MPI_PHYSDISK0_STATUS_FAILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) ? "failed"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) : state == MPI_PHYSDISK0_STATUS_INITIALIZING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) ? "initializing"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) ? "offline requested"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) ? "failed requested"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) ? "offline"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) : "state unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) ? ", out of sync" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) ? ", quiesced" : "" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) ioc->name, disk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) case MPI_EVENT_RAID_RC_SMART_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) ioc->name, disk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) * GetIoUnitPage2 - Retrieve BIOS version and boot order information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) * Returns: 0 for success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) * -ENOMEM if no memory available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) * -EPERM if not allowed due to ISR context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) * -EAGAIN if no msg frames currently available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) * -EFAULT for non-successful reply or no reply (timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) GetIoUnitPage2(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) ConfigPageHeader_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) IOUnitPage2_t *ppage_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) dma_addr_t page_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) int data_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) /* Get the page header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) hdr.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) hdr.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) hdr.PageNumber = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) cfg.cfghdr.hdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) cfg.pageAddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) cfg.timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) if ((rc = mpt_config(ioc, &cfg)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) if (hdr.PageLength == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) /* Read the config page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) data_sz = hdr.PageLength * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) ppage_alloc = (IOUnitPage2_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) if (ppage_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) memset((u8 *)ppage_alloc, 0, data_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) cfg.physAddr = page_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) /* If Good, save data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) if ((rc = mpt_config(ioc, &cfg)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) * @ioc: Pointer to a Adapter Strucutre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) * @portnum: IOC port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) * Return: -EFAULT if read of config page header fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) * or if no nvram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) * If read of SCSI Port Page 0 fails,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) * Adapter settings: async, narrow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) * Return 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) * If read of SCSI Port Page 2 fails,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) * Adapter settings valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) * Return 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) * Else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) * Both valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) * Return 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) * CHECK - what type of locking mechanisms should be used????
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) u8 *pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) dma_addr_t buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) ConfigPageHeader_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) int data, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) /* Allocate memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) if (!ioc->spi_data.nvram) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) u8 *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) mem = kmalloc(sz, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) if (mem == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) ioc->spi_data.nvram = (int *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) ioc->name, ioc->spi_data.nvram, sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) /* Invalidate NVRAM information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) /* Read SPP0 header, allocate memory, then read page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) header.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) header.PageNumber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) cfg.cfghdr.hdr = &header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) cfg.pageAddr = portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) cfg.timeout = 0; /* use default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) if (header.PageLength > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) if (pbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) cfg.physAddr = buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) if (mpt_config(ioc, &cfg) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) ioc->spi_data.maxBusWidth = MPT_NARROW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) ioc->spi_data.maxSyncOffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) ioc->spi_data.minSyncFactor = MPT_ASYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) rc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) "Unable to read PortPage0 minSyncFactor=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) ioc->name, ioc->spi_data.minSyncFactor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) /* Save the Port Page 0 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) "noQas due to Capabilities=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) ioc->name, pPP0->Capabilities));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) ioc->spi_data.minSyncFactor = (u8) (data >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) "PortPage0 minSyncFactor=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) ioc->name, ioc->spi_data.minSyncFactor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) ioc->spi_data.maxSyncOffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) ioc->spi_data.minSyncFactor = MPT_ASYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) /* Update the minSyncFactor based on bus type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) ioc->spi_data.minSyncFactor = MPT_ULTRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) "HVD or SE detected, minSyncFactor=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) ioc->name, ioc->spi_data.minSyncFactor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) if (pbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) /* SCSI Port Page 2 - Read the header then the page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) header.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) header.PageNumber = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) cfg.cfghdr.hdr = &header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) cfg.pageAddr = portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) if (header.PageLength > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) /* Allocate memory and read SCSI Port Page 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) if (pbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) cfg.physAddr = buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) if (mpt_config(ioc, &cfg) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) /* Nvram data is left with INVALID mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) rc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) /* This is an ATTO adapter, read Page2 accordingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) ATTODeviceInfo_t *pdevice = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) u16 ATTOFlags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) /* Save the Port Page 2 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) * (reformat into a 32bit quantity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) pdevice = &pPP2->DeviceSettings[ii];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) /* Translate ATTO device flags to LSI format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) if (ATTOFlags & ATTOFLAG_DISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) if (ATTOFlags & ATTOFLAG_ID_ENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) if (ATTOFlags & ATTOFLAG_LUN_ENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) if (ATTOFlags & ATTOFLAG_TAGGED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) data = (data << 16) | (pdevice->Period << 8) | 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) ioc->spi_data.nvram[ii] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) MpiDeviceInfo_t *pdevice = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) * Save "Set to Avoid SCSI Bus Resets" flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) ioc->spi_data.bus_reset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) (le32_to_cpu(pPP2->PortFlags) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) 0 : 1 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) /* Save the Port Page 2 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) * (reformat into a 32bit quantity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) ioc->spi_data.PortFlags = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) pdevice = &pPP2->DeviceSettings[ii];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) (pdevice->SyncFactor << 8) | pdevice->Timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) ioc->spi_data.nvram[ii] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) /* Update Adapter limits with those from NVRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) * Comment: Don't need to do this. Target performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) * parameters will never exceed the adapters limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) * mpt_readScsiDevicePageHeaders - save version and length of SDP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) * @ioc: Pointer to a Adapter Strucutre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) * @portnum: IOC port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) * Return: -EFAULT if read of config page header fails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) * or 0 if success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) ConfigPageHeader_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) /* Read the SCSI Device Page 1 header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) header.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) header.PageNumber = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) cfg.cfghdr.hdr = &header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) cfg.pageAddr = portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) cfg.timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) header.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) header.PageNumber = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) * mpt_inactive_raid_list_free - This clears this link list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) * @ioc : pointer to per adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) struct inactive_raid_component_info *component_info, *pNext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) if (list_empty(&ioc->raid_data.inactive_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) mutex_lock(&ioc->raid_data.inactive_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) list_for_each_entry_safe(component_info, pNext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) &ioc->raid_data.inactive_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) list_del(&component_info->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) kfree(component_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) mutex_unlock(&ioc->raid_data.inactive_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) * @ioc : pointer to per adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) * @channel : volume channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) * @id : volume target id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) ConfigPageHeader_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) pRaidVolumePage0_t buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) RaidPhysDiskPage0_t phys_disk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) struct inactive_raid_component_info *component_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) int handle_inactive_volumes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) memset(&cfg, 0 , sizeof(CONFIGPARMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) cfg.pageAddr = (channel << 8) + id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) cfg.cfghdr.hdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) if (!hdr.PageLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) &dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) if (!buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) cfg.physAddr = dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) if (!buffer->NumPhysDisks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) handle_inactive_volumes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) if (!handle_inactive_volumes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) mutex_lock(&ioc->raid_data.inactive_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) for (i = 0; i < buffer->NumPhysDisks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) if(mpt_raid_phys_disk_pg0(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) if ((component_info = kmalloc(sizeof (*component_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) GFP_KERNEL)) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) component_info->volumeID = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) component_info->volumeBus = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) component_info->d.PhysDiskID = phys_disk.PhysDiskID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) list_add_tail(&component_info->list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) &ioc->raid_data.inactive_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) mutex_unlock(&ioc->raid_data.inactive_list_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) if (buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) * mpt_raid_phys_disk_pg0 - returns phys disk page zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) * @ioc: Pointer to a Adapter Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) * @phys_disk_num: io unit unique phys disk num generated by the ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) * @phys_disk: requested payload data returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) * 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) * -EFAULT if read of config page header fails or data pointer not NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) * -ENOMEM if pci_alloc failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) RaidPhysDiskPage0_t *phys_disk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) ConfigPageHeader_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) pRaidPhysDiskPage0_t buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) memset(&cfg, 0 , sizeof(CONFIGPARMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) cfg.cfghdr.hdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) if (mpt_config(ioc, &cfg) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) if (!hdr.PageLength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) &dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) if (!buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) cfg.physAddr = dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) cfg.pageAddr = phys_disk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) if (mpt_config(ioc, &cfg) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) memcpy(phys_disk, buffer, sizeof(*buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) if (buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) * @ioc: Pointer to a Adapter Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) * @phys_disk_num: io unit unique phys disk num generated by the ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) * returns number paths
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) ConfigPageHeader_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) pRaidPhysDiskPage1_t buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) memset(&cfg, 0 , sizeof(CONFIGPARMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) hdr.PageNumber = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) cfg.cfghdr.hdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) if (mpt_config(ioc, &cfg) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) if (!hdr.PageLength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) &dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) if (!buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) cfg.physAddr = dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) cfg.pageAddr = phys_disk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) if (mpt_config(ioc, &cfg) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) rc = buffer->NumPhysDiskPaths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) if (buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) * mpt_raid_phys_disk_pg1 - returns phys disk page 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) * @ioc: Pointer to a Adapter Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) * @phys_disk_num: io unit unique phys disk num generated by the ioc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) * @phys_disk: requested payload data returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) * 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) * -EFAULT if read of config page header fails or data pointer not NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) * -ENOMEM if pci_alloc failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) RaidPhysDiskPage1_t *phys_disk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) ConfigPageHeader_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) dma_addr_t dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) pRaidPhysDiskPage1_t buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) __le64 sas_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) memset(&cfg, 0 , sizeof(CONFIGPARMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) hdr.PageNumber = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) cfg.cfghdr.hdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) if (mpt_config(ioc, &cfg) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) if (!hdr.PageLength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) &dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) if (!buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) cfg.physAddr = dma_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) cfg.pageAddr = phys_disk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) if (mpt_config(ioc, &cfg) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) rc = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) phys_disk->PhysDiskNum = phys_disk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) phys_disk->Path[i].OwnerIdentifier =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) buffer->Path[i].OwnerIdentifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) sas_address = le64_to_cpu(sas_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) memcpy(&sas_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) &buffer->Path[i].OwnerWWID, sizeof(__le64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) sas_address = le64_to_cpu(sas_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) memcpy(&phys_disk->Path[i].OwnerWWID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) &sas_address, sizeof(__le64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) if (buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) EXPORT_SYMBOL(mpt_raid_phys_disk_pg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) * @ioc: Pointer to a Adapter Strucutre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) * 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) * -EFAULT if read of config page header fails or data pointer not NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) * -ENOMEM if pci_alloc failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) mpt_findImVolumes(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) IOCPage2_t *pIoc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) u8 *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) dma_addr_t ioc2_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) ConfigPageHeader_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) int iocpage2sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) if (!ioc->ir_firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) /* Free the old page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) kfree(ioc->raid_data.pIocPg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) ioc->raid_data.pIocPg2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) mpt_inactive_raid_list_free(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) /* Read IOCP2 header then the page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) header.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) header.PageNumber = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) header.PageType = MPI_CONFIG_PAGETYPE_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) cfg.cfghdr.hdr = &header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) cfg.pageAddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) cfg.timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) if (header.PageLength == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) iocpage2sz = header.PageLength * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) if (!pIoc2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) cfg.physAddr = ioc2_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) mem = kmemdup(pIoc2, iocpage2sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) mpt_read_ioc_pg_3(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) mpt_inactive_raid_volumes(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) pIoc2->RaidVolume[i].VolumeBus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) pIoc2->RaidVolume[i].VolumeID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) IOCPage3_t *pIoc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) u8 *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) ConfigPageHeader_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) dma_addr_t ioc3_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) int iocpage3sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) /* Free the old page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) kfree(ioc->raid_data.pIocPg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) ioc->raid_data.pIocPg3 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) /* There is at least one physical disk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) * Read and save IOC Page 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) header.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) header.PageNumber = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) header.PageType = MPI_CONFIG_PAGETYPE_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) cfg.cfghdr.hdr = &header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) cfg.pageAddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) cfg.timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) if (header.PageLength == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) /* Read Header good, alloc memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) iocpage3sz = header.PageLength * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) if (!pIoc3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) /* Read the Page and save the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) * into malloc'd memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) cfg.physAddr = ioc3_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) if (mpt_config(ioc, &cfg) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) mem = kmalloc(iocpage3sz, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) if (mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) memcpy(mem, (u8 *)pIoc3, iocpage3sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) IOCPage4_t *pIoc4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) ConfigPageHeader_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) dma_addr_t ioc4_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) int iocpage4sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) /* Read and save IOC Page 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) header.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) header.PageNumber = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) header.PageType = MPI_CONFIG_PAGETYPE_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) cfg.cfghdr.hdr = &header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) cfg.pageAddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) cfg.timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) if (header.PageLength == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) if (!pIoc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) ioc->alloc_total += iocpage4sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) ioc4_dma = ioc->spi_data.IocPg4_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) iocpage4sz = ioc->spi_data.IocPg4Sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) /* Read the Page into dma memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) cfg.physAddr = ioc4_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) if (mpt_config(ioc, &cfg) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) ioc->spi_data.IocPg4_dma = ioc4_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) ioc->spi_data.IocPg4Sz = iocpage4sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) ioc->spi_data.pIocPg4 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) ioc->alloc_total -= iocpage4sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) IOCPage1_t *pIoc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) ConfigPageHeader_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) dma_addr_t ioc1_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) int iocpage1sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) /* Check the Coalescing Timeout in IOC Page 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) header.PageVersion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) header.PageNumber = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) header.PageType = MPI_CONFIG_PAGETYPE_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) cfg.cfghdr.hdr = &header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) cfg.pageAddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) cfg.dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) cfg.timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) if (header.PageLength == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) /* Read Header good, alloc memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) iocpage1sz = header.PageLength * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) if (!pIoc1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) /* Read the Page and check coalescing timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) cfg.physAddr = ioc1_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) if (mpt_config(ioc, &cfg) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) ioc->name, tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) if (tmp > MPT_COALESCING_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) /* Write NVRAM and current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) cfg.dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) if (mpt_config(ioc, &cfg) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) ioc->name, MPT_COALESCING_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) if (mpt_config(ioc, &cfg) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) "Reset NVRAM Coalescing Timeout to = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) ioc->name, MPT_COALESCING_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) "Reset NVRAM Coalescing Timeout Failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) dprintk(ioc, printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) "Reset of Current Coalescing Timeout Failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) CONFIGPARMS cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) ConfigPageHeader_t hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) dma_addr_t buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) ManufacturingPage0_t *pbuf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) memset(&cfg, 0 , sizeof(CONFIGPARMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) cfg.cfghdr.hdr = &hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) cfg.physAddr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) cfg.timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) if (!cfg.cfghdr.hdr->PageLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) if (!pbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) cfg.physAddr = buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) if (mpt_config(ioc, &cfg) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) if (pbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) * SendEventNotification - Send EventNotification (on or off) request to adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) * @EvSwitch: Event switch flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) * @sleepFlag: Specifies whether the process can sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) EventNotification_t evn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) MPIDefaultReply_t reply_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) memset(&evn, 0, sizeof(EventNotification_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) memset(&reply_buf, 0, sizeof(MPIDefaultReply_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) evn.Switch = EvSwitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) evn.MsgContext = cpu_to_le32(mpt_base_index << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) "Sending EventNotification (%d) request %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) ioc->name, EvSwitch, &evn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) * SendEventAck - Send EventAck request to MPT adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) * @evnp: Pointer to original EventNotification request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) EventAck_t *pAck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) ioc->name, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) pAck->Function = MPI_FUNCTION_EVENT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) pAck->ChainOffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) pAck->Reserved[0] = pAck->Reserved[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) pAck->MsgFlags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) pAck->Event = evnp->Event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) pAck->EventContext = evnp->EventContext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) * mpt_config - Generic function to issue config message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) * @ioc: Pointer to an adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) * @pCfg: Pointer to a configuration structure. Struct contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) * action, page address, direction, physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) * and pointer to a configuration page header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) * Page header is updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) * Returns 0 for success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) * -EPERM if not allowed due to ISR context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) * -EAGAIN if no msg frames currently available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) * -EFAULT for non-successful reply or no reply (timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) Config_t *pReq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) ConfigReply_t *pReply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) ConfigExtendedPageHeader_t *pExtHdr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) MPT_FRAME_HDR *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) int flagsLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) u8 page_type = 0, extend_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) unsigned long timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) int in_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) u8 issue_hard_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) u8 retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) /* Prevent calling wait_event() (below), if caller happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) * to be in ISR context, because that is fatal!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) in_isr = in_interrupt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) if (in_isr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) dcprintk(ioc, printk(MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) /* don't send a config page during diag reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) if (ioc->ioc_reset_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) "%s: busy with host reset\n", ioc->name, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) /* don't send if no chance of success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) if (!ioc->active ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) "%s: ioc not operational, %d, %xh\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) ioc->name, __func__, ioc->active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) mpt_GetIocState(ioc, 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) retry_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) mutex_lock(&ioc->mptbase_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) /* init the internal cmd struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) /* Get and Populate a free Frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) dcprintk(ioc, printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) "mpt_config: no msg frames!\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) pReq = (Config_t *)mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) pReq->Action = pCfg->action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) pReq->Reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) pReq->ChainOffset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) pReq->Function = MPI_FUNCTION_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) /* Assume page type is not extended and clear "reserved" fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) pReq->ExtPageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) pReq->ExtPageType = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) pReq->MsgFlags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) for (ii=0; ii < 8; ii++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) pReq->Reserved2[ii] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) pReq->ExtPageType = pExtHdr->ExtPageType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) /* Page Length must be treated as a reserved field for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) * extended header.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) pReq->Header.PageLength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) /* Add a SGE to the config request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) if (pCfg->dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) MPI_CONFIG_PAGETYPE_EXTENDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) flagsLength |= pExtHdr->ExtPageLength * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) page_type = pReq->ExtPageType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) extend_page = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) page_type = pReq->Header.PageType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) extend_page = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) "Sending Config request type 0x%x, page 0x%x and action %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) ioc->name, page_type, pReq->Header.PageNumber, pReq->Action));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) mpt_put_msg_frame(mpt_base_index, ioc, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) ret = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) "Failed Sending Config request type 0x%x, page 0x%x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) " action %d, status %xh, time left %ld\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) ioc->name, page_type, pReq->Header.PageNumber,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) pReq->Action, ioc->mptbase_cmds.status, timeleft));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) if (!timeleft) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) if (ioc->ioc_reset_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) spin_unlock_irqrestore(&ioc->taskmgmt_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) printk(MYIOC_s_INFO_FMT "%s: host reset in"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) " progress mpt_config timed out.!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) __func__, ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) mutex_unlock(&ioc->mptbase_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) issue_hard_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) if (ret == MPI_IOCSTATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) if (extend_page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) pCfg->cfghdr.ehdr->ExtPageLength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) le16_to_cpu(pReply->ExtPageLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) pCfg->cfghdr.ehdr->ExtPageType =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) pReply->ExtPageType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) if (retry_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) printk(MYIOC_s_INFO_FMT "Retry completed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) "ret=0x%x timeleft=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) ioc->name, ret, timeleft);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) ret, le32_to_cpu(pReply->IOCLogInfo)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) mutex_unlock(&ioc->mptbase_cmds.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) if (issue_hard_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) issue_hard_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) printk(MYIOC_s_WARN_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) "Issuing Reset from %s!!, doorbell=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) ioc->name, __func__, mpt_GetIocState(ioc, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) if (retry_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) retry_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) mpt_HardResetHandler(ioc, CAN_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) mpt_free_msg_frame(ioc, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) /* attempt one retry for a timed out command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) if (retry_count < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) "Attempting Retry Config request"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) " type 0x%x, page 0x%x,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) " action %d\n", ioc->name, page_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) pCfg->cfghdr.hdr->PageNumber, pCfg->action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) retry_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) goto retry_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) * mpt_ioc_reset - Base cleanup for hard reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) * @ioc: Pointer to the adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) * @reset_phase: Indicates pre- or post-reset functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) * Remark: Frees resources with internally generated commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) switch (reset_phase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) case MPT_IOC_SETUP_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) ioc->taskmgmt_quiesce_io = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) case MPT_IOC_PRE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) case MPT_IOC_POST_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) /* wake up mptbase_cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) ioc->mptbase_cmds.status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) MPT_MGMT_STATUS_DID_IOCRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) complete(&ioc->mptbase_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) /* wake up taskmgmt_cmds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) ioc->taskmgmt_cmds.status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) MPT_MGMT_STATUS_DID_IOCRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) complete(&ioc->taskmgmt_cmds.done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) return 1; /* currently means nothing really */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) #ifdef CONFIG_PROC_FS /* { */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) procmpt_create(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) if (mpt_proc_root_dir == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) return -ENOTDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) proc_create_single("summary", S_IRUGO, mpt_proc_root_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) mpt_summary_proc_show);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) proc_create_single("version", S_IRUGO, mpt_proc_root_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) mpt_version_proc_show);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) procmpt_destroy(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) remove_proc_entry("version", mpt_proc_root_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) remove_proc_entry("summary", mpt_proc_root_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) static int mpt_summary_proc_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) MPT_ADAPTER *ioc = m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) if (ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) seq_mpt_print_ioc_summary(ioc, m, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648) list_for_each_entry(ioc, &ioc_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) seq_mpt_print_ioc_summary(ioc, m, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) static int mpt_version_proc_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) int scsi, fc, sas, lan, ctl, targ, dmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) char *drvname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) seq_printf(m, " Fusion MPT base driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) scsi = fc = sas = lan = ctl = targ = dmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) drvname = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) if (MptCallbacks[cb_idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) switch (MptDriverClass[cb_idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) case MPTSPI_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) if (!scsi++) drvname = "SPI host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) case MPTFC_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) if (!fc++) drvname = "FC host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) case MPTSAS_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) if (!sas++) drvname = "SAS host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) case MPTLAN_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) if (!lan++) drvname = "LAN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) case MPTSTM_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) if (!targ++) drvname = "SCSI target";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) case MPTCTL_DRIVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) if (!ctl++) drvname = "ioctl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) if (drvname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) seq_printf(m, " Fusion MPT %s driver\n", drvname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) static int mpt_iocinfo_proc_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) MPT_ADAPTER *ioc = m->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) char expVer[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) int sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) int p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) mpt_get_fw_exp_ver(expVer, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) seq_printf(m, "%s:", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) seq_printf(m, " (f/w download boot flag set)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) // if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) // seq_printf(m, " CONFIG_CHECKSUM_FAIL!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) seq_printf(m, "\n ProductID = 0x%04x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) ioc->facts.ProductID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) ioc->prod_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) if (ioc->facts.FWImageSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) ioc->facts.CurrentHostMfaHighAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) ioc->facts.CurrentSenseBufferHighAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) * Rounding UP to nearest 4-kB boundary here...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) sz = (ioc->req_sz * ioc->req_depth) + 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) 4*ioc->facts.RequestFrameSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) ioc->facts.GlobalCredits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) sz = (ioc->reply_sz * ioc->reply_depth) + 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747) seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750) ioc->facts.CurReplyFrameSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) ioc->facts.ReplyQueueDepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) seq_printf(m, " MaxDevices = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) /* per-port info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) for (p=0; p < ioc->facts.NumberOfPorts; p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) seq_printf(m, " PortNumber = %d (of %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) p+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) ioc->facts.NumberOfPorts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) if (ioc->bus_type == FC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) seq_printf(m, " LanAddr = %pMR\n", a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) seq_printf(m, " WWN = %08X%08X:%08X%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) ioc->fc_port_page0[p].WWNN.High,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) ioc->fc_port_page0[p].WWNN.Low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) ioc->fc_port_page0[p].WWPN.High,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) ioc->fc_port_page0[p].WWPN.Low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) #endif /* CONFIG_PROC_FS } */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) buf[0] ='\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) sprintf(buf, " (Exp %02d%02d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789) /* insider hack! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) strcat(buf, " [MDBG]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) * @buffer: Pointer to buffer where IOC summary info should be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) * @size: Pointer to number of bytes we wrote (set by this routine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) * @len: Offset at which to start writing in buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) * @showlan: Display LAN stuff?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) * This routine writes (english readable) ASCII text, which represents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) * a summary of IOC information, to a buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) char expVer[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) int y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) mpt_get_fw_exp_ver(expVer, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) * Shorter summary of attached ioc's...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) ioc->prod_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) ioc->facts.FWVersion.Word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) expVer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) ioc->facts.NumberOfPorts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) ioc->req_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) y += sprintf(buffer+len+y, ", LanAddr=%pMR", a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) if (!ioc->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) y += sprintf(buffer+len+y, " (disabled)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837) y += sprintf(buffer+len+y, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) *size = y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) char expVer[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) mpt_get_fw_exp_ver(expVer, ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) * Shorter summary of attached ioc's...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) ioc->prod_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) ioc->facts.FWVersion.Word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) expVer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) ioc->facts.NumberOfPorts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) ioc->req_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) seq_printf(m, ", LanAddr=%pMR", a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) seq_printf(m, ", IRQ=%d", ioc->pci_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) if (!ioc->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) seq_printf(m, " (disabled)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) * Returns 0 for SUCCESS or -1 if FAILED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) * If -1 is return, then it was not possible to set the flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) retval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896) ioc->taskmgmt_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) ioc->taskmgmt_quiesce_io = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) if (ioc->alt_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899) ioc->alt_ioc->taskmgmt_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) ioc->alt_ioc->taskmgmt_quiesce_io = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914) mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919) ioc->taskmgmt_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) ioc->taskmgmt_quiesce_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) if (ioc->alt_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) ioc->alt_ioc->taskmgmt_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923) ioc->alt_ioc->taskmgmt_quiesce_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) * mpt_halt_firmware - Halts the firmware if it is operational and panic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932) * the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) mpt_halt_firmware(MPT_ADAPTER *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939) u32 ioc_raw_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) ioc_raw_state = mpt_GetIocState(ioc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943) if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) panic("%s: IOC Fault (%04xh)!!!\n", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947) ioc_raw_state & MPI_DOORBELL_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) panic("%s: Firmware is halted due to command timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951) ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) EXPORT_SYMBOL(mpt_halt_firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) * mpt_SoftResetHandler - Issues a less expensive reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959) * @sleepFlag: Indicates if sleep or schedule must be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) * Returns 0 for SUCCESS or -1 if FAILED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) * Message Unit Reset - instructs the IOC to reset the Reply Post and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) * All posted buffers are freed, and event notification is turned off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966) * IOC doesn't reply to any outstanding request. This will transfer IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) * to READY state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970) mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) u32 ioc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) unsigned long time_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980) ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982) ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) if (mpt_fwfault_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985) mpt_halt_firmware(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987) if (ioc_state == MPI_IOC_STATE_FAULT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988) ioc_state == MPI_IOC_STATE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990) "skipping, either in FAULT or RESET state!\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994) if (ioc->bus_type == FC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) "skipping, because the bus type is FC!\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001) if (ioc->ioc_reset_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005) ioc->ioc_reset_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008) rc = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) if (MptResetHandlers[cb_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012) mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016) if (ioc->taskmgmt_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) ioc->ioc_reset_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) /* Disable reply interrupts (also blocks FreeQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023) CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) ioc->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) time_count = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027) rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030) if (MptResetHandlers[cb_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) if (ioc_state != MPI_IOC_STATE_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041) for (ii = 0; ii < 5; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) /* Get IOC facts! Allow 5 retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) rc = GetIocFacts(ioc, sleepFlag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) MPT_HOSTEVENT_IOC_RECOVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) if (rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047) if (sleepFlag == CAN_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052) if (ii == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) rc = PrimeIocFifos(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) rc = SendIocInit(ioc, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) rc = SendEventNotification(ioc, 1, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) if (rc != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) if (ioc->hard_resets < -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068) ioc->hard_resets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) * At this point, we know soft reset succeeded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) ioc->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) ioc->ioc_reset_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080) ioc->taskmgmt_quiesce_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) ioc->taskmgmt_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) if (ioc->active) { /* otherwise, hard reset coming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) if (MptResetHandlers[cb_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) mpt_signal_reset(cb_idx, ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) MPT_IOC_POST_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) "SoftResetHandler: completed (%d seconds): %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) ioc->name, jiffies_to_msecs(jiffies - time_count)/1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095) ((rc == 0) ? "SUCCESS" : "FAILED")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101) * mpt_Soft_Hard_ResetHandler - Try less expensive reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) * @sleepFlag: Indicates if sleep or schedule must be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) * Returns 0 for SUCCESS or -1 if FAILED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) * Try for softreset first, only if it fails go for expensive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) * HardReset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) ret = mpt_SoftResetHandler(ioc, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) ret = mpt_HardResetHandler(ioc, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) * Reset Handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127) * mpt_HardResetHandler - Generic reset handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129) * @sleepFlag: Indicates if sleep or schedule must be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131) * Issues SCSI Task Management call based on input arg values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) * If TaskMgmt fails, returns associated SCSI request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134) * Remark: _HardResetHandler can be invoked from an interrupt thread (timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) * or a non-interrupt thread. In the former, must not call schedule().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) * Note: A return of -1 is a FATAL error case, as it means a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138) * FW reload/initialization failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140) * Returns 0 for SUCCESS or -1 if FAILED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148) unsigned long time_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) #ifdef MFCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153) printk("MF count 0x%x !\n", ioc->mfcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) if (mpt_fwfault_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) mpt_halt_firmware(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) /* Reset the adapter. Prevent more than 1 call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) * mpt_do_ioc_recovery at any instant in time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162) if (ioc->ioc_reset_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) ioc->wait_on_reset_completion = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) ssleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167) } while (ioc->ioc_reset_in_progress == 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) ioc->wait_on_reset_completion = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169) return ioc->reset_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) if (ioc->wait_on_reset_completion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) time_count = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) ioc->ioc_reset_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) ioc->alt_ioc->ioc_reset_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) /* The SCSI driver needs to adjust timeouts on all current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) * commands prior to the diagnostic reset being issued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) * Prevents timeouts occurring during a diagnostic reset...very bad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) * For all other protocol drivers, this is a no-op.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189) if (MptResetHandlers[cb_idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192) mpt_signal_reset(cb_idx, ioc->alt_ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) MPT_IOC_SETUP_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) time_count = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200) printk(KERN_WARNING MYNAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) rc, ioc->name, mpt_GetIocState(ioc, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) if (ioc->hard_resets < -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205) ioc->hard_resets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) ioc->ioc_reset_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210) ioc->taskmgmt_quiesce_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) ioc->taskmgmt_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) ioc->reset_status = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) if (ioc->alt_ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214) ioc->alt_ioc->ioc_reset_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215) ioc->alt_ioc->taskmgmt_quiesce_io = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) ioc->alt_ioc->taskmgmt_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) if (MptResetHandlers[cb_idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222) mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) if (ioc->alt_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) mpt_signal_reset(cb_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) ioc->alt_ioc, MPT_IOC_POST_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229) dtmprintk(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) "HardResetHandler: completed (%d seconds): %s\n", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) "SUCCESS" : "FAILED")));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) #ifdef CONFIG_FUSION_LOGGING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242) char *ds = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) u32 evData0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245) u8 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) char *evStr = ioc->evStr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) event = le32_to_cpu(pEventReply->Event) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249) evData0 = le32_to_cpu(pEventReply->Data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) switch(event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) case MPI_EVENT_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) ds = "None";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255) case MPI_EVENT_LOG_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) ds = "Log Data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) case MPI_EVENT_STATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259) ds = "State Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) case MPI_EVENT_UNIT_ATTENTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262) ds = "Unit Attention";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) case MPI_EVENT_IOC_BUS_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) ds = "IOC Bus Reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267) case MPI_EVENT_EXT_BUS_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) ds = "External Bus Reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) case MPI_EVENT_RESCAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271) ds = "Bus Rescan Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273) case MPI_EVENT_LINK_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) ds = "Link Status(FAILURE) Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) ds = "Link Status(ACTIVE) Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) case MPI_EVENT_LOOP_STATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280) if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) ds = "Loop State(LIP) Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283) ds = "Loop State(LPE) Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) ds = "Loop State(LPB) Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) case MPI_EVENT_LOGOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) ds = "Logout";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) case MPI_EVENT_EVENT_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) if (evData0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) ds = "Events ON";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) ds = "Events OFF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) case MPI_EVENT_INTEGRATED_RAID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) u8 ReasonCode = (u8)(evData0 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299) switch (ReasonCode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) case MPI_EVENT_RAID_RC_VOLUME_CREATED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) ds = "Integrated Raid: Volume Created";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) case MPI_EVENT_RAID_RC_VOLUME_DELETED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) ds = "Integrated Raid: Volume Deleted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307) ds = "Integrated Raid: Volume Settings Changed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) ds = "Integrated Raid: Volume Status Changed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312) case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) ds = "Integrated Raid: Volume Physdisk Changed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) ds = "Integrated Raid: Physdisk Created";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) ds = "Integrated Raid: Physdisk Deleted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322) ds = "Integrated Raid: Physdisk Settings Changed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324) case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) ds = "Integrated Raid: Physdisk Status Changed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) ds = "Integrated Raid: Domain Validation Needed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) case MPI_EVENT_RAID_RC_SMART_DATA :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) ds = "Integrated Raid; Smart Data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334) ds = "Integrated Raid: Replace Action Started";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337) ds = "Integrated Raid";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342) case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) ds = "SCSI Device Status Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) u8 id = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) u8 channel = (u8)(evData0 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349) u8 ReasonCode = (u8)(evData0 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) switch (ReasonCode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351) case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) "SAS Device Status Change: Added: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) "id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) "SAS Device Status Change: Deleted: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359) "id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) "SAS Device Status Change: SMART Data: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) "id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) "SAS Device Status Change: No Persistency: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) "id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371) case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) "SAS Device Status Change: Unsupported Device "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374) "Discovered : id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378) "SAS Device Status Change: Internal Device "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) "Reset : id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) "SAS Device Status Change: Internal Task "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) "Abort : id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) "SAS Device Status Change: Internal Abort "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389) "Task Set : id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) "SAS Device Status Change: Internal Clear "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394) "Task Set : id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) "SAS Device Status Change: Internal Query "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399) "Task : id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403) "SAS Device Status Change: Unknown: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404) "id=%d channel=%d", id, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) ds = "Bus Timer Expired";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) case MPI_EVENT_QUEUE_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) u16 curr_depth = (u16)(evData0 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) u8 channel = (u8)(evData0 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416) u8 id = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) "Queue Full: channel=%d id=%d depth=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) channel, id, curr_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) case MPI_EVENT_SAS_SES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) ds = "SAS SES Event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426) case MPI_EVENT_PERSISTENT_TABLE_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) ds = "Persistent Table Full";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) case MPI_EVENT_SAS_PHY_LINK_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) u8 LinkRates = (u8)(evData0 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) u8 PhyNumber = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) switch (LinkRates) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) "SAS PHY Link Status: Phy=%d:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) " Rate Unknown",PhyNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441) case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) "SAS PHY Link Status: Phy=%d:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) " Phy Disabled",PhyNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) "SAS PHY Link Status: Phy=%d:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) " Failed Speed Nego",PhyNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451) case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453) "SAS PHY Link Status: Phy=%d:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) " Sata OOB Completed",PhyNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) "SAS PHY Link Status: Phy=%d:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) " Rate 1.5 Gbps",PhyNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) "SAS PHY Link Status: Phy=%d:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) " Rate 3.0 Gbps", PhyNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) case MPI_EVENT_SAS_PLS_LR_RATE_6_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) "SAS PHY Link Status: Phy=%d:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469) " Rate 6.0 Gbps", PhyNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473) "SAS PHY Link Status: Phy=%d", PhyNumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) case MPI_EVENT_SAS_DISCOVERY_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479) ds = "SAS Discovery Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) case MPI_EVENT_IR_RESYNC_UPDATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483) u8 resync_complete = (u8)(evData0 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) "IR Resync Update: Complete = %d:",resync_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488) case MPI_EVENT_IR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490) u8 id = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491) u8 channel = (u8)(evData0 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) u8 phys_num = (u8)(evData0 >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493) u8 ReasonCode = (u8)(evData0 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495) switch (ReasonCode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498) "IR2: LD State Changed: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502) case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504) "IR2: PD State Changed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508) case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510) "IR2: Bad Block Table Full: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514) case MPI_EVENT_IR2_RC_PD_INSERTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516) "IR2: PD Inserted: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) case MPI_EVENT_IR2_RC_PD_REMOVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) "IR2: PD Removed: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526) case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528) "IR2: Foreign CFG Detected: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) "IR2: Rebuild Medium Error: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538) case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) "IR2: Dual Port Added: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) "IR2: Dual Port Removed: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) "id=%d channel=%d phys_num=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548) id, channel, phys_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) ds = "IR2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) case MPI_EVENT_SAS_DISCOVERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) if (evData0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) ds = "SAS Discovery: Start";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561) ds = "SAS Discovery: Stop";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564) case MPI_EVENT_LOG_ENTRY_ADDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565) ds = "SAS Log Entry Added";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568) case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) u8 phy_num = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) u8 port_num = (u8)(evData0 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) u8 port_width = (u8)(evData0 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573) u8 primitive = (u8)(evData0 >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) "SAS Broadcast Primitive: phy=%d port=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576) "width=%d primitive=0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577) phy_num, port_num, port_width, primitive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581) case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583) u8 reason = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) switch (reason) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586) case MPI_EVENT_SAS_INIT_RC_ADDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) ds = "SAS Initiator Status Change: Added";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589) case MPI_EVENT_SAS_INIT_RC_REMOVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590) ds = "SAS Initiator Status Change: Deleted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) ds = "SAS Initiator Status Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) u8 max_init = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) u8 current_init = (u8)(evData0 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605) "SAS Initiator Device Table Overflow: max initiators=%02d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606) "current initiators=%02d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607) max_init, current_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610) case MPI_EVENT_SAS_SMP_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612) u8 status = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) u8 port_num = (u8)(evData0 >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614) u8 result = (u8)(evData0 >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) "SAS SMP Error: port=%d result=0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619) port_num, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620) else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622) "SAS SMP Error: port=%d : CRC Error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623) port_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624) else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626) "SAS SMP Error: port=%d : Timeout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627) port_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628) else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) "SAS SMP Error: port=%d : No Destination",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) port_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634) "SAS SMP Error: port=%d : Bad Destination",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635) port_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637) snprintf(evStr, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638) "SAS SMP Error: port=%d : status=0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) port_num, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643) case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645) u8 reason = (u8)(evData0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647) switch (reason) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648) case MPI_EVENT_SAS_EXP_RC_ADDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649) ds = "Expander Status Change: Added";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652) ds = "Expander Status Change: Deleted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655) ds = "Expander Status Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) * MPT base "custom" events may be added here...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665) ds = "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668) if (ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) strlcpy(evStr, ds, EVENT_DESCR_STR_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672) devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) "MPT event:(%02Xh) : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674) ioc->name, event, evStr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) ": Event data:\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678) for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679) devtverboseprintk(ioc, printk(" %08x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680) le32_to_cpu(pEventReply->Data[ii])));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681) devtverboseprintk(ioc, printk(KERN_DEBUG "\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686) * ProcessEventNotification - Route EventNotificationReply to all event handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) * @pEventReply: Pointer to EventNotification reply frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689) * @evHandlers: Pointer to integer, number of event handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691) * Routes a received EventNotificationReply to all currently registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692) * event handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) * Returns sum of event handlers return values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696) ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698) u16 evDataLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699) u32 evData0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702) int r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) int handlers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704) u8 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) * Do platform normalization of values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) event = le32_to_cpu(pEventReply->Event) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) evDataLen = le16_to_cpu(pEventReply->EventDataLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711) if (evDataLen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712) evData0 = le32_to_cpu(pEventReply->Data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715) #ifdef CONFIG_FUSION_LOGGING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716) if (evDataLen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717) mpt_display_event_info(ioc, pEventReply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721) * Do general / base driver event processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) switch(event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724) case MPI_EVENT_EVENT_CHANGE: /* 0A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) if (evDataLen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) u8 evState = evData0 & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728) /* CHECKME! What if evState unexpectedly says OFF (0)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730) /* Update EventState field in cached IocFacts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) if (ioc->facts.Function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732) ioc->facts.EventState = evState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736) case MPI_EVENT_INTEGRATED_RAID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737) mptbase_raid_process_event_data(ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) (MpiEventDataRaid_t *)pEventReply->Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) * Should this event be logged? Events are written sequentially.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746) * When buffer is full, start again at the top.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) ioc->events[idx].event = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754) ioc->events[idx].eventContext = ioc->eventContext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756) for (ii = 0; ii < 2; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757) if (ii < evDataLen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760) ioc->events[idx].data[ii] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763) ioc->eventContext++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) * Call each currently registered protocol event handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) if (MptEvHandlers[cb_idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772) devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) "Routing Event to event handler #%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) ioc->name, cb_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775) r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776) handlers++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779) /* FIXME? Examine results here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) * If needed, send (a single) EventAck.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784) if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785) devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) "EventAck required\n",ioc->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787) if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788) devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789) ioc->name, ii));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793) *evHandlers = handlers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799) * mpt_fc_log_info - Log information returned from Fibre Channel IOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) * @log_info: U32 LogInfo reply word from the IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) * Refer to lsi/mpi_log_fc.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808) char *desc = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810) switch (log_info & 0xFF000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811) case MPI_IOCLOGINFO_FC_INIT_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812) desc = "FCP Initiator";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7814) case MPI_IOCLOGINFO_FC_TARGET_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7815) desc = "FCP Target";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7817) case MPI_IOCLOGINFO_FC_LAN_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7818) desc = "LAN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7820) case MPI_IOCLOGINFO_FC_MSG_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7821) desc = "MPI Message Layer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7823) case MPI_IOCLOGINFO_FC_LINK_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7824) desc = "FC Link";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7826) case MPI_IOCLOGINFO_FC_CTX_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7827) desc = "Context Manager";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7829) case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7830) desc = "Invalid Field Offset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7832) case MPI_IOCLOGINFO_FC_STATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7833) desc = "State Change Info";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7837) printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7838) ioc->name, log_info, desc, (log_info & 0xFFFFFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7841) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7842) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7843) * mpt_spi_log_info - Log information returned from SCSI Parallel IOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7844) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7845) * @log_info: U32 LogInfo word from the IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7846) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7847) * Refer to lsi/sp_log.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7849) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7850) mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7852) u32 info = log_info & 0x00FF0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7853) char *desc = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7855) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7856) case 0x00010000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7857) desc = "bug! MID not found";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7860) case 0x00020000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7861) desc = "Parity Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7864) case 0x00030000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7865) desc = "ASYNC Outbound Overrun";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7868) case 0x00040000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7869) desc = "SYNC Offset Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7872) case 0x00050000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7873) desc = "BM Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7876) case 0x00060000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7877) desc = "Msg In Overflow";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7878) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7880) case 0x00070000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7881) desc = "DMA Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7884) case 0x00080000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7885) desc = "Outbound DMA Overrun";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7888) case 0x00090000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7889) desc = "Task Management";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7892) case 0x000A0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7893) desc = "Device Problem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7896) case 0x000B0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7897) desc = "Invalid Phase Change";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7900) case 0x000C0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7901) desc = "Untagged Table Size";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7906) printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7909) /* strings for sas loginfo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7910) static char *originator_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7911) "IOP", /* 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7912) "PL", /* 01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7913) "IR" /* 02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7915) static char *iop_code_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7916) NULL, /* 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7917) "Invalid SAS Address", /* 01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7918) NULL, /* 02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7919) "Invalid Page", /* 03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7920) "Diag Message Error", /* 04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7921) "Task Terminated", /* 05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7922) "Enclosure Management", /* 06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7923) "Target Mode" /* 07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7925) static char *pl_code_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7926) NULL, /* 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7927) "Open Failure", /* 01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7928) "Invalid Scatter Gather List", /* 02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7929) "Wrong Relative Offset or Frame Length", /* 03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7930) "Frame Transfer Error", /* 04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7931) "Transmit Frame Connected Low", /* 05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7932) "SATA Non-NCQ RW Error Bit Set", /* 06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7933) "SATA Read Log Receive Data Error", /* 07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7934) "SATA NCQ Fail All Commands After Error", /* 08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7935) "SATA Error in Receive Set Device Bit FIS", /* 09h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7936) "Receive Frame Invalid Message", /* 0Ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7937) "Receive Context Message Valid Error", /* 0Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7938) "Receive Frame Current Frame Error", /* 0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7939) "SATA Link Down", /* 0Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7940) "Discovery SATA Init W IOS", /* 0Eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7941) "Config Invalid Page", /* 0Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7942) "Discovery SATA Init Timeout", /* 10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7943) "Reset", /* 11h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7944) "Abort", /* 12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7945) "IO Not Yet Executed", /* 13h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7946) "IO Executed", /* 14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7947) "Persistent Reservation Out Not Affiliation "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7948) "Owner", /* 15h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7949) "Open Transmit DMA Abort", /* 16h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7950) "IO Device Missing Delay Retry", /* 17h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7951) "IO Cancelled Due to Receive Error", /* 18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7952) NULL, /* 19h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7953) NULL, /* 1Ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7954) NULL, /* 1Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7955) NULL, /* 1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7956) NULL, /* 1Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7957) NULL, /* 1Eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7958) NULL, /* 1Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7959) "Enclosure Management" /* 20h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7961) static char *ir_code_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7962) "Raid Action Error", /* 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7963) NULL, /* 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7964) NULL, /* 01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7965) NULL, /* 02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7966) NULL, /* 03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7967) NULL, /* 04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7968) NULL, /* 05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7969) NULL, /* 06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7970) NULL /* 07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7972) static char *raid_sub_code_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7973) NULL, /* 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7974) "Volume Creation Failed: Data Passed too "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7975) "Large", /* 01h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7976) "Volume Creation Failed: Duplicate Volumes "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7977) "Attempted", /* 02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7978) "Volume Creation Failed: Max Number "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7979) "Supported Volumes Exceeded", /* 03h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7980) "Volume Creation Failed: DMA Error", /* 04h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7981) "Volume Creation Failed: Invalid Volume Type", /* 05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7982) "Volume Creation Failed: Error Reading "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7983) "MFG Page 4", /* 06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7984) "Volume Creation Failed: Creating Internal "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7985) "Structures", /* 07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7986) NULL, /* 08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7987) NULL, /* 09h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7988) NULL, /* 0Ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7989) NULL, /* 0Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7990) NULL, /* 0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7991) NULL, /* 0Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7992) NULL, /* 0Eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7993) NULL, /* 0Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7994) "Activation failed: Already Active Volume", /* 10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7995) "Activation failed: Unsupported Volume Type", /* 11h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7996) "Activation failed: Too Many Active Volumes", /* 12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7997) "Activation failed: Volume ID in Use", /* 13h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7998) "Activation failed: Reported Failure", /* 14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7999) "Activation failed: Importing a Volume", /* 15h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8000) NULL, /* 16h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8001) NULL, /* 17h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8002) NULL, /* 18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8003) NULL, /* 19h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8004) NULL, /* 1Ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8005) NULL, /* 1Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8006) NULL, /* 1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8007) NULL, /* 1Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8008) NULL, /* 1Eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8009) NULL, /* 1Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8010) "Phys Disk failed: Too Many Phys Disks", /* 20h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8011) "Phys Disk failed: Data Passed too Large", /* 21h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8012) "Phys Disk failed: DMA Error", /* 22h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8013) "Phys Disk failed: Invalid <channel:id>", /* 23h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8014) "Phys Disk failed: Creating Phys Disk Config "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8015) "Page", /* 24h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8016) NULL, /* 25h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8017) NULL, /* 26h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8018) NULL, /* 27h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8019) NULL, /* 28h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8020) NULL, /* 29h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8021) NULL, /* 2Ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8022) NULL, /* 2Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8023) NULL, /* 2Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8024) NULL, /* 2Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8025) NULL, /* 2Eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8026) NULL, /* 2Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8027) "Compatibility Error: IR Disabled", /* 30h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8028) "Compatibility Error: Inquiry Command Failed", /* 31h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8029) "Compatibility Error: Device not Direct Access "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8030) "Device ", /* 32h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8031) "Compatibility Error: Removable Device Found", /* 33h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8032) "Compatibility Error: Device SCSI Version not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8033) "2 or Higher", /* 34h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8034) "Compatibility Error: SATA Device, 48 BIT LBA "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8035) "not Supported", /* 35h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8036) "Compatibility Error: Device doesn't have "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8037) "512 Byte Block Sizes", /* 36h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8038) "Compatibility Error: Volume Type Check Failed", /* 37h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8039) "Compatibility Error: Volume Type is "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8040) "Unsupported by FW", /* 38h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8041) "Compatibility Error: Disk Drive too Small for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8042) "use in Volume", /* 39h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8043) "Compatibility Error: Phys Disk for Create "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8044) "Volume not Found", /* 3Ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8045) "Compatibility Error: Too Many or too Few "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8046) "Disks for Volume Type", /* 3Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8047) "Compatibility Error: Disk stripe Sizes "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8048) "Must be 64KB", /* 3Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8049) "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8052) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8053) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8054) * mpt_sas_log_info - Log information returned from SAS IOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8055) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8056) * @log_info: U32 LogInfo reply word from the IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8057) * @cb_idx: callback function's handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8058) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8059) * Refer to lsi/mpi_log_sas.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8060) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8061) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8062) mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8064) union loginfo_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8065) u32 loginfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8066) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8067) u32 subcode:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8068) u32 code:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8069) u32 originator:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8070) u32 bus_type:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8071) } dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8073) union loginfo_type sas_loginfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8074) char *originator_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8075) char *code_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8076) char *sub_code_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8078) sas_loginfo.loginfo = log_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8079) if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8080) (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8081) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8083) originator_desc = originator_str[sas_loginfo.dw.originator];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8085) switch (sas_loginfo.dw.originator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8087) case 0: /* IOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8088) if (sas_loginfo.dw.code <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8089) ARRAY_SIZE(iop_code_str))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8090) code_desc = iop_code_str[sas_loginfo.dw.code];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8092) case 1: /* PL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8093) if (sas_loginfo.dw.code <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8094) ARRAY_SIZE(pl_code_str))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8095) code_desc = pl_code_str[sas_loginfo.dw.code];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8097) case 2: /* IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8098) if (sas_loginfo.dw.code >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8099) ARRAY_SIZE(ir_code_str))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8101) code_desc = ir_code_str[sas_loginfo.dw.code];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8102) if (sas_loginfo.dw.subcode >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8103) ARRAY_SIZE(raid_sub_code_str))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8105) if (sas_loginfo.dw.code == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8106) sub_code_desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8107) raid_sub_code_str[sas_loginfo.dw.subcode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8110) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8113) if (sub_code_desc != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8114) printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8115) "LogInfo(0x%08x): Originator={%s}, Code={%s},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8116) " SubCode={%s} cb_idx %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8117) ioc->name, log_info, originator_desc, code_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8118) sub_code_desc, MptCallbacksName[cb_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8119) else if (code_desc != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8120) printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8121) "LogInfo(0x%08x): Originator={%s}, Code={%s},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8122) " SubCode(0x%04x) cb_idx %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8123) ioc->name, log_info, originator_desc, code_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8124) sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8125) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8126) printk(MYIOC_s_INFO_FMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8127) "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8128) " SubCode(0x%04x) cb_idx %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8129) ioc->name, log_info, originator_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8130) sas_loginfo.dw.code, sas_loginfo.dw.subcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8131) MptCallbacksName[cb_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8134) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8136) * mpt_iocstatus_info_config - IOCSTATUS information for config pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8137) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8138) * @ioc_status: U32 IOCStatus word from IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8139) * @mf: Pointer to MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8141) * Refer to lsi/mpi.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8142) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8143) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8144) mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8146) Config_t *pReq = (Config_t *)mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8147) char extend_desc[EVENT_DESCR_STR_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8148) char *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8149) u32 form;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8150) u8 page_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8152) if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8153) page_type = pReq->ExtPageType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8155) page_type = pReq->Header.PageType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8158) * ignore invalid page messages for GET_NEXT_HANDLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8160) form = le32_to_cpu(pReq->PageAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8161) if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8162) if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8163) page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8164) page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8165) if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8166) MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8167) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8169) if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8170) if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8171) MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8175) snprintf(extend_desc, EVENT_DESCR_STR_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8176) "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8177) page_type, pReq->Header.PageNumber, pReq->Action, form);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8179) switch (ioc_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8181) case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8182) desc = "Config Page Invalid Action";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8185) case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8186) desc = "Config Page Invalid Type";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8189) case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8190) desc = "Config Page Invalid Page";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8193) case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8194) desc = "Config Page Invalid Data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8197) case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8198) desc = "Config Page No Defaults";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8201) case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8202) desc = "Config Page Can't Commit";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8206) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8209) dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8210) ioc->name, ioc_status, desc, extend_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8214) * mpt_iocstatus_info - IOCSTATUS information returned from IOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8215) * @ioc: Pointer to MPT_ADAPTER structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8216) * @ioc_status: U32 IOCStatus word from IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8217) * @mf: Pointer to MPT request frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8219) * Refer to lsi/mpi.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8220) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8221) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8222) mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8224) u32 status = ioc_status & MPI_IOCSTATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8225) char *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8227) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8229) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8230) /* Common IOCStatus values for all replies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8231) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8233) case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8234) desc = "Invalid Function";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8237) case MPI_IOCSTATUS_BUSY: /* 0x0002 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8238) desc = "Busy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8241) case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8242) desc = "Invalid SGL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8245) case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8246) desc = "Internal Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8249) case MPI_IOCSTATUS_RESERVED: /* 0x0005 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8250) desc = "Reserved";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8253) case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8254) desc = "Insufficient Resources";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8257) case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8258) desc = "Invalid Field";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8261) case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8262) desc = "Invalid State";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8265) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8266) /* Config IOCStatus values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8267) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8269) case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8270) case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8271) case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8272) case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8273) case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8274) case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8275) mpt_iocstatus_info_config(ioc, status, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8278) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8279) /* SCSIIO Reply (SPI, FCP, SAS) initiator values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8280) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8281) /* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8282) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8283) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8285) case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8286) case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8287) case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8288) case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8289) case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8290) case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8291) case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8292) case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8293) case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8294) case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8295) case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8296) case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8297) case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8300) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8301) /* SCSI Target values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8302) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8304) case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8305) desc = "Target: Priority IO";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8308) case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8309) desc = "Target: Invalid Port";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8312) case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8313) desc = "Target Invalid IO Index:";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8316) case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8317) desc = "Target: Aborted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8320) case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8321) desc = "Target: No Conn Retryable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8324) case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8325) desc = "Target: No Connection";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8328) case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8329) desc = "Target: Transfer Count Mismatch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8332) case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8333) desc = "Target: STS Data not Sent";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8336) case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8337) desc = "Target: Data Offset Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8340) case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8341) desc = "Target: Too Much Write Data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8344) case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8345) desc = "Target: IU Too Short";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8348) case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8349) desc = "Target: ACK NAK Timeout";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8352) case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8353) desc = "Target: Nak Received";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8356) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8357) /* Fibre Channel Direct Access values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8358) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8360) case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8361) desc = "FC: Aborted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8364) case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8365) desc = "FC: RX ID Invalid";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8368) case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8369) desc = "FC: DID Invalid";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8372) case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8373) desc = "FC: Node Logged Out";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8376) case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8377) desc = "FC: Exchange Canceled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8380) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8381) /* LAN values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8382) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8384) case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8385) desc = "LAN: Device not Found";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8388) case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8389) desc = "LAN: Device Failure";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8392) case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8393) desc = "LAN: Transmit Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8396) case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8397) desc = "LAN: Transmit Aborted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8400) case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8401) desc = "LAN: Receive Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8404) case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8405) desc = "LAN: Receive Aborted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8408) case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8409) desc = "LAN: Partial Packet";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8412) case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8413) desc = "LAN: Canceled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8416) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8417) /* Serial Attached SCSI values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8418) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8420) case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8421) desc = "SAS: SMP Request Failed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8424) case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8425) desc = "SAS: SMP Data Overrun";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8428) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8429) desc = "Others";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8433) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8434) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8436) dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8437) ioc->name, status, desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8440) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8441) EXPORT_SYMBOL(mpt_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8442) EXPORT_SYMBOL(mpt_detach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8443) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8444) EXPORT_SYMBOL(mpt_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8445) EXPORT_SYMBOL(mpt_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8446) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8447) EXPORT_SYMBOL(ioc_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8448) EXPORT_SYMBOL(mpt_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8449) EXPORT_SYMBOL(mpt_deregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8450) EXPORT_SYMBOL(mpt_event_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8451) EXPORT_SYMBOL(mpt_event_deregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8452) EXPORT_SYMBOL(mpt_reset_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8453) EXPORT_SYMBOL(mpt_reset_deregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8454) EXPORT_SYMBOL(mpt_device_driver_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8455) EXPORT_SYMBOL(mpt_device_driver_deregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8456) EXPORT_SYMBOL(mpt_get_msg_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8457) EXPORT_SYMBOL(mpt_put_msg_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8458) EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8459) EXPORT_SYMBOL(mpt_free_msg_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8460) EXPORT_SYMBOL(mpt_send_handshake_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8461) EXPORT_SYMBOL(mpt_verify_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8462) EXPORT_SYMBOL(mpt_GetIocState);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8463) EXPORT_SYMBOL(mpt_print_ioc_summary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8464) EXPORT_SYMBOL(mpt_HardResetHandler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8465) EXPORT_SYMBOL(mpt_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8466) EXPORT_SYMBOL(mpt_findImVolumes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8467) EXPORT_SYMBOL(mpt_alloc_fw_memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8468) EXPORT_SYMBOL(mpt_free_fw_memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8469) EXPORT_SYMBOL(mptbase_sas_persist_operation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8470) EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8472) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8473) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8474) * fusion_init - Fusion MPT base driver initialization routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8475) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8476) * Returns 0 for success, non-zero for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8478) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8479) fusion_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8481) u8 cb_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8483) show_mptmod_ver(my_NAME, my_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8484) printk(KERN_INFO COPYRIGHT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8486) for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8487) MptCallbacks[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8488) MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8489) MptEvHandlers[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8490) MptResetHandlers[cb_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8493) /* Register ourselves (mptbase) in order to facilitate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8494) * EventNotification handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8496) mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8497) "mptbase_reply");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8499) /* Register for hard reset handling callbacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8501) mpt_reset_register(mpt_base_index, mpt_ioc_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8503) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8504) (void) procmpt_create();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8505) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8509) /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8510) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8511) * fusion_exit - Perform driver unload cleanup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8512) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8513) * This routine frees all resources associated with each MPT adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8514) * and removes all %MPT_PROCFS_MPTBASEDIR entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8516) static void __exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8517) fusion_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8520) mpt_reset_deregister(mpt_base_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8522) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8523) procmpt_destroy();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8524) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8527) module_init(fusion_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8528) module_exit(fusion_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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