Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2010 - Maxim Levitsky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * driver for Ricoh memstick readers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef R592_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/memstick.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kfifo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* write to this reg (number,len) triggers TPC execution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define R592_TPC_EXEC			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define R592_TPC_EXEC_LEN_SHIFT		16		/* Bits 16..25 are TPC len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define R592_TPC_EXEC_BIG_FIFO		(1 << 26)	/* If bit 26 is set, large fifo is used (reg 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define R592_TPC_EXEC_TPC_SHIFT		28		/* Bits 28..31 are the TPC number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* Window for small TPC fifo (big endian)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* reads and writes always are done in  8 byte chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* Not used in driver, because large fifo does better job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define R592_SFIFO			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Status register (ms int, small fifo, IO)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define R592_STATUS			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 							/* Parallel INT bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define R592_STATUS_P_CMDNACK		(1 << 16)	/* INT reg: NACK (parallel mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define R592_STATUS_P_BREQ		(1 << 17)	/* INT reg: card ready (parallel mode)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define R592_STATUS_P_INTERR		(1 << 18)	/* INT reg: int error (parallel mode)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define R592_STATUS_P_CED		(1 << 19)	/* INT reg: command done (parallel mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 							/* Fifo status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define R592_STATUS_SFIFO_FULL		(1 << 20)	/* Small Fifo almost full (last chunk is written) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define R592_STATUS_SFIFO_EMPTY		(1 << 21)	/* Small Fifo empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 							/* Error detection via CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define R592_STATUS_SEND_ERR		(1 << 24)	/* Send failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define R592_STATUS_RECV_ERR		(1 << 25)	/* Receive failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 							/* Card state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define R592_STATUS_RDY			(1 << 28)	/* RDY signal received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define R592_STATUS_CED			(1 << 29)	/* INT: Command done (serial mode)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define R592_STATUS_SFIFO_INPUT		(1 << 30)	/* Small fifo received data*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define R592_SFIFO_SIZE			32		/* total size of small fifo is 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define R592_SFIFO_PACKET		8		/* packet size of small fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* IO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define R592_IO				0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	R592_IO_16			(1 << 16)	/* Set by default, can be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	R592_IO_18			(1 << 18)	/* Set by default, can be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	R592_IO_SERIAL1			(1 << 20)	/* Set by default, can be cleared, (cleared on parallel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	R592_IO_22			(1 << 22)	/* Set by default, can be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define R592_IO_DIRECTION		(1 << 24)	/* TPC direction (1 write 0 read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define	R592_IO_26			(1 << 26)	/* Set by default, can be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define	R592_IO_SERIAL2			(1 << 30)	/* Set by default, can be cleared (cleared on parallel), serial doesn't work if unset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define R592_IO_RESET			(1 << 31)	/* Reset, sets defaults*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Turns hardware on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define R592_POWER			0x20		/* bits 0-7 writeable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define R592_POWER_0			(1 << 0)	/* set on start, cleared on stop - must be set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define R592_POWER_1			(1 << 1)	/* set on start, cleared on stop - must be set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define R592_POWER_3			(1 << 3)	/* must be clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define R592_POWER_20			(1 << 5)	/* set before switch to parallel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* IO mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define R592_IO_MODE			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define R592_IO_MODE_SERIAL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define R592_IO_MODE_PARALLEL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* IRQ,card detection,large fifo (first word irq status, second enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* IRQs are ACKed by clearing the bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define R592_REG_MSC			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define R592_REG_MSC_PRSNT		(1 << 1)	/* card present (only status)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define R592_REG_MSC_IRQ_INSERT		(1 << 8)	/* detect insert / card insered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define R592_REG_MSC_IRQ_REMOVE		(1 << 9)	/* detect removal / card removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define R592_REG_MSC_FIFO_EMPTY		(1 << 10)	/* fifo is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define R592_REG_MSC_FIFO_DMA_DONE	(1 << 11)	/* dma enable / dma done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define R592_REG_MSC_FIFO_USER_ORN	(1 << 12)	/* set if software reads empty fifo (if R592_REG_MSC_FIFO_EMPTY is set) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define R592_REG_MSC_FIFO_MISMATH	(1 << 13)	/* set if amount of data in fifo doesn't match amount in TPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define R592_REG_MSC_FIFO_DMA_ERR	(1 << 14)	/* IO failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define R592_REG_MSC_LED		(1 << 15)	/* clear to turn led off (only status)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DMA_IRQ_ACK_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	(R592_REG_MSC_FIFO_DMA_DONE | R592_REG_MSC_FIFO_DMA_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DMA_IRQ_EN_MASK (DMA_IRQ_ACK_MASK << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IRQ_ALL_ACK_MASK 0x00007F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IRQ_ALL_EN_MASK (IRQ_ALL_ACK_MASK << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* DMA address for large FIFO read/writes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R592_FIFO_DMA			0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PIO access to large FIFO (512 bytes) (big endian)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R592_FIFO_PIO			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R592_LFIFO_SIZE			512		/* large fifo size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* large FIFO DMA settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R592_FIFO_DMA_SETTINGS		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define R592_FIFO_DMA_SETTINGS_EN	(1 << 0)	/* DMA enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define R592_FIFO_DMA_SETTINGS_DIR	(1 << 1)	/* Dma direction (1 read, 0 write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define R592_FIFO_DMA_SETTINGS_CAP	(1 << 24)	/* Dma is aviable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Maybe just an delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Bits 17..19 are just number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* bit 16 is set, then bit 20 is waited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* time to wait is about 50 spins * 2 ^ (bits 17..19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* seems to be possible just to ignore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Probably debug register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define R592_REG38			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define R592_REG38_CHANGE		(1 << 16)	/* Start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define R592_REG38_DONE			(1 << 20)	/* HW set this after the delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define R592_REG38_SHIFT		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Debug register, written (0xABCDEF00) when error happens - not used*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define R592_REG_3C			0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct r592_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct memstick_host	*host;		/* host backpointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct memstick_request *req;		/* current request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Registers, IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	spinlock_t io_thread_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct timer_list detect_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct task_struct *io_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bool parallel_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	DECLARE_KFIFO(pio_fifo, u8, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* DMA area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int dma_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int dma_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct completion dma_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	void *dummy_dma_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	dma_addr_t dummy_dma_page_physical_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DRV_NAME "r592"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define message(format, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	printk(KERN_INFO DRV_NAME ": " format "\n", ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define __dbg(level, format, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		if (debug >= level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			printk(KERN_DEBUG DRV_NAME \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				": " format "\n", ## __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	} while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define dbg(format, ...)		__dbg(1, format, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define dbg_verbose(format, ...)	__dbg(2, format, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define dbg_reg(format, ...)		__dbg(3, format, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif