^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/memstick.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRIVER_NAME "jmb38x_ms"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static bool no_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) module_param(no_dma, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DMA_ADDRESS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) BLOCK = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DMA_CONTROL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) TPC_P0 = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) TPC_P1 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) TPC = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) HOST_CONTROL = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DATA = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) STATUS = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) INT_STATUS = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) INT_STATUS_ENABLE = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) INT_SIGNAL_ENABLE = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) TIMER = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) TIMER_CONTROL = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PAD_OUTPUT_ENABLE = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PAD_PU_PD = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CLOCK_DELAY = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ADMA_ADDRESS = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CLOCK_CONTROL = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) LED_CONTROL = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) VERSION = 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct jmb38x_ms_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct jmb38x_ms *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct tasklet_struct notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) char host_id[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int block_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long timeout_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct memstick_host *msh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct memstick_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned char cmd_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned char io_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned char ifmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int io_word[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct jmb38x_ms {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int host_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct memstick_host *hosts[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BLOCK_COUNT_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BLOCK_SIZE_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DMA_CONTROL_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TPC_DATA_SEL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TPC_DIR 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TPC_WAIT_INT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TPC_GET_INT 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TPC_CODE_SZ_MASK 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TPC_DATA_SZ_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HOST_CONTROL_TDELAY_EN 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HOST_CONTROL_HW_OC_P 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HOST_CONTROL_RESET_REQ 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HOST_CONTROL_REI 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HOST_CONTROL_LED 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HOST_CONTROL_FAST_CLK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HOST_CONTROL_RESET 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HOST_CONTROL_POWER_EN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HOST_CONTROL_CLOCK_EN 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HOST_CONTROL_REO 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HOST_CONTROL_IF_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HOST_CONTROL_IF_SERIAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HOST_CONTROL_IF_PAR4 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HOST_CONTROL_IF_PAR8 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STATUS_BUSY 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STATUS_MS_DAT7 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STATUS_MS_DAT6 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define STATUS_MS_DAT5 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STATUS_MS_DAT4 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STATUS_MS_DAT3 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STATUS_MS_DAT2 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STATUS_MS_DAT1 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define STATUS_MS_DAT0 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define STATUS_HAS_MEDIA 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define STATUS_FIFO_EMPTY 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define STATUS_FIFO_FULL 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define STATUS_MS_CED 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define STATUS_MS_ERR 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define STATUS_MS_BRQ 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STATUS_MS_CNK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define INT_STATUS_TPC_ERR 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INT_STATUS_CRC_ERR 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define INT_STATUS_TIMER_TO 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INT_STATUS_HSK_TO 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define INT_STATUS_ANY_ERR 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define INT_STATUS_FIFO_WRDY 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define INT_STATUS_FIFO_RRDY 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define INT_STATUS_MEDIA_OUT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define INT_STATUS_MEDIA_IN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define INT_STATUS_DMA_BOUNDARY 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define INT_STATUS_EOTRAN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define INT_STATUS_EOTPC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INT_STATUS_ALL 0x000f801f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PAD_OUTPUT_ENABLE_MS 0x0F3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PAD_PU_PD_OFF 0x7FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLOCK_CONTROL_BY_MMIO 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLOCK_CONTROL_40MHZ 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLOCK_CONTROL_50MHZ 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLOCK_CONTROL_60MHZ 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLOCK_CONTROL_62_5MHZ 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLOCK_CONTROL_OFF 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCI_CTL_CLOCK_DLY_ADDR 0x000000b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CMD_READY = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FIFO_READY = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) REG_DATA = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DMA_DATA = 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned char *buf, unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) while (host->io_pos && length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) buf[off++] = host->io_word[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) host->io_word[0] >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) host->io_pos--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (length < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) length -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) off += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) host->io_word[0] = readl(host->addr + DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (host->io_pos = 4; host->io_pos; --host->io_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) buf[off++] = host->io_word[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) host->io_word[0] >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) while (host->io_pos > 4 && length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) buf[off++] = host->io_word[0] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) host->io_word[0] >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) host->io_pos--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) while (host->io_pos && length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) buf[off++] = host->io_word[1] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) host->io_word[1] >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) host->io_pos--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (host->io_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) while (host->io_pos < 4 && length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) host->io_word[0] |= buf[off++] << (host->io_pos * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) host->io_pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (host->io_pos == 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel(host->io_word[0], host->addr + DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) host->io_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) host->io_word[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } else if (host->io_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (length < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __raw_writel(*(unsigned int *)(buf + off),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) host->addr + DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) length -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) off += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) switch (length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) host->io_word[0] |= buf[off + 2] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) host->io_pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) host->io_word[0] |= buf[off + 1] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) host->io_pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) host->io_word[0] |= buf[off];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) host->io_pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) off += host->io_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) while (host->io_pos < 4 && length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) host->io_word[0] &= ~(0xff << (host->io_pos * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) host->io_word[0] |= buf[off++] << (host->io_pos * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) host->io_pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) while (host->io_pos < 8 && length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) host->io_word[1] &= ~(0xff << (host->io_pos * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) host->io_word[1] |= buf[off++] << (host->io_pos * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) host->io_pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int t_size, p_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct page *pg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (host->req->long_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) length = host->req->sg.length - host->block_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) off = host->req->sg.offset + host->block_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) length = host->req->data_len - host->block_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) while (length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int p_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (host->req->long_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pg = nth_page(sg_page(&host->req->sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) off >> PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) p_off = offset_in_page(off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) p_cnt = PAGE_SIZE - p_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) p_cnt = min(p_cnt, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) buf = kmap_atomic(pg) + p_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) buf = host->req->data + host->block_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) p_cnt = host->req->data_len - host->block_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (host->req->data_dir == WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) t_size = !(host->cmd_flags & REG_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ? jmb38x_ms_write_data(host, buf, p_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) : jmb38x_ms_write_reg_data(host, buf, p_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) t_size = !(host->cmd_flags & REG_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ? jmb38x_ms_read_data(host, buf, p_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) : jmb38x_ms_read_reg_data(host, buf, p_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (host->req->long_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) kunmap_atomic(buf - p_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!t_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) host->block_pos += t_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) length -= t_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) off += t_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!length && host->req->data_dir == WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (host->cmd_flags & REG_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel(host->io_word[0], host->addr + TPC_P0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writel(host->io_word[1], host->addr + TPC_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } else if (host->io_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) writel(host->io_word[0], host->addr + DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int jmb38x_ms_issue_cmd(struct memstick_host *msh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct jmb38x_ms_host *host = memstick_priv(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int data_len, cmd, t_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_dbg(&msh->dev, "no media status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) host->req->error = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return host->req->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_dbg(&msh->dev, "control %08x\n", readl(host->addr + HOST_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) host->cmd_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) host->block_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) host->io_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) host->io_word[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) host->io_word[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) cmd = host->req->tpc << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cmd |= TPC_DATA_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (host->req->data_dir == READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) cmd |= TPC_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (host->req->need_card_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (host->ifmode == MEMSTICK_SERIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) cmd |= TPC_GET_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) cmd |= TPC_WAIT_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!no_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) host->cmd_flags |= DMA_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (host->req->long_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) data_len = host->req->sg.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data_len = host->req->data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) host->cmd_flags &= ~DMA_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (data_len <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cmd &= ~(TPC_DATA_SEL | 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) host->cmd_flags |= REG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cmd |= data_len & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) host->cmd_flags &= ~DMA_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (host->cmd_flags & DMA_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (1 != dma_map_sg(&host->chip->pdev->dev, &host->req->sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) host->req->data_dir == READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ? DMA_FROM_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) : DMA_TO_DEVICE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) host->req->error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return host->req->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) data_len = sg_dma_len(&host->req->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) writel(sg_dma_address(&host->req->sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) host->addr + DMA_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) writel(((1 << 16) & BLOCK_COUNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) | (data_len & BLOCK_SIZE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) host->addr + BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } else if (!(host->cmd_flags & REG_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel(((1 << 16) & BLOCK_COUNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) | (data_len & BLOCK_SIZE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) host->addr + BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) t_val = readl(host->addr + INT_STATUS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) t_val |= host->req->data_dir == READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ? INT_STATUS_FIFO_RRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) : INT_STATUS_FIFO_WRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) writel(t_val, host->addr + INT_STATUS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) writel(t_val, host->addr + INT_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cmd &= ~(TPC_DATA_SEL | 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) host->cmd_flags |= REG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cmd |= data_len & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (host->req->data_dir == WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) jmb38x_ms_transfer_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writel(host->io_word[0], host->addr + TPC_P0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) writel(host->io_word[1], host->addr + TPC_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mod_timer(&host->timer, jiffies + host->timeout_jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) host->addr + HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) host->req->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) writel(cmd, host->addr + TPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_dbg(&msh->dev, "executing TPC %08x, len %x\n", cmd, data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct jmb38x_ms_host *host = memstick_priv(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int t_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) del_timer(&host->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_dbg(&msh->dev, "c control %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) readl(host->addr + HOST_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_dbg(&msh->dev, "c status %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) readl(host->addr + INT_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) host->req->int_reg = readl(host->addr + STATUS) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) writel(0, host->addr + BLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) writel(0, host->addr + DMA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (host->cmd_flags & DMA_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dma_unmap_sg(&host->chip->pdev->dev, &host->req->sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) host->req->data_dir == READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) t_val = readl(host->addr + INT_STATUS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (host->req->data_dir == READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) t_val &= ~INT_STATUS_FIFO_RRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) t_val &= ~INT_STATUS_FIFO_WRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) writel(t_val, host->addr + INT_STATUS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) writel(t_val, host->addr + INT_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) host->addr + HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rc = memstick_next_req(msh, &host->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } while (!rc && jmb38x_ms_issue_cmd(msh));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) rc = memstick_next_req(msh, &host->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) host->req->error = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) } while (!rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct memstick_host *msh = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct jmb38x_ms_host *host = memstick_priv(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) irq_status = readl(host->addr + INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (irq_status == 0 || irq_status == (~0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (host->req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (irq_status & INT_STATUS_ANY_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (irq_status & INT_STATUS_CRC_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) host->req->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) else if (irq_status & INT_STATUS_TPC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_dbg(&host->chip->pdev->dev, "TPC_ERR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) jmb38x_ms_complete_cmd(msh, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) host->req->error = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (host->cmd_flags & DMA_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (irq_status & INT_STATUS_EOTRAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) host->cmd_flags |= FIFO_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (irq_status & (INT_STATUS_FIFO_RRDY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) | INT_STATUS_FIFO_WRDY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) jmb38x_ms_transfer_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (irq_status & INT_STATUS_EOTRAN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) jmb38x_ms_transfer_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) host->cmd_flags |= FIFO_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (irq_status & INT_STATUS_EOTPC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) host->cmd_flags |= CMD_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (host->cmd_flags & REG_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (host->req->data_dir == READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) host->io_word[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) = readl(host->addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) + TPC_P0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) host->io_word[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) = readl(host->addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) + TPC_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) host->io_pos = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) jmb38x_ms_transfer_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) host->cmd_flags |= FIFO_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_dbg(&host->chip->pdev->dev, "media changed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) memstick_detect_change(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) writel(irq_status, host->addr + INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (host->req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) && (((host->cmd_flags & CMD_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) && (host->cmd_flags & FIFO_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) || host->req->error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) jmb38x_ms_complete_cmd(msh, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static void jmb38x_ms_abort(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct jmb38x_ms_host *host = from_timer(host, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct memstick_host *msh = host->msh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_dbg(&host->chip->pdev->dev, "abort\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (host->req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) host->req->error = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) jmb38x_ms_complete_cmd(msh, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void jmb38x_ms_req_tasklet(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct memstick_host *msh = (struct memstick_host *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct jmb38x_ms_host *host = memstick_priv(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!host->req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) rc = memstick_next_req(msh, &host->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_dbg(&host->chip->pdev->dev, "tasklet req %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) } while (!rc && jmb38x_ms_issue_cmd(msh));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void jmb38x_ms_dummy_submit(struct memstick_host *msh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void jmb38x_ms_submit_req(struct memstick_host *msh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct jmb38x_ms_host *host = memstick_priv(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) tasklet_schedule(&host->notify);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int jmb38x_ms_reset(struct jmb38x_ms_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) | readl(host->addr + HOST_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) host->addr + HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) for (cnt = 0; cnt < 20; ++cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!(HOST_CONTROL_RESET_REQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) & readl(host->addr + HOST_CONTROL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto reset_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ndelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) reset_next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) | readl(host->addr + HOST_CONTROL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) host->addr + HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (cnt = 0; cnt < 20; ++cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!(HOST_CONTROL_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) & readl(host->addr + HOST_CONTROL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) goto reset_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ndelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_dbg(&host->chip->pdev->dev, "reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) reset_ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int jmb38x_ms_set_param(struct memstick_host *msh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) enum memstick_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct jmb38x_ms_host *host = memstick_priv(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case MEMSTICK_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (value == MEMSTICK_POWER_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) rc = jmb38x_ms_reset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) host_ctl = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) host_ctl |= HOST_CONTROL_POWER_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) | HOST_CONTROL_CLOCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) writel(host_ctl, host->addr + HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) : PAD_PU_PD_ON_MS_SOCK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) host->addr + PAD_PU_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) writel(PAD_OUTPUT_ENABLE_MS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) host->addr + PAD_OUTPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_dbg(&host->chip->pdev->dev, "power on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) } else if (value == MEMSTICK_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) host_ctl &= ~(HOST_CONTROL_POWER_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) | HOST_CONTROL_CLOCK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) writel(host_ctl, host->addr + HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel(0, host->addr + PAD_OUTPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_dbg(&host->chip->pdev->dev, "power off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case MEMSTICK_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_dbg(&host->chip->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "Set Host Interface Mode to %d\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) host_ctl &= ~(HOST_CONTROL_FAST_CLK | HOST_CONTROL_REI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) HOST_CONTROL_REO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) host_ctl |= HOST_CONTROL_TDELAY_EN | HOST_CONTROL_HW_OC_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (value == MEMSTICK_SERIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) host_ctl |= HOST_CONTROL_IF_SERIAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) << HOST_CONTROL_IF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) host_ctl |= HOST_CONTROL_REI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) clock_ctl |= CLOCK_CONTROL_40MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) clock_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) } else if (value == MEMSTICK_PAR4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) host_ctl |= HOST_CONTROL_FAST_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) host_ctl |= HOST_CONTROL_IF_PAR4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) << HOST_CONTROL_IF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) host_ctl |= HOST_CONTROL_REO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) clock_ctl |= CLOCK_CONTROL_40MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) clock_delay = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else if (value == MEMSTICK_PAR8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) host_ctl |= HOST_CONTROL_FAST_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) host_ctl |= HOST_CONTROL_IF_PAR8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) << HOST_CONTROL_IF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) clock_ctl |= CLOCK_CONTROL_50MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clock_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) writel(host_ctl, host->addr + HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) writel(clock_ctl, host->addr + CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pci_write_config_byte(host->chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PCI_CTL_CLOCK_DLY_ADDR + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) clock_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) host->ifmode = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define PCI_PMOS0_CONTROL 0xae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define PMOS0_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define PMOS0_OVERCURRENT_LEVEL_2_4V 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define PMOS0_EN_OVERCURRENT_DEBOUNCE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define PMOS0_SW_LED_POLARITY_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define PMOS0_ACTIVE_BITS (PMOS0_ENABLE | PMOS0_EN_OVERCURRENT_DEBOUNCE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PMOS0_OVERCURRENT_LEVEL_2_4V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define PCI_PMOS1_CONTROL 0xbd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define PMOS1_ACTIVE_BITS 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define PCI_CLOCK_CTL 0xb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int jmb38x_ms_pmos(struct pci_dev *pdev, int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pci_read_config_byte(pdev, PCI_PMOS0_CONTROL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) val |= PMOS0_ACTIVE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) val &= ~PMOS0_ACTIVE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pci_write_config_byte(pdev, PCI_PMOS0_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_dbg(&pdev->dev, "JMB38x: set PMOS0 val 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (pci_resource_flags(pdev, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pci_read_config_byte(pdev, PCI_PMOS1_CONTROL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) val |= PMOS1_ACTIVE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) val &= ~PMOS1_ACTIVE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pci_write_config_byte(pdev, PCI_PMOS1_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_dbg(&pdev->dev, "JMB38x: set PMOS1 val 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) pci_read_config_byte(pdev, PCI_CLOCK_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pci_write_config_byte(pdev, PCI_CLOCK_CTL, val & ~0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pci_write_config_byte(pdev, PCI_CLOCK_CTL, val | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev_dbg(&pdev->dev, "Clock Control by PCI config is disabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int __maybe_unused jmb38x_ms_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct jmb38x_ms *jm = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!jm->hosts[cnt])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) memstick_suspend_host(jm->hosts[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) device_wakeup_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int __maybe_unused jmb38x_ms_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct jmb38x_ms *jm = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) jmb38x_ms_pmos(to_pci_dev(dev), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) for (rc = 0; rc < jm->host_cnt; ++rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!jm->hosts[rc])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) memstick_resume_host(jm->hosts[rc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) memstick_detect_change(jm->hosts[rc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int jmb38x_ms_count_slots(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int cnt, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) for (cnt = 0; cnt < PCI_STD_NUM_BARS; ++cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (256 != pci_resource_len(pdev, cnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ++rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct memstick_host *msh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct jmb38x_ms_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) &jm->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!msh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) host = memstick_priv(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) host->msh = msh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) host->chip = jm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) host->addr = ioremap(pci_resource_start(jm->pdev, cnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pci_resource_len(jm->pdev, cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!host->addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) goto err_out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) host->id = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) snprintf(host->host_id, sizeof(host->host_id), DRIVER_NAME ":slot%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) host->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) host->irq = jm->pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) host->timeout_jiffies = msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) tasklet_init(&host->notify, jmb38x_ms_req_tasklet, (unsigned long)msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) msh->request = jmb38x_ms_submit_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) msh->set_param = jmb38x_ms_set_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) timer_setup(&host->timer, jmb38x_ms_abort, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) msh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return msh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) iounmap(host->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) err_out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) memstick_free_host(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static void jmb38x_ms_free_host(struct memstick_host *msh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct jmb38x_ms_host *host = memstick_priv(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) free_irq(host->irq, msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) iounmap(host->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) memstick_free_host(msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int jmb38x_ms_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) const struct pci_device_id *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct jmb38x_ms *jm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int pci_dev_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int rc, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) rc = pci_request_regions(pdev, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pci_dev_busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) jmb38x_ms_pmos(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) cnt = jmb38x_ms_count_slots(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) pci_dev_busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) goto err_out_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) jm = kzalloc(sizeof(struct jmb38x_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) + cnt * sizeof(struct memstick_host *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (!jm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) goto err_out_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) jm->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) jm->host_cnt = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) pci_set_drvdata(pdev, jm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (!jm->hosts[cnt])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) rc = memstick_add_host(jm->hosts[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) jmb38x_ms_free_host(jm->hosts[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) jm->hosts[cnt] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) pci_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) kfree(jm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) err_out_int:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!pci_dev_busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static void jmb38x_ms_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct jmb38x_ms *jm = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct jmb38x_ms_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (!jm->hosts[cnt])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) host = memstick_priv(jm->hosts[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) jm->hosts[cnt]->request = jmb38x_ms_dummy_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) tasklet_kill(&host->notify);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) writel(0, host->addr + INT_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) writel(0, host->addr + INT_STATUS_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dev_dbg(&jm->pdev->dev, "interrupts off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (host->req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) host->req->error = -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) jmb38x_ms_complete_cmd(jm->hosts[cnt], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) memstick_remove_host(jm->hosts[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) dev_dbg(&jm->pdev->dev, "host removed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) jmb38x_ms_free_host(jm->hosts[cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) jmb38x_ms_pmos(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pci_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) kfree(jm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static struct pci_device_id jmb38x_ms_id_tbl [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB385_MS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB390_MS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static SIMPLE_DEV_PM_OPS(jmb38x_ms_pm_ops, jmb38x_ms_suspend, jmb38x_ms_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static struct pci_driver jmb38x_ms_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .id_table = jmb38x_ms_id_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .probe = jmb38x_ms_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .remove = jmb38x_ms_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .driver.pm = &jmb38x_ms_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) module_pci_driver(jmb38x_ms_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) MODULE_AUTHOR("Alex Dubov");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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