^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI AEMIF driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Murali Karicheri <m-karicheri2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/ti-aemif.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TA_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RHOLD_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RSTROBE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RSETUP_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WHOLD_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WSTROBE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WSETUP_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EW_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SSTROBE_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TA(x) ((x) << TA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RHOLD(x) ((x) << RHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RSTROBE(x) ((x) << RSTROBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RSETUP(x) ((x) << RSETUP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WHOLD(x) ((x) << WHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WSTROBE(x) ((x) << WSTROBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WSETUP(x) ((x) << WSETUP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EW(x) ((x) << EW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SSTROBE(x) ((x) << SSTROBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ASIZE_MAX 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TA_MAX 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RHOLD_MAX 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RSTROBE_MAX 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RSETUP_MAX 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WHOLD_MAX 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WSTROBE_MAX 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WSETUP_MAX 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EW_MAX 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSTROBE_MAX 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NUM_CS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RHOLD_VAL(x) (((x) & RHOLD(RHOLD_MAX)) >> RHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RSTROBE_VAL(x) (((x) & RSTROBE(RSTROBE_MAX)) >> RSTROBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RSETUP_VAL(x) (((x) & RSETUP(RSETUP_MAX)) >> RSETUP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WHOLD_VAL(x) (((x) & WHOLD(WHOLD_MAX)) >> WHOLD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WSTROBE_VAL(x) (((x) & WSTROBE(WSTROBE_MAX)) >> WSTROBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WSETUP_VAL(x) (((x) & WSETUP(WSETUP_MAX)) >> WSETUP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EW_VAL(x) (((x) & EW(EW_MAX)) >> EW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SSTROBE_VAL(x) (((x) & SSTROBE(SSTROBE_MAX)) >> SSTROBE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NRCSR_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AWCCR_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define A1CR_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ACR_ASIZE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ACR_EW_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ACR_SSTROBE_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ASIZE_16BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CONFIG_MASK (TA(TA_MAX) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) RHOLD(RHOLD_MAX) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) RSTROBE(RSTROBE_MAX) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) RSETUP(RSETUP_MAX) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) WHOLD(WHOLD_MAX) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) WSTROBE(WSTROBE_MAX) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) WSETUP(WSETUP_MAX) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ASIZE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * struct aemif_cs_data: structure to hold cs parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @cs: chip-select number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @wstrobe: write strobe width, ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @rstrobe: read strobe width, ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @wsetup: write setup width, ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @whold: write hold width, ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @rsetup: read setup width, ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @rhold: read hold width, ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @ta: minimum turn around time, ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @enable_ss: enable/disable select strobe mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @enable_ew: enable/disable extended wait mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @asize: width of the asynchronous device's data bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct aemif_cs_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 wstrobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 rstrobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 wsetup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 whold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 rsetup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 rhold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 ta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 enable_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 enable_ew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * struct aemif_device: structure to hold device data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @base: base address of AEMIF registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @clk: source clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @clk_rate: clock's rate in kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @num_cs: number of assigned chip-selects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @cs_offset: start number of cs nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @cs_data: array of chip-select settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct aemif_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 num_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int cs_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct aemif_cs_data cs_data[NUM_CS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * aemif_calc_rate - calculate timing data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @pdev: platform device to calculate for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @wanted: The cycle time needed in nanoseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @clk: The input clock rate in kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @max: The maximum divider value that can be programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * On success, returns the calculated timing value minus 1 for easy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * programming into AEMIF timing registers, else negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int aemif_calc_rate(struct platform_device *pdev, int wanted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned long clk, int max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_dbg(&pdev->dev, "%s: result %d from %ld, %d\n", __func__, result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk, wanted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* It is generally OK to have a more relaxed timing than requested... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* ... But configuring tighter timings is not an option. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else if (result > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * aemif_config_abus - configure async bus parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @pdev: platform device to configure for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @csnum: aemif chip select number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * This function programs the given timing values (in real clock) into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * AEMIF registers taking the AEMIF clock into account.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * This function does not use any locking while programming the AEMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * because it is expected that there is only one user of a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * chip-select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Returns 0 on success, else negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int aemif_config_abus(struct platform_device *pdev, int csnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct aemif_device *aemif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct aemif_cs_data *data = &aemif->cs_data[csnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long clk_rate = aemif->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 set, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) whold < 0 || wstrobe < 0 || wsetup < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(&pdev->dev, "%s: cannot get suitable timings\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) set |= (data->asize & ACR_ASIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (data->enable_ew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) set |= ACR_EW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (data->enable_ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) set |= ACR_SSTROBE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = readl(aemif->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val &= ~CONFIG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) writel(val, aemif->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ((val + 1) * NSEC_PER_MSEC) / clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * aemif_get_hw_params - function to read hw register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @pdev: platform device to read for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @csnum: aemif chip select number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * This function reads the defaults from the registers and update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * the timing values. Required for get/set commands and also for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * the case when driver needs to use defaults in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void aemif_get_hw_params(struct platform_device *pdev, int csnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct aemif_device *aemif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct aemif_cs_data *data = &aemif->cs_data[csnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long clk_rate = aemif->clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 val, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val = readl(aemif->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) data->ta = aemif_cycles_to_nsec(TA_VAL(val), clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) data->rhold = aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) data->rstrobe = aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) data->rsetup = aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) data->whold = aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) data->wstrobe = aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) data->wsetup = aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) data->enable_ew = EW_VAL(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) data->enable_ss = SSTROBE_VAL(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) data->asize = val & ASIZE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * of_aemif_parse_abus_config - parse CS configuration from DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @pdev: platform device to parse for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @np: device node ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * This function update the emif async bus configuration based on the values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * configured in a cs device binding node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int of_aemif_parse_abus_config(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct aemif_device *aemif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct aemif_cs_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_dbg(&pdev->dev, "cs property is required");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_dbg(&pdev->dev, "cs number is incorrect %d", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (aemif->num_cs >= NUM_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_dbg(&pdev->dev, "cs count is more than %d", NUM_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) data = &aemif->cs_data[aemif->num_cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) data->cs = cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* read the current value in the hw register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) aemif_get_hw_params(pdev, aemif->num_cs++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* override the values from device node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) data->ta = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) data->rhold = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) data->rstrobe = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) data->rsetup = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data->whold = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) data->wstrobe = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data->wsetup = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!of_property_read_u32(np, "ti,cs-bus-width", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (val == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) data->asize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct of_device_id aemif_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { .compatible = "ti,davinci-aemif", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .compatible = "ti,da850-aemif", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MODULE_DEVICE_TABLE(of, aemif_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int aemif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct device_node *child_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct aemif_device *aemif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct aemif_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct of_dev_auxdata *dev_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) aemif = devm_kzalloc(dev, sizeof(*aemif), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!aemif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_lookup = pdata ? pdata->dev_lookup : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) platform_set_drvdata(pdev, aemif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) aemif->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (IS_ERR(aemif->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(dev, "cannot get clock 'aemif'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return PTR_ERR(aemif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = clk_prepare_enable(aemif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) aemif->clk_rate = clk_get_rate(aemif->clk) / MSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (np && of_device_is_compatible(np, "ti,da850-aemif"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) aemif->cs_offset = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) aemif->cs_offset = pdata->cs_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) aemif->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (IS_ERR(aemif->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = PTR_ERR(aemif->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * For every controller device node, there is a cs device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * that describe the bus configuration parameters. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * functions iterate over these nodes and update the cs data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for_each_available_child_of_node(np, child_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = of_aemif_parse_abus_config(pdev, child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) of_node_put(child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } else if (pdata && pdata->num_abus_data > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 0; i < pdata->num_abus_data; i++, aemif->num_cs++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) aemif->cs_data[i].cs = pdata->abus_data[i].cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) aemif_get_hw_params(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for (i = 0; i < aemif->num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = aemif_config_abus(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(dev, "Error configuring chip select %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) aemif->cs_data[i].cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Create a child devices explicitly from here to guarantee that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * child will be probed after the AEMIF timing parameters are set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for_each_available_child_of_node(np, child_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = of_platform_populate(child_np, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_lookup, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) of_node_put(child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } else if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) for (i = 0; i < pdata->num_sub_devices; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pdata->sub_devices[i].dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = platform_device_register(&pdata->sub_devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_warn(dev, "Error register sub device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pdata->sub_devices[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk_disable_unprepare(aemif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int aemif_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct aemif_device *aemif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clk_disable_unprepare(aemif->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct platform_driver aemif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .probe = aemif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .remove = aemif_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .name = "ti-aemif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .of_match_table = of_match_ptr(aemif_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) module_platform_driver(aemif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_DESCRIPTION("Texas Instruments AEMIF driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_ALIAS("platform:" KBUILD_MODNAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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