^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Tegra30 External Memory Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on downstream driver from NVIDIA and tegra124-emc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011-2014 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Dmitry Osipenko <digetx@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2019 GRATE-DRIVER project
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EMC_INTSTATUS 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EMC_INTMASK 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EMC_DBG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EMC_CFG 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EMC_REFCTRL 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EMC_TIMING_CONTROL 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EMC_RC 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EMC_RFC 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EMC_RAS 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EMC_RP 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EMC_R2W 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EMC_W2R 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EMC_R2P 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EMC_W2P 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EMC_RD_RCD 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EMC_WR_RCD 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EMC_RRD 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EMC_REXT 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EMC_WDV 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EMC_QUSE 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EMC_QRST 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EMC_QSAFE 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EMC_RDV 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EMC_REFRESH 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EMC_BURST_REFRESH_NUM 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EMC_PDEX2WR 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EMC_PDEX2RD 0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EMC_PCHG2PDEN 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EMC_ACT2PDEN 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EMC_AR2PDEN 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EMC_RW2PDEN 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EMC_TXSR 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EMC_TCKE 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EMC_TFAW 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EMC_TRPAB 0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EMC_TCLKSTABLE 0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EMC_TCLKSTOP 0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EMC_TREFBW 0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EMC_QUSE_EXTRA 0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EMC_ODT_WRITE 0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EMC_ODT_READ 0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EMC_WEXT 0x0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EMC_CTT 0x0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EMC_MRS_WAIT_CNT 0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EMC_MRS 0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EMC_EMRS 0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EMC_SELF_REF 0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EMC_MRW 0x0e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EMC_XM2DQSPADCTRL3 0x0f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EMC_FBIO_SPARE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EMC_FBIO_CFG5 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EMC_FBIO_CFG6 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EMC_CFG_RSV 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EMC_AUTO_CAL_CONFIG 0x2a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EMC_AUTO_CAL_INTERVAL 0x2a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EMC_AUTO_CAL_STATUS 0x2ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EMC_STATUS 0x2b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EMC_CFG_2 0x2b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EMC_CFG_DIG_DLL 0x2bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EMC_CTT_DURATION 0x2d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EMC_CTT_TERM_CTRL 0x2dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define EMC_ZCAL_INTERVAL 0x2e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define EMC_ZCAL_WAIT_CNT 0x2e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EMC_ZQ_CAL 0x2ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EMC_XM2CMDPADCTRL 0x2f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EMC_XM2DQSPADCTRL2 0x2fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EMC_XM2DQPADCTRL2 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define EMC_XM2CLKPADCTRL 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EMC_XM2COMPPADCTRL 0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EMC_XM2VTTGENPADCTRL 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define EMC_XM2VTTGENPADCTRL2 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EMC_XM2QUSEPADCTRL 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EMC_DLL_XFORM_DQS0 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EMC_DLL_XFORM_DQS1 0x32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EMC_DLL_XFORM_DQS2 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define EMC_DLL_XFORM_DQS3 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EMC_DLL_XFORM_DQS4 0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EMC_DLL_XFORM_DQS5 0x33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EMC_DLL_XFORM_DQS6 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EMC_DLL_XFORM_DQS7 0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EMC_DLL_XFORM_QUSE0 0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EMC_DLL_XFORM_QUSE1 0x34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EMC_DLL_XFORM_QUSE2 0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EMC_DLL_XFORM_QUSE3 0x354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EMC_DLL_XFORM_QUSE4 0x358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EMC_DLL_XFORM_QUSE5 0x35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EMC_DLL_XFORM_QUSE6 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EMC_DLL_XFORM_QUSE7 0x364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EMC_DLL_XFORM_DQ0 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EMC_DLL_XFORM_DQ1 0x36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EMC_DLL_XFORM_DQ2 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EMC_DLL_XFORM_DQ3 0x374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EMC_DLI_TRIM_TXDQS0 0x3a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EMC_DLI_TRIM_TXDQS1 0x3ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EMC_DLI_TRIM_TXDQS2 0x3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EMC_DLI_TRIM_TXDQS3 0x3b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EMC_DLI_TRIM_TXDQS4 0x3b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EMC_DLI_TRIM_TXDQS5 0x3bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EMC_DLI_TRIM_TXDQS6 0x3c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EMC_DLI_TRIM_TXDQS7 0x3c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EMC_SEL_DPD_CTRL 0x3d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EMC_DYN_SELF_REF_CONTROL 0x3e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EMC_TXSRDLL 0x3e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EMC_MODE_SET_DLL_RESET BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EMC_MODE_SET_LONG_CNT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EMC_SELF_REF_CMD_ENABLED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DRAM_DEV_SEL_ALL (0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DRAM_DEV_SEL_0 BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DRAM_DEV_SEL_1 BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DRAM_BROADCAST(num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EMC_ZQ_CAL_CMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EMC_ZQ_CAL_LONG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EMC_ZQ_CAL_LONG_CMD_DEV0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EMC_ZQ_CAL_LONG_CMD_DEV1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EMC_DBG_FORCE_UPDATE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EMC_DBG_CFG_PRIORITY BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EMC_CFG5_QUSE_MODE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define EMC_CFG5_QUSE_MODE_MASK (7 << EMC_CFG5_QUSE_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EMC_CFG5_QUSE_MODE_INTERNAL_LPBK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EMC_CFG5_QUSE_MODE_PULSE_INTERN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EMC_XM2DQSPADCTRL3_VREF_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (0x3ff << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EMC_REFCTRL_DEV_SEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EMC_REFCTRL_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EMC_REFCTRL_ENABLE_ALL(num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define EMC_CFG_PERIODIC_QRST BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define EMC_CFG_DYN_SREF_ENABLE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EMC_CLKCHANGE_SR_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EMC_TIMING_UPDATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EMC_REFRESH_OVERFLOW_INT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) enum emc_dram_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DRAM_TYPE_DDR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DRAM_TYPE_DDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DRAM_TYPE_LPDDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DRAM_TYPE_DDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum emc_dll_change {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DLL_CHANGE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DLL_CHANGE_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DLL_CHANGE_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const u16 emc_timing_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [0] = EMC_RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [1] = EMC_RFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [2] = EMC_RAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [3] = EMC_RP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [4] = EMC_R2W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [5] = EMC_W2R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [6] = EMC_R2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [7] = EMC_W2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [8] = EMC_RD_RCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [9] = EMC_WR_RCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [10] = EMC_RRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [11] = EMC_REXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [12] = EMC_WEXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [13] = EMC_WDV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [14] = EMC_QUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [15] = EMC_QRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [16] = EMC_QSAFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [17] = EMC_RDV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [18] = EMC_REFRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [19] = EMC_BURST_REFRESH_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [20] = EMC_PRE_REFRESH_REQ_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [21] = EMC_PDEX2WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [22] = EMC_PDEX2RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [23] = EMC_PCHG2PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [24] = EMC_ACT2PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [25] = EMC_AR2PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [26] = EMC_RW2PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [27] = EMC_TXSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [28] = EMC_TXSRDLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [29] = EMC_TCKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [30] = EMC_TFAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [31] = EMC_TRPAB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [32] = EMC_TCLKSTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [33] = EMC_TCLKSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [34] = EMC_TREFBW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [35] = EMC_QUSE_EXTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [36] = EMC_FBIO_CFG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [37] = EMC_ODT_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [38] = EMC_ODT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [39] = EMC_FBIO_CFG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [40] = EMC_CFG_DIG_DLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [41] = EMC_CFG_DIG_DLL_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [42] = EMC_DLL_XFORM_DQS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [43] = EMC_DLL_XFORM_DQS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [44] = EMC_DLL_XFORM_DQS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) [45] = EMC_DLL_XFORM_DQS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [46] = EMC_DLL_XFORM_DQS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [47] = EMC_DLL_XFORM_DQS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [48] = EMC_DLL_XFORM_DQS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [49] = EMC_DLL_XFORM_DQS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [50] = EMC_DLL_XFORM_QUSE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [51] = EMC_DLL_XFORM_QUSE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [52] = EMC_DLL_XFORM_QUSE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [53] = EMC_DLL_XFORM_QUSE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [54] = EMC_DLL_XFORM_QUSE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [55] = EMC_DLL_XFORM_QUSE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [56] = EMC_DLL_XFORM_QUSE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [57] = EMC_DLL_XFORM_QUSE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [58] = EMC_DLI_TRIM_TXDQS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [59] = EMC_DLI_TRIM_TXDQS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [60] = EMC_DLI_TRIM_TXDQS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [61] = EMC_DLI_TRIM_TXDQS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [62] = EMC_DLI_TRIM_TXDQS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [63] = EMC_DLI_TRIM_TXDQS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [64] = EMC_DLI_TRIM_TXDQS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [65] = EMC_DLI_TRIM_TXDQS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [66] = EMC_DLL_XFORM_DQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [67] = EMC_DLL_XFORM_DQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [68] = EMC_DLL_XFORM_DQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [69] = EMC_DLL_XFORM_DQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [70] = EMC_XM2CMDPADCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [71] = EMC_XM2DQSPADCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [72] = EMC_XM2DQPADCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [73] = EMC_XM2CLKPADCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [74] = EMC_XM2COMPPADCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [75] = EMC_XM2VTTGENPADCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [76] = EMC_XM2VTTGENPADCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [77] = EMC_XM2QUSEPADCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [78] = EMC_XM2DQSPADCTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [79] = EMC_CTT_TERM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [80] = EMC_ZCAL_INTERVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [81] = EMC_ZCAL_WAIT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [82] = EMC_MRS_WAIT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [83] = EMC_AUTO_CAL_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [84] = EMC_CTT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [85] = EMC_CTT_DURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [86] = EMC_DYN_SELF_REF_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [87] = EMC_FBIO_SPARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [88] = EMC_CFG_RSV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct emc_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 data[ARRAY_SIZE(emc_timing_registers)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 emc_auto_cal_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 emc_mode_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 emc_mode_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 emc_mode_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 emc_zcal_cnt_long;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) bool emc_cfg_periodic_qrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bool emc_cfg_dyn_self_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct tegra_emc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct tegra_mc *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct notifier_block clk_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bool bad_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct emc_timing *new_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct emc_timing *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 mc_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 emc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 emc_mode_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 emc_mode_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 emc_mode_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bool vref_cal_toggle : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bool zcal_long : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bool dll_on : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned long min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int emc_seq_update_timing(struct tegra_emc *emc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) !(val & EMC_STATUS_TIMING_UPDATE_STALLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 1, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_err(emc->dev, "failed to update timing: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static irqreturn_t tegra_emc_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 intmask = EMC_REFRESH_OVERFLOW_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* notify about HW problem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (status & EMC_REFRESH_OVERFLOW_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err_ratelimited(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "refresh request overflow timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel_relaxed(status, emc->regs + EMC_INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct emc_timing *emc_find_timing(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct emc_timing *timing = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) for (i = 0; i < emc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (emc->timings[i].rate >= rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) timing = &emc->timings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(emc->dev, "no timing for rate %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) bool *schmitt_to_vref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bool preset = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) preset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!(val & EMC_XM2DQSPADCTRL3_VREF_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val |= EMC_XM2DQSPADCTRL3_VREF_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) preset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!(val & EMC_XM2QUSEPADCTRL_IVREF_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) val |= EMC_XM2QUSEPADCTRL_IVREF_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) *schmitt_to_vref = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) preset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return preset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct tegra_mc *mc = emc->mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int misc0_index = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bool same;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) for (i = 0; i < mc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (mc->timings[i].rate != rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (mc->timings[i].emem_data[misc0_index] & BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) same = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) same = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct emc_timing *timing = emc_find_timing(emc, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enum emc_dll_change dll_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) enum emc_dram_type dram_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) bool schmitt_to_vref = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned int pre_wait = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bool qrst_used = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int dram_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 fbio_cfg5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 emc_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!timing || emc->bad_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __func__, timing->rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) emc->bad_state = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) err = emc_prepare_mc_clk_cfg(emc, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(emc->dev, "mc clock preparation failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) emc->vref_cal_toggle = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dll_change = DLL_CHANGE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) else if (timing->emc_mode_1 & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dll_change = DLL_CHANGE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dll_change = DLL_CHANGE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) emc->dll_on = !!(timing->emc_mode_1 & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) emc->zcal_long = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) emc->zcal_long = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dram_num = tegra_mc_get_emem_device_count(emc->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* disable dynamic self-refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pre_wait = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* update MC arbiter settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!(val & MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ((val & MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK) > 0x50)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val = MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE | 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mc_writel(emc->mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MC_EMEM_ARB_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* check DQ/DQS VREF delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (pre_wait < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pre_wait = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (pre_wait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err = emc_seq_update_timing(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) udelay(pre_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* disable auto-calibration if VREF mode is switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (timing->emc_auto_cal_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val ^= timing->data[74];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (val & EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) err = readl_relaxed_poll_timeout_atomic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) emc->regs + EMC_AUTO_CAL_STATUS, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) !(val & EMC_AUTO_CAL_STATUS_ACTIVE), 1, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev_err(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) "auto-cal finish timeout: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) emc->vref_cal_toggle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* program shadow registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for (i = 0; i < ARRAY_SIZE(timing->data); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* EMC_XM2CLKPADCTRL should be programmed separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (i != 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) writel_relaxed(timing->data[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) emc->regs + emc_timing_registers[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* DDR3: predict MRS long wait count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 cnt = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (emc->zcal_long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) cnt -= dram_num * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (cnt < val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) cnt = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* this read also completes the writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!(val & EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE) && schmitt_to_vref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 cur_mode, new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) cur_mode = fbio_cfg5 & EMC_CFG5_QUSE_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) cur_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) new_mode >>= EMC_CFG5_QUSE_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if ((cur_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) cur_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) (new_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) new_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) qrst_used = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* flow control marker 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* enable periodic reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (qrst_used) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) emc->regs + EMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* disable auto-refresh to save time after clock change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) writel_relaxed(EMC_REFCTRL_DISABLE_ALL(dram_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) emc->regs + EMC_REFCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* turn off DLL and enter self-refresh on DDR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (dram_type == DRAM_TYPE_DDR3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (dll_change == DLL_CHANGE_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) writel_relaxed(timing->emc_mode_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) emc->regs + EMC_EMRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) writel_relaxed(DRAM_BROADCAST(dram_num) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) EMC_SELF_REF_CMD_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) emc->regs + EMC_SELF_REF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* flow control marker 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* enable write-active MUX, update unshadowed pad control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* restore periodic QRST and disable write-active MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (qrst_used || timing->emc_cfg_periodic_qrst != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (timing->emc_cfg_periodic_qrst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) emc->emc_cfg |= EMC_CFG_PERIODIC_QRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* exit self-refresh on DDR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (dram_type == DRAM_TYPE_DDR3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) writel_relaxed(DRAM_BROADCAST(dram_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) emc->regs + EMC_SELF_REF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* set DRAM-mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (dram_type == DRAM_TYPE_DDR3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (timing->emc_mode_1 != emc->emc_mode_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) writel_relaxed(timing->emc_mode_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) emc->regs + EMC_EMRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (timing->emc_mode_2 != emc->emc_mode_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) writel_relaxed(timing->emc_mode_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) emc->regs + EMC_EMRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (timing->emc_mode_reset != emc->emc_mode_reset ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dll_change == DLL_CHANGE_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) val = timing->emc_mode_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (dll_change == DLL_CHANGE_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) val |= EMC_MODE_SET_DLL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) val |= EMC_MODE_SET_LONG_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) val &= ~EMC_MODE_SET_DLL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) writel_relaxed(val, emc->regs + EMC_MRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (timing->emc_mode_2 != emc->emc_mode_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) writel_relaxed(timing->emc_mode_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) emc->regs + EMC_MRW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (timing->emc_mode_1 != emc->emc_mode_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) writel_relaxed(timing->emc_mode_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) emc->regs + EMC_MRW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) emc->emc_mode_1 = timing->emc_mode_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) emc->emc_mode_2 = timing->emc_mode_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) emc->emc_mode_reset = timing->emc_mode_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* issue ZCAL command if turning ZCAL on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (emc->zcal_long) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) emc->regs + EMC_ZQ_CAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (dram_num > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) emc->regs + EMC_ZQ_CAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* flow control marker 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Read and discard an arbitrary MC register (Note: EMC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * can't be used) to ensure the register writes are completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int emc_complete_timing_change(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct emc_timing *timing = emc_find_timing(emc, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned int dram_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) v & EMC_CLKCHANGE_COMPLETE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* re-enable auto-refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dram_num = tegra_mc_get_emem_device_count(emc->mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) emc->regs + EMC_REFCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* restore auto-calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (emc->vref_cal_toggle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) writel_relaxed(timing->emc_auto_cal_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) emc->regs + EMC_AUTO_CAL_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* restore dynamic self-refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (timing->emc_cfg_dyn_self_ref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* set number of clocks to wait after each ZQ command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (emc->zcal_long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) writel_relaxed(timing->emc_zcal_cnt_long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) emc->regs + EMC_ZCAL_WAIT_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* wait for writes to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* update restored timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) err = emc_seq_update_timing(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) emc->bad_state = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* restore early ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static int emc_unprepare_timing_change(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!emc->bad_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* shouldn't ever happen in practice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(emc->dev, "timing configuration can't be reverted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) emc->bad_state = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int emc_clk_change_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) unsigned long msg, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct clk_notifier_data *cnd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) switch (msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * Disable interrupt since read accesses are prohibited after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * stalling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) disable_irq(emc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) err = emc_prepare_timing_change(emc, cnd->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) enable_irq(emc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case ABORT_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) err = emc_unprepare_timing_change(emc, cnd->old_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) err = emc_complete_timing_change(emc, cnd->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return notifier_from_errno(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int load_one_timing_from_dt(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct emc_timing *timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) err = of_property_read_u32(node, "clock-frequency", &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) node, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) timing->rate = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) err = of_property_read_u32_array(node, "nvidia,emc-configuration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) timing->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ARRAY_SIZE(emc_timing_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_err(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) "timing %pOF: failed to read emc timing data: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) node, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define EMC_READ_BOOL(prop, dtprop) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) timing->prop = of_property_read_bool(node, dtprop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define EMC_READ_U32(prop, dtprop) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) err = of_property_read_u32(node, dtprop, &timing->prop); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (err) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev_err(emc->dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "timing %pOFn: failed to read " #prop ": %d\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) node, err); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return err; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #undef EMC_READ_U32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #undef EMC_READ_BOOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int cmp_timings(const void *_a, const void *_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) const struct emc_timing *a = _a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) const struct emc_timing *b = _b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (a->rate < b->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (a->rate > b->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int emc_check_mc_timings(struct tegra_emc *emc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct tegra_mc *mc = emc->mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (emc->num_timings != mc->num_timings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) emc->num_timings, mc->num_timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for (i = 0; i < mc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (emc->timings[i].rate != mc->timings[i].rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_err(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) "emc/mc timing rate mismatch: %lu %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) emc->timings[i].rate, mc->timings[i].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static int emc_load_timings_from_dt(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct emc_timing *timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int child_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) child_count = of_get_child_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!child_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_err(emc->dev, "no memory timings in: %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (!emc->timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) emc->num_timings = child_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) timing = emc->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) for_each_child_of_node(node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) err = load_one_timing_from_dt(emc, timing++, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) err = emc_check_mc_timings(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev_info(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) emc->num_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) tegra_read_ram_code(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) emc->timings[0].rate / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) emc->timings[emc->num_timings - 1].rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static struct device_node *emc_find_node_by_ram_code(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u32 value, ram_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ram_code = tegra_read_ram_code();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) for_each_child_of_node(dev->of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) err = of_property_read_u32(np, "nvidia,ram-code", &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (err || value != ram_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dev_err(dev, "no memory timings for RAM code %u found in device-tree\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ram_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int emc_setup_hw(struct tegra_emc *emc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u32 intmask = EMC_REFRESH_OVERFLOW_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 fbio_cfg5, emc_cfg, emc_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) enum emc_dram_type dram_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* enable EMC and CAR to handshake on PLL divider/source changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* configure clock change mode accordingly to DRAM type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) switch (dram_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case DRAM_TYPE_LPDDR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) emc_cfg |= EMC_CLKCHANGE_PD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) emc_cfg &= ~EMC_CLKCHANGE_PD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* initialize interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) writel_relaxed(intmask, emc->regs + EMC_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* ensure that unwanted debug features are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) emc_dbg |= EMC_DBG_CFG_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static long emc_round_rate(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) unsigned long min_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) unsigned long max_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct emc_timing *timing = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct tegra_emc *emc = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) for (i = 0; i < emc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (emc->timings[i].rate > max_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) i = max(i, 1u) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (emc->timings[i].rate < min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (emc->timings[i].rate < min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) timing = &emc->timings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) rate, min_rate, max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return timing->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * debugfs interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * The memory controller driver exposes some files in debugfs that can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * to control the EMC frequency. The top-level directory can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * /sys/kernel/debug/emc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * It contains the following files:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * - available_rates: This file contains a list of valid, space-separated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * EMC frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * - min_rate: Writing a value to this file sets the given frequency as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * floor of the permitted range. If this is higher than the currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * configured EMC frequency, this will cause the frequency to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * increased so that it stays within the valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * - max_rate: Similarily to the min_rate file, writing a value to this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * sets the given frequency as the ceiling of the permitted range. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * the value is lower than the currently configured EMC frequency, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * will cause the frequency to be decreased so that it stays within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) for (i = 0; i < emc->num_timings; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (rate == emc->timings[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct tegra_emc *emc = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) const char *prefix = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) for (i = 0; i < emc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) prefix = " ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) seq_puts(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int tegra_emc_debug_available_rates_open(struct inode *inode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return single_open(file, tegra_emc_debug_available_rates_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) inode->i_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const struct file_operations tegra_emc_debug_available_rates_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .open = tegra_emc_debug_available_rates_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .read = seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .llseek = seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .release = single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) *rate = emc->debugfs.min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (!tegra_emc_validate_rate(emc, rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) err = clk_set_min_rate(emc->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) emc->debugfs.min_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) tegra_emc_debug_min_rate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) tegra_emc_debug_min_rate_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) *rate = emc->debugfs.max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!tegra_emc_validate_rate(emc, rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) err = clk_set_max_rate(emc->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) emc->debugfs.max_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) tegra_emc_debug_max_rate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) tegra_emc_debug_max_rate_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static void tegra_emc_debugfs_init(struct tegra_emc *emc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct device *dev = emc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) emc->debugfs.min_rate = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) emc->debugfs.max_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) for (i = 0; i < emc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (emc->timings[i].rate < emc->debugfs.min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) emc->debugfs.min_rate = emc->timings[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (emc->timings[i].rate > emc->debugfs.max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) emc->debugfs.max_rate = emc->timings[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!emc->num_timings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) emc->debugfs.min_rate = clk_get_rate(emc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) emc->debugfs.max_rate = emc->debugfs.min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) emc->debugfs.max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) emc->debugfs.min_rate, emc->debugfs.max_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) emc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) emc->debugfs.root = debugfs_create_dir("emc", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (!emc->debugfs.root) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev_err(emc->dev, "failed to create debugfs directory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) debugfs_create_file("available_rates", 0444, emc->debugfs.root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) emc, &tegra_emc_debug_available_rates_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) debugfs_create_file("min_rate", 0644, emc->debugfs.root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) emc, &tegra_emc_debug_min_rate_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) debugfs_create_file("max_rate", 0644, emc->debugfs.root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) emc, &tegra_emc_debug_max_rate_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int tegra_emc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct platform_device *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct tegra_emc *emc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (of_get_child_count(pdev->dev.of_node) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "device-tree node doesn't have memory timings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_err(&pdev->dev, "could not get memory controller node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) mc = of_find_device_by_node(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (!mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) np = emc_find_node_by_ram_code(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (!emc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) emc->mc = platform_get_drvdata(mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (!emc->mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) emc->clk_nb.notifier_call = emc_clk_change_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) emc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) err = emc_load_timings_from_dt(emc, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) emc->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (IS_ERR(emc->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return PTR_ERR(emc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) err = emc_setup_hw(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) err = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_err(&pdev->dev, "interrupt not specified: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) emc->irq = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_name(&pdev->dev), emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_err(&pdev->dev, "failed to request irq: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) emc->clk = devm_clk_get(&pdev->dev, "emc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (IS_ERR(emc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) err = PTR_ERR(emc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) goto unset_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) err = clk_notifier_register(emc->clk, &emc->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) goto unset_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) platform_set_drvdata(pdev, emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) tegra_emc_debugfs_init(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) unset_cb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) tegra20_clk_set_emc_round_callback(NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int tegra_emc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct tegra_emc *emc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* take exclusive control over the clock's rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) err = clk_rate_exclusive_get(emc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dev_err(emc->dev, "failed to acquire clk: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* suspending in a bad state will hang machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (WARN(emc->bad_state, "hardware in a bad state\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) emc->bad_state = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static int tegra_emc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct tegra_emc *emc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) emc_setup_hw(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) emc->bad_state = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) clk_rate_exclusive_put(emc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static const struct dev_pm_ops tegra_emc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .suspend = tegra_emc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .resume = tegra_emc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static const struct of_device_id tegra_emc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) { .compatible = "nvidia,tegra30-emc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static struct platform_driver tegra_emc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .probe = tegra_emc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .name = "tegra30-emc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .of_match_table = tegra_emc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .pm = &tegra_emc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static int __init tegra_emc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return platform_driver_register(&tegra_emc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) subsys_initcall(tegra_emc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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