Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef TEGRA210_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define TEGRA210_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MC_LATENCY_ALLOWANCE_AVPC_0				0x2e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MC_LATENCY_ALLOWANCE_HC_0				0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MC_LATENCY_ALLOWANCE_HC_1				0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MC_LATENCY_ALLOWANCE_MPCORE_0				0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MC_LATENCY_ALLOWANCE_NVENC_0				0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MC_LATENCY_ALLOWANCE_PPCS_0				0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MC_LATENCY_ALLOWANCE_PPCS_1				0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MC_LATENCY_ALLOWANCE_ISP2_0				0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MC_LATENCY_ALLOWANCE_ISP2_1				0x374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MC_LATENCY_ALLOWANCE_XUSB_0				0x37c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MC_LATENCY_ALLOWANCE_XUSB_1				0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MC_LATENCY_ALLOWANCE_TSEC_0				0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MC_LATENCY_ALLOWANCE_VIC_0				0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MC_LATENCY_ALLOWANCE_VI2_0				0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MC_LATENCY_ALLOWANCE_GPU_0				0x3ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MC_LATENCY_ALLOWANCE_SDMMCA_0				0x3b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MC_LATENCY_ALLOWANCE_SDMMCAA_0				0x3bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MC_LATENCY_ALLOWANCE_SDMMC_0				0x3c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MC_LATENCY_ALLOWANCE_SDMMCAB_0				0x3c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MC_LATENCY_ALLOWANCE_GPU2_0				0x3e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MC_LATENCY_ALLOWANCE_NVDEC_0				0x3d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MC_MLL_MPCORER_PTSA_RATE				0x44c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MC_FTOP_PTSA_RATE					0x50c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MC_EMEM_ARB_TIMING_RFCPB				0x6c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MC_EMEM_ARB_TIMING_CCDMW				0x6c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MC_EMEM_ARB_REFPB_HP_CTRL				0x6f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MC_EMEM_ARB_REFPB_BANK_CTRL				0x6f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MC_PTSA_GRANT_DECREMENT					0x960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MC_EMEM_ARB_DHYST_CTRL					0xbcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0			0xbd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1			0xbd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2			0xbd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3			0xbdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4			0xbe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5			0xbe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6			0xbe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7			0xbec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif