^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef TEGRA210_EMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define TEGRA210_EMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DVFS_FGCG_HIGH_SPEED_THRESHOLD 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IOBRICK_DCC_THRESHOLD 2400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DVFS_FGCG_MID_SPEED_THRESHOLD 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EMC_STATUS_UPDATE_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EMC_INTSTATUS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EMC_DBG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EMC_DBG_WRITE_ACTIVE_ONLY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EMC_CFG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EMC_CFG_DRAM_CLKSTOP_PD BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EMC_CFG_DRAM_CLKSTOP_SR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EMC_CFG_DRAM_ACPD BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EMC_CFG_DYN_SELF_REF BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EMC_PIN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EMC_PIN_PIN_CKE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EMC_PIN_PIN_CKEB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EMC_PIN_PIN_CKE_PER_DEV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EMC_TIMING_CONTROL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EMC_RC 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EMC_RFC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EMC_RAS 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EMC_RP 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EMC_R2W 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EMC_W2R 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EMC_R2P 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EMC_W2P 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EMC_RD_RCD 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EMC_WR_RCD 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EMC_RRD 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EMC_REXT 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EMC_WDV 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EMC_QUSE 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EMC_QRST 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EMC_QSAFE 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EMC_RDV 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EMC_REFRESH 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EMC_BURST_REFRESH_NUM 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EMC_PDEX2WR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EMC_PDEX2RD 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EMC_PCHG2PDEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EMC_ACT2PDEN 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EMC_AR2PDEN 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EMC_RW2PDEN 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EMC_TXSR 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EMC_TCKE 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EMC_TFAW 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EMC_TRPAB 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EMC_TCLKSTABLE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EMC_TCLKSTOP 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EMC_TREFBW 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EMC_TPPD 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EMC_ODT_WRITE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EMC_PDEX2MRR 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EMC_WEXT 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EMC_RFC_SLR 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EMC_MRS_WAIT_CNT2 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EMC_MRS_WAIT_CNT 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EMC_MRS 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EMC_EMRS 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EMC_EMRS_USE_EMRS_LONG_CNT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EMC_REF 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EMC_REF_REF_CMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EMC_SELF_REF 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EMC_MRW 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EMC_MRW_MRW_OP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EMC_MRW_MRW_OP_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (0xff << EMC_MRW_MRW_OP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EMC_MRW_MRW_MA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EMC_MRW_USE_MRW_EXT_CNT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define EMC_MRW_MRW_DEV_SELECTN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EMC_MRR 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EMC_MRR_DEV_SEL_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EMC_MRR_DEV_SEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EMC_MRR_MA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define EMC_MRR_MA_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EMC_MRR_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EMC_MRR_DATA_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EMC_FBIO_SPARE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EMC_FBIO_CFG5 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EMC_FBIO_CFG5_DRAM_TYPE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EMC_FBIO_CFG5_CMD_TX_DIS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EMC_PDEX2CKE 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EMC_CKE2PDEN 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EMC_MPC 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EMC_EMRS2 0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EMC_EMRS2_USE_EMRS2_LONG_CNT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EMC_MRW2 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EMC_MRW3 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EMC_MRW4 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EMC_R2R 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EMC_EINPUT 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EMC_EINPUT_DURATION 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EMC_PUTERM_EXTRA 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EMC_TCKESR 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EMC_TPD 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EMC_AUTO_CAL_CONFIG 0x2a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EMC_EMC_STATUS 0x2b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EMC_EMC_STATUS_MRR_DIVLD BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define EMC_EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EMC_CFG_2 0x2b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EMC_CFG_DIG_DLL 0x2bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EMC_CFG_DIG_DLL_CFG_DLL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EMC_DIG_DLL_STATUS 0x2c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EMC_DIG_DLL_STATUS_DLL_LOCK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EMC_CFG_DIG_DLL_1 0x2c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EMC_RDV_MASK 0x2cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EMC_WDV_MASK 0x2d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EMC_RDV_EARLY_MASK 0x2d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EMC_RDV_EARLY 0x2d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define EMC_AUTO_CAL_CONFIG8 0x2dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EMC_ZCAL_INTERVAL 0x2e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EMC_ZCAL_WAIT_CNT 0x2e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define EMC_ZQ_CAL 0x2ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EMC_ZQ_CAL_DEV_SEL_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define EMC_ZQ_CAL_LONG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EMC_ZQ_CAL_ZQ_LATCH_CMD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EMC_ZQ_CAL_ZQ_CAL_CMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EMC_FDPD_CTRL_DQ 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EMC_FDPD_CTRL_CMD 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EMC_PMACRO_BRICK_CTRL_RFU1 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EMC_PMACRO_BRICK_CTRL_RFU2 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EMC_TR_TIMING_0 0x3b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EMC_TR_CTRL_1 0x3bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EMC_TR_RDV 0x3c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define EMC_SEL_DPD_CTRL 0x3d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define EMC_DYN_SELF_REF_CONTROL 0x3e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define EMC_TXSRDLL 0x3e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define EMC_CCFIFO_ADDR 0x3e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define EMC_CCFIFO_ADDR_STALL_BY_1 (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EMC_CCFIFO_ADDR_STALL(x) (((x) & 0x7fff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EMC_CCFIFO_ADDR_OFFSET(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EMC_CCFIFO_DATA 0x3ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define EMC_TR_QPOP 0x3f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EMC_TR_RDV_MASK 0x3f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EMC_TR_QSAFE 0x3fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EMC_TR_QRST 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EMC_ISSUE_QRST 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define EMC_AUTO_CAL_CONFIG2 0x458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define EMC_AUTO_CAL_CONFIG3 0x45c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EMC_TR_DVFS 0x460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define EMC_AUTO_CAL_CHANNEL 0x464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EMC_IBDLY 0x468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EMC_OBDLY 0x46c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EMC_TXDSRVTTGEN 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EMC_WE_DURATION 0x48c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define EMC_WS_DURATION 0x490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define EMC_WEV 0x494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define EMC_WSV 0x498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define EMC_CFG_3 0x49c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define EMC_MRW6 0x4a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define EMC_MRW7 0x4a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define EMC_MRW8 0x4ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EMC_MRW9 0x4b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EMC_MRW10 0x4b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define EMC_MRW11 0x4b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define EMC_MRW12 0x4bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define EMC_MRW13 0x4c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define EMC_MRW14 0x4c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define EMC_MRW15 0x4d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define EMC_CFG_SYNC 0x4d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define EMC_WDV_CHK 0x4e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define EMC_CFG_PIPE_2 0x554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define EMC_CFG_PIPE_CLK 0x558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define EMC_CFG_PIPE_1 0x55c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define EMC_CFG_PIPE 0x560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define EMC_QPOP 0x564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define EMC_QUSE_WIDTH 0x568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define EMC_PUTERM_WIDTH 0x56c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define EMC_AUTO_CAL_CONFIG7 0x574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define EMC_REFCTRL2 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define EMC_FBIO_CFG7 0x584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define EMC_FBIO_CFG7_CH0_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define EMC_FBIO_CFG7_CH1_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define EMC_DATA_BRLSHFT_0 0x588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define EMC_DATA_BRLSHFT_1 0x58c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define EMC_RFCPB 0x590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define EMC_DQS_BRLSHFT_0 0x594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define EMC_DQS_BRLSHFT_1 0x598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define EMC_CMD_BRLSHFT_0 0x59c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define EMC_CMD_BRLSHFT_1 0x5a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define EMC_CMD_BRLSHFT_2 0x5a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define EMC_CMD_BRLSHFT_3 0x5a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define EMC_QUSE_BRLSHFT_0 0x5ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define EMC_AUTO_CAL_CONFIG4 0x5b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define EMC_AUTO_CAL_CONFIG5 0x5b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define EMC_QUSE_BRLSHFT_1 0x5b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define EMC_QUSE_BRLSHFT_2 0x5bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define EMC_CCDMW 0x5c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define EMC_QUSE_BRLSHFT_3 0x5c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define EMC_AUTO_CAL_CONFIG6 0x5cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define EMC_DLL_CFG_0 0x5e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define EMC_DLL_CFG_1 0x5e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define EMC_CONFIG_SAMPLE_DELAY 0x5f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define EMC_CFG_UPDATE 0x5f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) (0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) (0x3ff << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define EMC_PMACRO_TX_PWRD_0 0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define EMC_PMACRO_TX_PWRD_1 0x724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define EMC_PMACRO_TX_PWRD_2 0x728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define EMC_PMACRO_TX_PWRD_3 0x72c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define EMC_PMACRO_TX_PWRD_4 0x730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define EMC_PMACRO_TX_PWRD_5 0x734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define EMC_PMACRO_DDLL_BYPASS 0x760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define EMC_PMACRO_DDLL_PWRD_0 0x770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define EMC_PMACRO_DDLL_PWRD_1 0x774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define EMC_PMACRO_DDLL_PWRD_2 0x778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define EMC_PMACRO_CMD_CTRL_0 0x780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define EMC_PMACRO_CMD_CTRL_1 0x784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define EMC_PMACRO_CMD_CTRL_2 0x788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define EMC_PMACRO_IB_VREF_DQ_0 0xbe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define EMC_PMACRO_IB_VREF_DQ_1 0xbe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define EMC_PMACRO_IB_VREF_DQS_0 0xbf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define EMC_PMACRO_IB_VREF_DQS_1 0xbf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7 BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define EMC_PMACRO_VTTGEN_CTRL_0 0xc34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define EMC_PMACRO_VTTGEN_CTRL_1 0xc38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define EMC_PMACRO_PAD_CFG_CTRL 0xc40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define EMC_PMACRO_ZCTRL 0xc44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define EMC_PMACRO_IB_RXRT 0xcf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define EMC_PMACRO_TRAINING_CTRL_0 0xcf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define EMC_PMACRO_TRAINING_CTRL_1 0xcfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define EMC_TRAINING_CTRL 0xe04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define EMC_TRAINING_QUSE_FINE_CTRL 0xe10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define EMC_TRAINING_QUSE_CTRL_MISC 0xe14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define EMC_TRAINING_WRITE_FINE_CTRL 0xe18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define EMC_TRAINING_WRITE_VREF_CTRL 0xe20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define EMC_TRAINING_READ_FINE_CTRL 0xe24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define EMC_TRAINING_READ_CTRL_MISC 0xe28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define EMC_TRAINING_READ_VREF_CTRL 0xe2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define EMC_TRAINING_CA_FINE_CTRL 0xe30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define EMC_TRAINING_CA_CTRL_MISC 0xe34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define EMC_TRAINING_CA_CTRL_MISC1 0xe38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define EMC_TRAINING_CA_VREF_CTRL 0xe3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define EMC_TRAINING_SETTLE 0xe44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define EMC_TRAINING_MPC 0xe5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define EMC_TRAINING_VREF_SETTLE 0xe6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define EMC_TRAINING_QUSE_VREF_CTRL 0xed0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define EMC_COPY_TABLE_PARAM_PERIODIC_FIELDS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define EMC_COPY_TABLE_PARAM_TRIM_REGS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) enum burst_regs_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) EMC_RP_INDEX = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) EMC_R2P_INDEX = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) EMC_W2P_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) EMC_MRW6_INDEX = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) EMC_REFRESH_INDEX = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) EMC_PRE_REFRESH_REQ_CNT_INDEX = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) EMC_TRPAB_INDEX = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) EMC_MRW7_INDEX = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) EMC_FBIO_CFG5_INDEX = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) EMC_FBIO_CFG7_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) EMC_CFG_DIG_DLL_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) EMC_ZCAL_INTERVAL_INDEX = 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) EMC_ZCAL_WAIT_CNT_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) EMC_MRS_WAIT_CNT_INDEX = 141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) EMC_DLL_CFG_0_INDEX = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX = 146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) EMC_CFG_INDEX = 148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) EMC_DYN_SELF_REF_CONTROL_INDEX = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX = 161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) EMC_PMACRO_BRICK_CTRL_RFU1_INDEX = 167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) EMC_PMACRO_BG_BIAS_CTRL_0_INDEX = 171,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) EMC_MRW14_INDEX = 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) EMC_MRW15_INDEX = 220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) enum trim_regs_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_INDEX = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) enum burst_mc_regs_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) MC_EMEM_ARB_MISC0_INDEX = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) T_RP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) T_FC_LPDDR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) T_RFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) T_PDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) RL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) AUTO_PD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) MAN_SR = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ASSEMBLY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) C0D0U0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) C0D0U1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) C0D1U0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) C0D1U1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) C1D0U0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) C1D0U1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) C1D1U0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) C1D1U1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) DRAM_CLKTREE_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define VREF_REGS_PER_CHANNEL_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define DRAM_TIMINGS_NUM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define BURST_REGS_PER_CHANNEL_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define TRIM_REGS_PER_CHANNEL_SIZE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define PTFV_ARRAY_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define SAVE_RESTORE_MOD_REGS_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define TRAINING_MOD_REGS_SIZE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define BURST_UP_DOWN_REGS_SIZE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define BURST_MC_REGS_SIZE 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define TRIM_REGS_SIZE 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define BURST_REGS_SIZE 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct tegra210_emc_per_channel_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u16 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u16 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct tegra210_emc_table_register_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u16 burst[BURST_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u16 trim[TRIM_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u16 burst_mc[BURST_MC_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u16 la_scale[BURST_UP_DOWN_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct tegra210_emc_per_channel_regs burst_per_channel[BURST_REGS_PER_CHANNEL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct tegra210_emc_per_channel_regs trim_per_channel[TRIM_REGS_PER_CHANNEL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct tegra210_emc_per_channel_regs vref_per_channel[VREF_REGS_PER_CHANNEL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct tegra210_emc_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) const char dvfs_ver[60];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 min_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u32 gpu_min_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) const char clock_src[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 clk_src_emc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 needs_training;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 training_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 trained;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 periodic_training;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 trained_dram_clktree[DRAM_CLKTREE_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 current_dram_clktree[DRAM_CLKTREE_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 run_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 tree_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 num_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 num_burst_per_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 num_trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u32 num_trim_per_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 num_mc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 num_up_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 vref_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 training_mod_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 dram_timing_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 ptfv_list[PTFV_ARRAY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 burst_regs[BURST_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u32 burst_reg_per_ch[BURST_REGS_PER_CHANNEL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 shadow_regs_ca_train[BURST_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u32 shadow_regs_quse_train[BURST_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u32 shadow_regs_rdwr_train[BURST_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 trim_regs[TRIM_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 trim_perch_regs[TRIM_REGS_PER_CHANNEL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u32 vref_perch_regs[VREF_REGS_PER_CHANNEL_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 dram_timings[DRAM_TIMINGS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 training_mod_regs[TRAINING_MOD_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u32 save_restore_mod_regs[SAVE_RESTORE_MOD_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u32 burst_mc_regs[BURST_MC_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u32 la_scale_regs[BURST_UP_DOWN_REGS_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u32 min_mrs_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 emc_mrw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 emc_mrw2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 emc_mrw3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u32 emc_mrw4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u32 emc_mrw9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u32 emc_mrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 emc_emrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 emc_emrs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 emc_auto_cal_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u32 emc_auto_cal_config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 emc_auto_cal_config3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 emc_auto_cal_config4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u32 emc_auto_cal_config5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 emc_auto_cal_config6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u32 emc_auto_cal_config7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 emc_auto_cal_config8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 emc_cfg_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 emc_sel_dpd_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 emc_fdpd_ctrl_cmd_no_ramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 dll_clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 clk_out_enb_x_0_clk_enb_emc_dll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) enum tegra210_emc_refresh {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) TEGRA210_EMC_REFRESH_NOMINAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) TEGRA210_EMC_REFRESH_2X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) TEGRA210_EMC_REFRESH_4X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) TEGRA210_EMC_REFRESH_THROTTLE, /* 4x Refresh + derating. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define DRAM_TYPE_DDR3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define DRAM_TYPE_LPDDR4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define DRAM_TYPE_LPDDR2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define DRAM_TYPE_DDR2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct tegra210_emc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct tegra_mc *mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* nominal EMC frequency table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct tegra210_emc_timing *nominal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* derated EMC frequency table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct tegra210_emc_timing *derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* currently selected table (nominal or derated) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct tegra210_emc_timing *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) unsigned int num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) const struct tegra210_emc_table_register_offsets *offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) const struct tegra210_emc_sequence *sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) void __iomem *regs, *channel[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) unsigned int num_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) unsigned int dram_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct tegra210_emc_timing *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct tegra210_emc_timing *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned int training_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct timer_list training;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) enum tegra210_emc_refresh refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned int refresh_poll_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct timer_list refresh_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) unsigned int temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) atomic_t refresh_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ktime_t clkchange_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int clkchange_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned long resume_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned long min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) unsigned long max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned int temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) } debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct tegra210_clk_emc_provider provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct tegra210_emc_sequence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 (*periodic_compensation)(struct tegra210_emc *emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static inline void emc_writel(struct tegra210_emc *emc, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) writel_relaxed(value, emc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return readl_relaxed(emc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static inline void emc_channel_writel(struct tegra210_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u32 value, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) writel_relaxed(value, emc->channel[channel] + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static inline u32 emc_channel_readl(struct tegra210_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned int channel, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return readl_relaxed(emc->channel[channel] + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static inline void ccfifo_writel(struct tegra210_emc *emc, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) unsigned int offset, u32 delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) writel_relaxed(value, emc->regs + EMC_CCFIFO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) value = EMC_CCFIFO_ADDR_STALL_BY_1 | EMC_CCFIFO_ADDR_STALL(delay) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) EMC_CCFIFO_ADDR_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) writel_relaxed(value, emc->regs + EMC_CCFIFO_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static inline u32 div_o3(u32 a, u32 b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 result = a / b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if ((b * result) < a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return result + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* from tegra210-emc-r21021.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) extern const struct tegra210_emc_sequence tegra210_emc_r21021;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int tegra210_emc_set_refresh(struct tegra210_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) enum tegra210_emc_refresh refresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned int address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) void tegra210_emc_set_shadow_bypass(struct tegra210_emc *emc, int set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) void tegra210_emc_timing_update(struct tegra210_emc *emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 tegra210_emc_get_dll_state(struct tegra210_emc_timing *next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct tegra210_emc_timing *tegra210_emc_find_timing(struct tegra210_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) void tegra210_emc_adjust_timing(struct tegra210_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct tegra210_emc_timing *timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int tegra210_emc_wait_for_update(struct tegra210_emc *emc, unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned int offset, u32 bit_mask, bool state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) unsigned long tegra210_emc_actual_osc_clocks(u32 in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u32 tegra210_emc_compensate(struct tegra210_emc_timing *next, u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) void tegra210_emc_dll_disable(struct tegra210_emc *emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) void tegra210_emc_dll_enable(struct tegra210_emc *emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u32 tegra210_emc_dvfs_power_ramp_down(struct tegra210_emc *emc, u32 clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) bool flip_backward);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 tegra210_emc_dvfs_power_ramp_up(struct tegra210_emc *emc, u32 clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) bool flip_backward);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) void tegra210_emc_start_periodic_compensation(struct tegra210_emc *emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags