Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <dt-bindings/memory/tegra20-mc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) static const struct tegra_mc_client tegra20_mc_clients[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 		.id = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 		.name = "display0a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 		.id = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 		.name = "display0ab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 		.id = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 		.name = "display0b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		.id = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		.name = "display0bb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		.id = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.name = "display0c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.id = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.name = "display0cb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.id = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.name = "display1b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.id = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.name = "display1bb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.id = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.name = "eppup",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.id = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.name = "g2pr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.id = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.name = "g2sr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.id = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.name = "mpeunifbr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.id = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.name = "viruv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.id = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.name = "avpcarm7r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.id = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.name = "displayhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.id = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.name = "displayhcb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.id = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.name = "fdcdrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.id = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.name = "g2dr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.id = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.name = "host1xdmar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.id = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.name = "host1xr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.id = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.name = "idxsrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.id = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.name = "mpcorer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.id = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.name = "mpe_ipred",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.id = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.name = "mpeamemrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.id = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.name = "mpecsrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.id = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.name = "ppcsahbdmar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.id = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.name = "ppcsahbslvr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.id = 0x1b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.name = "texsrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.id = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.name = "vdebsevr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.id = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.name = "vdember",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.id = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.name = "vdemcer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.id = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.name = "vdetper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.id = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.name = "eppu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.id = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.name = "eppv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.id = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.name = "eppy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.id = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.name = "mpeunifbw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.id = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.name = "viwsb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.id = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.name = "viwu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.id = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.name = "viwv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.id = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.name = "viwy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.id = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.name = "g2dw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.id = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.name = "avpcarm7w",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.id = 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.name = "fdcdwr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.id = 0x2b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.name = "host1xw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.id = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.name = "ispw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.id = 0x2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.name = "mpcorew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.id = 0x2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.name = "mpecswr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.id = 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.name = "ppcsahbdmaw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.id = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.name = "ppcsahbslvw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.id = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.name = "vdebsevw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.id = 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.name = "vdembew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.id = 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.name = "vdetpmw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.name = #_name,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.id = TEGRA20_MC_RESET_##_name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.control = _control,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.status = _status,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.reset = _reset,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.bit = _bit,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct tegra_mc_reset tegra20_mc_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	TEGRA20_MC_RESET(AVPC,   0x100, 0x140, 0x104,  0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	TEGRA20_MC_RESET(DC,     0x100, 0x144, 0x104,  1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	TEGRA20_MC_RESET(DCB,    0x100, 0x148, 0x104,  2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	TEGRA20_MC_RESET(EPP,    0x100, 0x14c, 0x104,  3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	TEGRA20_MC_RESET(2D,     0x100, 0x150, 0x104,  4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	TEGRA20_MC_RESET(HC,     0x100, 0x154, 0x104,  5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	TEGRA20_MC_RESET(ISP,    0x100, 0x158, 0x104,  6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	TEGRA20_MC_RESET(MPCORE, 0x100, 0x15c, 0x104,  7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	TEGRA20_MC_RESET(MPEA,   0x100, 0x160, 0x104,  8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	TEGRA20_MC_RESET(MPEB,   0x100, 0x164, 0x104,  9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	TEGRA20_MC_RESET(MPEC,   0x100, 0x168, 0x104, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	TEGRA20_MC_RESET(3D,     0x100, 0x16c, 0x104, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	TEGRA20_MC_RESET(PPCS,   0x100, 0x170, 0x104, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	TEGRA20_MC_RESET(VDE,    0x100, 0x174, 0x104, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	TEGRA20_MC_RESET(VI,     0x100, 0x178, 0x104, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int tegra20_mc_hotreset_assert(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				      const struct tegra_mc_reset *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	spin_lock_irqsave(&mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	value = mc_readl(mc, rst->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mc_writel(mc, value & ~BIT(rst->bit), rst->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	spin_unlock_irqrestore(&mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 					const struct tegra_mc_reset *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	spin_lock_irqsave(&mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	value = mc_readl(mc, rst->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mc_writel(mc, value | BIT(rst->bit), rst->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	spin_unlock_irqrestore(&mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int tegra20_mc_block_dma(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				const struct tegra_mc_reset *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	spin_lock_irqsave(&mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	mc_writel(mc, value, rst->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	spin_unlock_irqrestore(&mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static bool tegra20_mc_dma_idling(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				  const struct tegra_mc_reset *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return mc_readl(mc, rst->status) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int tegra20_mc_reset_status(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				   const struct tegra_mc_reset *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int tegra20_mc_unblock_dma(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				  const struct tegra_mc_reset *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	spin_lock_irqsave(&mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	value = mc_readl(mc, rst->control) | BIT(rst->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mc_writel(mc, value, rst->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	spin_unlock_irqrestore(&mc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.hotreset_assert = tegra20_mc_hotreset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.hotreset_deassert = tegra20_mc_hotreset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.block_dma = tegra20_mc_block_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.dma_idling = tegra20_mc_dma_idling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.unblock_dma = tegra20_mc_unblock_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.reset_status = tegra20_mc_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const struct tegra_mc_soc tegra20_mc_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.clients = tegra20_mc_clients,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.num_clients = ARRAY_SIZE(tegra20_mc_clients),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.num_address_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.client_id_mask = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		   MC_INT_DECERR_EMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.reset_ops = &tegra20_mc_reset_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.resets = tegra20_mc_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.num_resets = ARRAY_SIZE(tegra20_mc_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };