^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Tegra20 External Memory Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Dmitry Osipenko <digetx@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EMC_INTSTATUS 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EMC_INTMASK 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EMC_DBG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EMC_TIMING_CONTROL 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EMC_RC 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EMC_RFC 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EMC_RAS 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EMC_RP 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EMC_R2W 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EMC_W2R 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EMC_R2P 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EMC_W2P 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EMC_RD_RCD 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EMC_WR_RCD 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EMC_RRD 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EMC_REXT 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EMC_WDV 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EMC_QUSE 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EMC_QRST 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EMC_QSAFE 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EMC_RDV 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EMC_REFRESH 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EMC_BURST_REFRESH_NUM 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EMC_PDEX2WR 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EMC_PDEX2RD 0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EMC_PCHG2PDEN 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EMC_ACT2PDEN 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EMC_AR2PDEN 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EMC_RW2PDEN 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EMC_TXSR 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EMC_TCKE 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EMC_TFAW 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EMC_TRPAB 0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EMC_TCLKSTABLE 0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EMC_TCLKSTOP 0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EMC_TREFBW 0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EMC_QUSE_EXTRA 0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EMC_ODT_WRITE 0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EMC_ODT_READ 0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EMC_FBIO_CFG5 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EMC_FBIO_CFG6 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EMC_AUTO_CAL_INTERVAL 0x2a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EMC_CFG_2 0x2b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EMC_CFG_DIG_DLL 0x2bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EMC_DLL_XFORM_DQS 0x2c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EMC_DLL_XFORM_QUSE 0x2c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EMC_ZCAL_REF_CNT 0x2e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EMC_ZCAL_WAIT_CNT 0x2e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EMC_CFG_CLKTRIM_0 0x2d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EMC_CFG_CLKTRIM_1 0x2d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EMC_CFG_CLKTRIM_2 0x2d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EMC_CLKCHANGE_SR_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EMC_TIMING_UPDATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EMC_REFRESH_OVERFLOW_INT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EMC_DBG_FORCE_UPDATE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EMC_DBG_READ_DQM_CTRL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EMC_DBG_CFG_PRIORITY BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const u16 emc_timing_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) EMC_RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) EMC_RFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) EMC_RAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EMC_RP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) EMC_R2W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) EMC_W2R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) EMC_R2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) EMC_W2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) EMC_RD_RCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) EMC_WR_RCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EMC_RRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) EMC_REXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) EMC_WDV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) EMC_QUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) EMC_QRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) EMC_QSAFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) EMC_RDV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) EMC_REFRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) EMC_BURST_REFRESH_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) EMC_PDEX2WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) EMC_PDEX2RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EMC_PCHG2PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) EMC_ACT2PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) EMC_AR2PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) EMC_RW2PDEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EMC_TXSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EMC_TCKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EMC_TFAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) EMC_TRPAB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EMC_TCLKSTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EMC_TCLKSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EMC_TREFBW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EMC_QUSE_EXTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) EMC_FBIO_CFG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EMC_ODT_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) EMC_ODT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) EMC_FBIO_CFG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) EMC_CFG_DIG_DLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) EMC_DLL_XFORM_DQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) EMC_DLL_XFORM_QUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) EMC_ZCAL_REF_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) EMC_ZCAL_WAIT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) EMC_AUTO_CAL_INTERVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EMC_CFG_CLKTRIM_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) EMC_CFG_CLKTRIM_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) EMC_CFG_CLKTRIM_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct emc_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 data[ARRAY_SIZE(emc_timing_registers)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct tegra_emc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct notifier_block clk_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct emc_timing *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct dentry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static irqreturn_t tegra_emc_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 intmask = EMC_REFRESH_OVERFLOW_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* notify about HW problem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (status & EMC_REFRESH_OVERFLOW_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err_ratelimited(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "refresh request overflow timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel_relaxed(status, emc->regs + EMC_INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct emc_timing *timing = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < emc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (emc->timings[i].rate >= rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) timing = &emc->timings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(emc->dev, "no timing for rate %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __func__, timing->rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* program shadow registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) for (i = 0; i < ARRAY_SIZE(timing->data); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel_relaxed(timing->data[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) emc->regs + emc_timing_registers[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* wait until programming has settled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (flush) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* manually initiate memory timing update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel_relaxed(EMC_TIMING_UPDATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) emc->regs + EMC_TIMING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) v & EMC_CLKCHANGE_COMPLETE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int tegra_emc_clk_change_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long msg, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct clk_notifier_data *cnd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err = emc_prepare_timing_change(emc, cnd->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case ABORT_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err = emc_prepare_timing_change(emc, cnd->old_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) err = emc_complete_timing_change(emc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err = emc_complete_timing_change(emc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return notifier_from_errno(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int load_one_timing_from_dt(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct emc_timing *timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) err = of_property_read_u32(node, "clock-frequency", &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) node, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) err = of_property_read_u32_array(node, "nvidia,emc-registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) timing->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ARRAY_SIZE(emc_timing_registers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "timing %pOF: failed to read emc timing data: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) node, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * The EMC clock rate is twice the bus rate, and the bus rate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * measured in kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) timing->rate = rate * 2 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __func__, node, timing->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int cmp_timings(const void *_a, const void *_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const struct emc_timing *a = _a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) const struct emc_timing *b = _b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (a->rate < b->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (a->rate > b->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct emc_timing *timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int child_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) child_count = of_get_child_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!child_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!emc->timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) emc->num_timings = child_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) timing = emc->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) for_each_child_of_node(node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) err = load_one_timing_from_dt(emc, timing++, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_info(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) emc->num_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tegra_read_ram_code(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) emc->timings[0].rate / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) emc->timings[emc->num_timings - 1].rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct device_node *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) tegra_emc_find_node_by_ram_code(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 value, ram_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return of_node_get(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ram_code = tegra_read_ram_code();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) np = of_find_node_by_name(np, "emc-tables")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) err = of_property_read_u32(np, "nvidia,ram-code", &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (err || value != ram_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ram_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int emc_setup_hw(struct tegra_emc *emc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 intmask = EMC_REFRESH_OVERFLOW_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 emc_cfg, emc_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Depending on a memory type, DRAM should enter either self-refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * or power-down state on EMC clock change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(emc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "bootloader didn't specify DRAM auto-suspend mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* enable EMC and CAR to handshake on PLL divider/source changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* initialize interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writel_relaxed(intmask, emc->regs + EMC_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* ensure that unwanted debug features are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) emc_dbg |= EMC_DBG_CFG_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static long emc_round_rate(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned long min_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned long max_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct emc_timing *timing = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct tegra_emc *emc = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) for (i = 0; i < emc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (emc->timings[i].rate > max_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) i = max(i, 1u) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (emc->timings[i].rate < min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (emc->timings[i].rate < min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) timing = &emc->timings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) rate, min_rate, max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return timing->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * debugfs interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * The memory controller driver exposes some files in debugfs that can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * to control the EMC frequency. The top-level directory can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * /sys/kernel/debug/emc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * It contains the following files:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * - available_rates: This file contains a list of valid, space-separated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * EMC frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * - min_rate: Writing a value to this file sets the given frequency as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * floor of the permitted range. If this is higher than the currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * configured EMC frequency, this will cause the frequency to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * increased so that it stays within the valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * - max_rate: Similarily to the min_rate file, writing a value to this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * sets the given frequency as the ceiling of the permitted range. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * the value is lower than the currently configured EMC frequency, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * will cause the frequency to be decreased so that it stays within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (i = 0; i < emc->num_timings; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (rate == emc->timings[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct tegra_emc *emc = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) const char *prefix = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) for (i = 0; i < emc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) prefix = " ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) seq_puts(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int tegra_emc_debug_available_rates_open(struct inode *inode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return single_open(file, tegra_emc_debug_available_rates_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) inode->i_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct file_operations tegra_emc_debug_available_rates_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .open = tegra_emc_debug_available_rates_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .read = seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .llseek = seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .release = single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) *rate = emc->debugfs.min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!tegra_emc_validate_rate(emc, rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err = clk_set_min_rate(emc->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) emc->debugfs.min_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) tegra_emc_debug_min_rate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) tegra_emc_debug_min_rate_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *rate = emc->debugfs.max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct tegra_emc *emc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!tegra_emc_validate_rate(emc, rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) err = clk_set_max_rate(emc->clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) emc->debugfs.max_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) tegra_emc_debug_max_rate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) tegra_emc_debug_max_rate_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static void tegra_emc_debugfs_init(struct tegra_emc *emc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct device *dev = emc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) emc->debugfs.min_rate = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) emc->debugfs.max_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) for (i = 0; i < emc->num_timings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (emc->timings[i].rate < emc->debugfs.min_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) emc->debugfs.min_rate = emc->timings[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (emc->timings[i].rate > emc->debugfs.max_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) emc->debugfs.max_rate = emc->timings[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!emc->num_timings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) emc->debugfs.min_rate = clk_get_rate(emc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) emc->debugfs.max_rate = emc->debugfs.min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) emc->debugfs.max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) emc->debugfs.min_rate, emc->debugfs.max_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) emc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) emc->debugfs.root = debugfs_create_dir("emc", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!emc->debugfs.root) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_err(emc->dev, "failed to create debugfs directory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) debugfs_create_file("available_rates", 0444, emc->debugfs.root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) emc, &tegra_emc_debug_available_rates_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) debugfs_create_file("min_rate", 0644, emc->debugfs.root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) emc, &tegra_emc_debug_min_rate_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) debugfs_create_file("max_rate", 0644, emc->debugfs.root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) emc, &tegra_emc_debug_max_rate_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int tegra_emc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct tegra_emc *emc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int irq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* driver has nothing to do in a case of memory timing absence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (of_get_child_count(pdev->dev.of_node) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "EMC device tree node doesn't have memory timings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_err(&pdev->dev, "interrupt not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_err(&pdev->dev, "please update your device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) np = tegra_emc_find_node_by_ram_code(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (!emc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) emc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) err = tegra_emc_load_timings_from_dt(emc, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) emc->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (IS_ERR(emc->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return PTR_ERR(emc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) err = emc_setup_hw(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_name(&pdev->dev), emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) emc->clk = devm_clk_get(&pdev->dev, "emc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (IS_ERR(emc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) err = PTR_ERR(emc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) goto unset_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) err = clk_notifier_register(emc->clk, &emc->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) goto unset_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) platform_set_drvdata(pdev, emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) tegra_emc_debugfs_init(emc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unset_cb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) tegra20_clk_set_emc_round_callback(NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const struct of_device_id tegra_emc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { .compatible = "nvidia,tegra20-emc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct platform_driver tegra_emc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .probe = tegra_emc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .name = "tegra20-emc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .of_match_table = tegra_emc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int __init tegra_emc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return platform_driver_register(&tegra_emc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) subsys_initcall(tegra_emc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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