^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/memory/tegra124-mc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "mc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const struct tegra_mc_client tegra124_mc_clients[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .id = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .name = "ptcr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .swgroup = TEGRA_SWGROUP_PTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .id = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .name = "display0a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .swgroup = TEGRA_SWGROUP_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .reg = 0x2e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .def = 0xc2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .id = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = "display0ab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .swgroup = TEGRA_SWGROUP_DCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .reg = 0x2f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .def = 0xc6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .id = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "display0b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .swgroup = TEGRA_SWGROUP_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .reg = 0x2e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .id = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .name = "display0bb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .swgroup = TEGRA_SWGROUP_DCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .reg = 0x2f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .id = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .name = "display0c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .swgroup = TEGRA_SWGROUP_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .reg = 0x2ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .id = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = "display0cb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .swgroup = TEGRA_SWGROUP_DCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .reg = 0x2f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .id = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = "afir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .swgroup = TEGRA_SWGROUP_AFI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .reg = 0x2e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .def = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .id = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = "avpcarm7r",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .swgroup = TEGRA_SWGROUP_AVPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .reg = 0x2e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .def = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .id = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "displayhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .swgroup = TEGRA_SWGROUP_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .reg = 0x2f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .id = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "displayhcb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .swgroup = TEGRA_SWGROUP_DCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .reg = 0x2fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .id = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "hdar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .swgroup = TEGRA_SWGROUP_HDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .reg = 0x318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .def = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .id = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .name = "host1xdmar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .swgroup = TEGRA_SWGROUP_HC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .reg = 0x310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .def = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .id = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "host1xr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .swgroup = TEGRA_SWGROUP_HC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .reg = 0x310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .id = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "msencsrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .swgroup = TEGRA_SWGROUP_MSENC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .reg = 0x328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .def = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .id = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "ppcsahbdmar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .swgroup = TEGRA_SWGROUP_PPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .reg = 0x344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .def = 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .id = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .name = "ppcsahbslvr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .swgroup = TEGRA_SWGROUP_PPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .reg = 0x344,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .def = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .id = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .name = "satar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .swgroup = TEGRA_SWGROUP_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .reg = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .reg = 0x350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .def = 0x65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .id = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "vdebsevr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .swgroup = TEGRA_SWGROUP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .reg = 0x354,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .def = 0x4f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .id = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "vdember",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .swgroup = TEGRA_SWGROUP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .reg = 0x354,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .def = 0x3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .id = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .name = "vdemcer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .swgroup = TEGRA_SWGROUP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .reg = 0x358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .def = 0x66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .id = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "vdetper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .swgroup = TEGRA_SWGROUP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .reg = 0x358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .def = 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .id = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "mpcorelpr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .swgroup = TEGRA_SWGROUP_MPCORELP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .reg = 0x324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .def = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .id = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "mpcorer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .swgroup = TEGRA_SWGROUP_MPCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .reg = 0x320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .def = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .id = 0x2b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "msencswr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .swgroup = TEGRA_SWGROUP_MSENC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .reg = 0x328,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .id = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .name = "afiw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .swgroup = TEGRA_SWGROUP_AFI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .reg = 0x2e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .id = 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = "avpcarm7w",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .swgroup = TEGRA_SWGROUP_AVPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .reg = 0x2e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .id = 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "hdaw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .swgroup = TEGRA_SWGROUP_HDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .reg = 0x318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .id = 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = "host1xw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .swgroup = TEGRA_SWGROUP_HC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .reg = 0x314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .id = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "mpcorelpw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .swgroup = TEGRA_SWGROUP_MPCORELP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .reg = 0x324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .id = 0x39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .name = "mpcorew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .swgroup = TEGRA_SWGROUP_MPCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .reg = 0x320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .id = 0x3b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = "ppcsahbdmaw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .swgroup = TEGRA_SWGROUP_PPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .reg = 0x348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .id = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .name = "ppcsahbslvw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .swgroup = TEGRA_SWGROUP_PPCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .reg = 0x348,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .id = 0x3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .name = "sataw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .swgroup = TEGRA_SWGROUP_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .reg = 0x350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .def = 0x65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .id = 0x3e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .name = "vdebsevw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .swgroup = TEGRA_SWGROUP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .reg = 0x35c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .id = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .name = "vdedbgw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .swgroup = TEGRA_SWGROUP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .reg = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .reg = 0x35c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .id = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .name = "vdembew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .swgroup = TEGRA_SWGROUP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .reg = 0x360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .id = 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .name = "vdetpmw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .swgroup = TEGRA_SWGROUP_VDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .reg = 0x360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .id = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .name = "ispra",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .swgroup = TEGRA_SWGROUP_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .reg = 0x370,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .def = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .id = 0x46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "ispwa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .swgroup = TEGRA_SWGROUP_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .reg = 0x374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .id = 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .name = "ispwb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .swgroup = TEGRA_SWGROUP_ISP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .reg = 0x374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .id = 0x4a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .name = "xusb_hostr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .swgroup = TEGRA_SWGROUP_XUSB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .reg = 0x37c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .def = 0x39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .id = 0x4b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .name = "xusb_hostw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .swgroup = TEGRA_SWGROUP_XUSB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .reg = 0x37c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .id = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .name = "xusb_devr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .swgroup = TEGRA_SWGROUP_XUSB_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .reg = 0x380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .def = 0x39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .id = 0x4d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .name = "xusb_devw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .swgroup = TEGRA_SWGROUP_XUSB_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .reg = 0x380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .id = 0x4e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .name = "isprab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .swgroup = TEGRA_SWGROUP_ISP2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .reg = 0x384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .def = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .id = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .name = "ispwab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .swgroup = TEGRA_SWGROUP_ISP2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .reg = 0x388,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .id = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = "ispwbb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .swgroup = TEGRA_SWGROUP_ISP2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .reg = 0x388,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .id = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .name = "tsecsrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .swgroup = TEGRA_SWGROUP_TSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .reg = 0x390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .def = 0x9b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .id = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .name = "tsecswr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .swgroup = TEGRA_SWGROUP_TSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .reg = 0x390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .id = 0x56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .name = "a9avpscr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .swgroup = TEGRA_SWGROUP_A9AVP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .reg = 0x3a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .def = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .id = 0x57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .name = "a9avpscw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .swgroup = TEGRA_SWGROUP_A9AVP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .reg = 0x3a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .id = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .name = "gpusrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .swgroup = TEGRA_SWGROUP_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .reg = 0x3c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .def = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .id = 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .name = "gpuswr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .swgroup = TEGRA_SWGROUP_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .reg = 0x3c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .id = 0x5a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .name = "displayt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .swgroup = TEGRA_SWGROUP_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .reg = 0x230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .reg = 0x2f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .id = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .name = "sdmmcra",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .swgroup = TEGRA_SWGROUP_SDMMC1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .reg = 0x3b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .def = 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .id = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .name = "sdmmcraa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .swgroup = TEGRA_SWGROUP_SDMMC2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .reg = 0x3bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .def = 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .id = 0x62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .name = "sdmmcr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .swgroup = TEGRA_SWGROUP_SDMMC3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .reg = 0x3c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .def = 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .id = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .swgroup = TEGRA_SWGROUP_SDMMC4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .name = "sdmmcrab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .reg = 0x3c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .def = 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .id = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .name = "sdmmcwa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .swgroup = TEGRA_SWGROUP_SDMMC1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .reg = 0x3b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .id = 0x65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .name = "sdmmcwaa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .swgroup = TEGRA_SWGROUP_SDMMC2A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .reg = 0x3bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .id = 0x66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .name = "sdmmcw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .swgroup = TEGRA_SWGROUP_SDMMC3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .reg = 0x3c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .id = 0x67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .name = "sdmmcwab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .swgroup = TEGRA_SWGROUP_SDMMC4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .reg = 0x3c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .id = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "vicsrd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .swgroup = TEGRA_SWGROUP_VIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .reg = 0x394,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .def = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .id = 0x6d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .name = "vicswr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .swgroup = TEGRA_SWGROUP_VIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .reg = 0x394,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .id = 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "viw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .swgroup = TEGRA_SWGROUP_VI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .reg = 0x398,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .def = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .id = 0x73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .name = "displayd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .swgroup = TEGRA_SWGROUP_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .smmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .reg = 0x234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .la = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .reg = 0x3c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .def = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const unsigned int tegra124_group_drm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) TEGRA_SWGROUP_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) TEGRA_SWGROUP_DCB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) TEGRA_SWGROUP_VIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const struct tegra_smmu_group_soc tegra124_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .name = "drm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .swgroups = tegra124_group_drm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .id = TEGRA124_MC_RESET_##_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .control = _control, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .status = _status, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .bit = _bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const struct tegra_mc_reset tegra124_mc_resets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #ifdef CONFIG_ARCH_TEGRA_124_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const unsigned long tegra124_mc_emem_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) MC_EMEM_ARB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) MC_EMEM_ARB_OUTSTANDING_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) MC_EMEM_ARB_TIMING_RCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) MC_EMEM_ARB_TIMING_RP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) MC_EMEM_ARB_TIMING_RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) MC_EMEM_ARB_TIMING_RAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) MC_EMEM_ARB_TIMING_FAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) MC_EMEM_ARB_TIMING_RRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) MC_EMEM_ARB_TIMING_RAP2PRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) MC_EMEM_ARB_TIMING_WAP2PRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) MC_EMEM_ARB_TIMING_R2R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) MC_EMEM_ARB_TIMING_W2W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) MC_EMEM_ARB_TIMING_R2W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) MC_EMEM_ARB_TIMING_W2R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) MC_EMEM_ARB_DA_TURNS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) MC_EMEM_ARB_DA_COVERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) MC_EMEM_ARB_MISC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) MC_EMEM_ARB_MISC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) MC_EMEM_ARB_RING1_THROTTLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static const struct tegra_smmu_soc tegra124_smmu_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .clients = tegra124_mc_clients,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .num_clients = ARRAY_SIZE(tegra124_mc_clients),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .swgroups = tegra124_swgroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .groups = tegra124_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .num_groups = ARRAY_SIZE(tegra124_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .supports_round_robin_arbitration = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .supports_request_limit = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .num_tlb_lines = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .num_asids = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) const struct tegra_mc_soc tegra124_mc_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .clients = tegra124_mc_clients,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .num_clients = ARRAY_SIZE(tegra124_mc_clients),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .num_address_bits = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .atom_size = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .client_id_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .smmu = &tegra124_smmu_soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .emem_regs = tegra124_mc_emem_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .reset_ops = &tegra_mc_reset_ops_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .resets = tegra124_mc_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .num_resets = ARRAY_SIZE(tegra124_mc_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #endif /* CONFIG_ARCH_TEGRA_124_SOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #ifdef CONFIG_ARCH_TEGRA_132_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const struct tegra_smmu_soc tegra132_smmu_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .clients = tegra124_mc_clients,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .num_clients = ARRAY_SIZE(tegra124_mc_clients),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .swgroups = tegra124_swgroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .groups = tegra124_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .num_groups = ARRAY_SIZE(tegra124_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .supports_round_robin_arbitration = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .supports_request_limit = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .num_tlb_lines = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .num_asids = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) const struct tegra_mc_soc tegra132_mc_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .clients = tegra124_mc_clients,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .num_clients = ARRAY_SIZE(tegra124_mc_clients),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .num_address_bits = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .atom_size = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .client_id_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .smmu = &tegra132_smmu_soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .reset_ops = &tegra_mc_reset_ops_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .resets = tegra124_mc_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .num_resets = ARRAY_SIZE(tegra124_mc_resets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #endif /* CONFIG_ARCH_TEGRA_132_SOC */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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