^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef MEMORY_TEGRA_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define MEMORY_TEGRA_MC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <soc/tegra/mc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MC_INTSTATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MC_INTMASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MC_ERR_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MC_ERR_ADR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MC_GART_ERROR_REQ 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MC_EMEM_ADR_CFG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MC_DECERR_EMEM_OTHERS_STATUS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MC_SECURITY_VIOLATION_STATUS 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MC_EMEM_ARB_CFG 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MC_EMEM_ARB_TIMING_RCD 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MC_EMEM_ARB_TIMING_RP 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MC_EMEM_ARB_TIMING_RC 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MC_EMEM_ARB_TIMING_RAS 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MC_EMEM_ARB_TIMING_FAW 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MC_EMEM_ARB_TIMING_RRD 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MC_EMEM_ARB_TIMING_R2R 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MC_EMEM_ARB_TIMING_W2W 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MC_EMEM_ARB_TIMING_R2W 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MC_EMEM_ARB_TIMING_W2R 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MC_EMEM_ARB_MISC2 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MC_EMEM_ARB_DA_TURNS 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MC_EMEM_ARB_DA_COVERS 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MC_EMEM_ARB_MISC0 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MC_EMEM_ARB_MISC1 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MC_EMEM_ARB_RING1_THROTTLE 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MC_EMEM_ARB_OVERRIDE 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MC_TIMING_CONTROL_DBG 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MC_TIMING_CONTROL 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MC_INT_DECERR_MTS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MC_INT_SECERR_SEC BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MC_INT_DECERR_VPR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MC_INT_INVALID_APB_ASID_UPDATE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MC_INT_INVALID_SMMU_PAGE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MC_INT_ARBITRATION_EMEM BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MC_INT_SECURITY_VIOLATION BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MC_INT_INVALID_GART_PAGE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MC_INT_DECERR_EMEM BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MC_ERR_STATUS_TYPE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MC_ERR_STATUS_TYPE_MASK (0x7 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MC_ERR_STATUS_READABLE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MC_ERR_STATUS_WRITABLE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MC_ERR_STATUS_NONSECURE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MC_ERR_STATUS_ADR_HI_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MC_ERR_STATUS_ADR_HI_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MC_ERR_STATUS_SECURITY BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MC_ERR_STATUS_RW BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MC_TIMING_UPDATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return readl_relaxed(mc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline void mc_writel(struct tegra_mc *mc, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel_relaxed(value, mc->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern const struct tegra_mc_soc tegra20_mc_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern const struct tegra_mc_soc tegra30_mc_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_ARCH_TEGRA_114_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) extern const struct tegra_mc_soc tegra114_mc_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_ARCH_TEGRA_124_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) extern const struct tegra_mc_soc tegra124_mc_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_ARCH_TEGRA_132_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) extern const struct tegra_mc_soc tegra132_mc_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_ARCH_TEGRA_210_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern const struct tegra_mc_soc tegra210_mc_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* MEMORY_TEGRA_MC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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