^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2015 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // http://www.samsung.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Exynos - SROM Controller support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Author: Pankaj Dubey <pankaj.dubey@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "exynos-srom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static const unsigned long exynos_srom_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* SROM side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) EXYNOS_SROM_BW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) EXYNOS_SROM_BC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) EXYNOS_SROM_BC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) EXYNOS_SROM_BC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) EXYNOS_SROM_BC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * struct exynos_srom_reg_dump: register dump of SROM Controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @offset: srom register offset from the controller base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @value: the value of register under the offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct exynos_srom_reg_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * struct exynos_srom: platform data for exynos srom controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @dev: platform device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @reg_base: srom base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct exynos_srom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct exynos_srom_reg_dump *reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct exynos_srom_reg_dump *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) exynos_srom_alloc_reg_dump(const unsigned long *rdump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long nr_rdump)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct exynos_srom_reg_dump *rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) for (i = 0; i < nr_rdump; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) rd[i].offset = rdump[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int exynos_srom_configure_bank(struct exynos_srom *srom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 bank, width, pmc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 timing[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 cs, bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (of_property_read_u32(np, "reg", &bank))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (of_property_read_u32(np, "reg-io-width", &width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) width = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (of_property_read_bool(np, "samsung,srom-page-mode"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pmc = 1 << EXYNOS_SROM_BCX__PMC__SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (of_property_read_u32_array(np, "samsung,srom-timing", timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ARRAY_SIZE(timing)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bank *= 4; /* Convert bank into shift/offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cs = 1 << EXYNOS_SROM_BW__BYTEENABLE__SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (width == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cs |= 1 << EXYNOS_SROM_BW__DATAWIDTH__SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) srom->reg_base + EXYNOS_SROM_BC0 + bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int exynos_srom_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct device_node *np, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct exynos_srom *srom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bool bad_bank_config = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(&pdev->dev, "could not find device info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) srom = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sizeof(struct exynos_srom), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!srom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) srom->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) srom->reg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!srom->reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_err(&pdev->dev, "iomap of exynos srom controller failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) platform_set_drvdata(pdev, srom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ARRAY_SIZE(exynos_srom_offsets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!srom->reg_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) iounmap(srom->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (exynos_srom_configure_bank(srom, child)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "Could not decode bank configuration for %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bad_bank_config = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * If any bank failed to configure, we still provide suspend/resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * but do not probe child devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (bad_bank_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return of_platform_populate(np, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void exynos_srom_save(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct exynos_srom_reg_dump *rd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int num_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) for (; num_regs > 0; --num_regs, ++rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) rd->value = readl(base + rd->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void exynos_srom_restore(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct exynos_srom_reg_dump *rd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int num_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (; num_regs > 0; --num_regs, ++rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel(rd->value, base + rd->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int exynos_srom_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct exynos_srom *srom = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) exynos_srom_save(srom->reg_base, srom->reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ARRAY_SIZE(exynos_srom_offsets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int exynos_srom_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct exynos_srom *srom = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) exynos_srom_restore(srom->reg_base, srom->reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ARRAY_SIZE(exynos_srom_offsets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct of_device_id of_exynos_srom_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .compatible = "samsung,exynos4210-srom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct platform_driver exynos_srom_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .probe = exynos_srom_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .name = "exynos-srom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .of_match_table = of_exynos_srom_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pm = &exynos_srom_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) builtin_platform_driver(exynos_srom_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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