^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas RPC-IF core driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018-2019 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2019 Macronix International Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2019-2020 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <memory/renesas-rpc-if.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RPCIF_CMNCR 0x0000 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RPCIF_CMNCR_MD BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RPCIF_CMNCR_MOIIO1(3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RPCIF_CMNCR_IO3FV(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RPCIF_SSLDR 0x0004 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RPCIF_DRCR 0x000C /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RPCIF_DRCR_SSLN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RPCIF_DRCR_RCF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RPCIF_DRCR_RBE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RPCIF_DRCR_SSLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RPCIF_DRCMR 0x0010 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RPCIF_DREAR 0x0014 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RPCIF_DROPR 0x0018 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RPCIF_DRENR 0x001C /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RPCIF_DRENR_DME BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RPCIF_DRENR_CDE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RPCIF_DRENR_OCDE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RPCIF_SMCR 0x0020 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RPCIF_SMCR_SSLKP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RPCIF_SMCR_SPIRE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RPCIF_SMCR_SPIWE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RPCIF_SMCR_SPIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RPCIF_SMCMR 0x0024 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RPCIF_SMADR 0x0028 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RPCIF_SMOPR 0x002C /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RPCIF_SMENR 0x0030 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RPCIF_SMENR_DME BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RPCIF_SMENR_CDE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RPCIF_SMENR_OCDE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RPCIF_SMRDR0 0x0038 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RPCIF_SMRDR1 0x003C /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RPCIF_SMWDR0 0x0040 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RPCIF_SMWDR1 0x0044 /* W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RPCIF_CMNSR 0x0048 /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RPCIF_CMNSR_SSLF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RPCIF_CMNSR_TEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RPCIF_DRDMCR 0x0058 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RPCIF_DRDRENR 0x005C /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RPCIF_DRDRENR_ADDRE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RPCIF_DRDRENR_OPDRE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RPCIF_DRDRENR_DRDRE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RPCIF_SMDMCR 0x0060 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RPCIF_SMDRENR 0x0064 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RPCIF_SMDRENR_ADDRE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RPCIF_SMDRENR_OPDRE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RPCIF_SMDRENR_SPIDRE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RPCIF_PHYCNT 0x007C /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RPCIF_PHYCNT_CAL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RPCIF_PHYCNT_EXDS BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RPCIF_PHYCNT_OCT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RPCIF_PHYCNT_DDRCAL BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RPCIF_PHYCNT_HS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RPCIF_PHYCNT_WBUF2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RPCIF_PHYCNT_WBUF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RPCIF_PHYOFFSET1 0x0080 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RPCIF_PHYOFFSET2 0x0084 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RPCIF_PHYINT 0x0088 /* R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RPCIF_PHYINT_WPVAL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RPCIF_DIRMAP_SIZE 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct regmap_range rpcif_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct regmap_access_table rpcif_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .yes_ranges = rpcif_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * with proper width. Requires SMENR_SPIDE to be correctly set before!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct rpcif *rpc = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (spide == 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *val = readb(rpc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } else if (spide == 0xC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *val = readw(rpc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } else if (spide != 0xF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *val = readl(rpc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct rpcif *rpc = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (spide == 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writeb(val, rpc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else if (spide == 0xC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) writew(val, rpc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else if (spide != 0xF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel(val, rpc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct regmap_config rpcif_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .reg_read = rpcif_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .reg_write = rpcif_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .max_register = RPCIF_PHYINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .volatile_table = &rpcif_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rpc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rpc->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (IS_ERR(rpc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return PTR_ERR(rpc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (IS_ERR(rpc->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "failed to init regmap for rpcif, error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PTR_ERR(rpc->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return PTR_ERR(rpc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (IS_ERR(rpc->dirmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return PTR_ERR(rpc->dirmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) rpc->size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return PTR_ERR_OR_ZERO(rpc->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EXPORT_SYMBOL(rpcif_sw_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) void rpcif_enable_rpm(struct rpcif *rpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pm_runtime_enable(rpc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EXPORT_SYMBOL(rpcif_enable_rpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void rpcif_disable_rpm(struct rpcif *rpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pm_runtime_disable(rpc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) EXPORT_SYMBOL(rpcif_disable_rpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pm_runtime_get_sync(rpc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * NOTE: The 0x260 are undocumented bits, but they must be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * 0x0 : the delay is biggest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * 0x1 : the delay is 2nd biggest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * On H3 ES1.x, the value should be 0, while on others,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * the value should be 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * NOTE: The 0x1511144 are undocumented bits, but they must be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * for RPCIF_PHYOFFSET1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * The 0x31 are undocumented bits, but they must be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * for RPCIF_PHYOFFSET2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) RPCIF_PHYOFFSET1_DDRTMG(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RPCIF_PHYOFFSET2_OCTTMG(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (hyperflash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) RPCIF_PHYINT_WPVAL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Set RCF after BSZ update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Dummy read according to spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pm_runtime_put(rpc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) rpc->bus_size = hyperflash ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) EXPORT_SYMBOL(rpcif_hw_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int wait_msg_xfer_end(struct rpcif *rpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) sts & RPCIF_CMNSR_TEND, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) USEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (rpc->bus_size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) nbytes /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) nbytes = clamp(nbytes, 1U, 4U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return GENMASK(3, 4 - nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static u8 rpcif_bit_size(u8 buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return buswidth > 4 ? 2 : ilog2(buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) size_t *len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rpc->smcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rpc->smadr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rpc->enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rpc->command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rpc->option = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rpc->dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rpc->ddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rpc->xferlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (op->cmd.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) rpc->enable = RPCIF_SMENR_CDE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (op->cmd.ddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (op->ocmd.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) rpc->enable |= RPCIF_SMENR_OCDE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (op->addr.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rpc->enable |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (op->addr.nbytes == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) rpc->enable |= RPCIF_SMENR_ADE(0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 2, 3 - op->addr.nbytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (op->addr.ddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rpc->ddr |= RPCIF_SMDRENR_ADDRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (offs && len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) rpc->smadr = *offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) rpc->smadr = op->addr.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (op->dummy.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) rpc->enable |= RPCIF_SMENR_DME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) op->dummy.buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (op->option.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rpc->enable |= RPCIF_SMENR_OPDE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) rpcif_bits_set(rpc, op->option.nbytes)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (op->option.ddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rpc->ddr |= RPCIF_SMDRENR_OPDRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) rpc->option = op->option.val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rpc->dir = op->data.dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (op->data.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) rpc->buffer = op->data.buf.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) switch (op->data.dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case RPCIF_DATA_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) rpc->smcr = RPCIF_SMCR_SPIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case RPCIF_DATA_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rpc->smcr = RPCIF_SMCR_SPIWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (op->data.ddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (offs && len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) nbytes = *len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) nbytes = op->data.nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rpc->xferlen = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) EXPORT_SYMBOL(rpcif_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int rpcif_manual_xfer(struct rpcif *rpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pm_runtime_get_sync(rpc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) smenr = rpc->enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) switch (rpc->dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case RPCIF_DATA_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) while (pos < rpc->xferlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 bytes_left = rpc->xferlen - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 nbytes, data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) smcr = rpc->smcr | RPCIF_SMCR_SPIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* nbytes may only be 1, 2, 4, or 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (bytes_left > nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) smcr |= RPCIF_SMCR_SSLKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) memcpy(data, rpc->buffer + pos, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (nbytes == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regmap_write(rpc->regmap, RPCIF_SMWDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regmap_write(rpc->regmap, RPCIF_SMWDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) regmap_write(rpc->regmap, RPCIF_SMWDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = wait_msg_xfer_end(rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pos += nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) smenr = rpc->enable &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case RPCIF_DATA_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * RPC-IF spoils the data for the commands without an address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * phase (like RDID) in the manual mode, so we'll have to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * around this issue by using the external address space read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * mode instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RPCIF_CMNCR_MD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) regmap_write(rpc->regmap, RPCIF_DRCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) regmap_write(rpc->regmap, RPCIF_DREAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) RPCIF_DREAR_EAC(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) regmap_write(rpc->regmap, RPCIF_DRENR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) smenr & ~RPCIF_SMENR_SPIDE(0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Dummy read according to spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) while (pos < rpc->xferlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 bytes_left = rpc->xferlen - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 nbytes, data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* nbytes may only be 1, 2, 4, or 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) regmap_write(rpc->regmap, RPCIF_SMADR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rpc->smadr + pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) smenr &= ~RPCIF_SMENR_SPIDE(0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) regmap_write(rpc->regmap, RPCIF_SMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rpc->smcr | RPCIF_SMCR_SPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = wait_msg_xfer_end(rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (nbytes == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) regmap_read(rpc->regmap, RPCIF_SMRDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) regmap_read(rpc->regmap, RPCIF_SMRDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) regmap_read(rpc->regmap, RPCIF_SMRDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) memcpy(rpc->buffer + pos, data, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pos += nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) regmap_write(rpc->regmap, RPCIF_SMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) rpc->smcr | RPCIF_SMCR_SPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = wait_msg_xfer_end(rpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pm_runtime_put(rpc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (reset_control_reset(rpc->rstc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(rpc->dev, "Failed to reset HW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) rpcif_hw_init(rpc, rpc->bus_size == 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) EXPORT_SYMBOL(rpcif_manual_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) size_t size = RPCIF_DIRMAP_SIZE - from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (len > size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) len = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pm_runtime_get_sync(rpc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) regmap_write(rpc->regmap, RPCIF_DRCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) regmap_write(rpc->regmap, RPCIF_DREAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regmap_write(rpc->regmap, RPCIF_DRENR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) memcpy_fromio(buf, rpc->dirmap + from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pm_runtime_put(rpc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) EXPORT_SYMBOL(rpcif_dirmap_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int rpcif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct platform_device *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct device_node *flash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) flash = of_get_next_child(pdev->dev.of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (!flash) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_warn(&pdev->dev, "no flash node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (of_device_is_compatible(flash, "jedec,spi-nor")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) name = "rpc-if-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } else if (of_device_is_compatible(flash, "cfi-flash")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) name = "rpc-if-hyperflash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) of_node_put(flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_warn(&pdev->dev, "unknown flash type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) of_node_put(flash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) vdev = platform_device_alloc(name, pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!vdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) vdev->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) platform_set_drvdata(pdev, vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return platform_device_add(vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int rpcif_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct platform_device *vdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) platform_device_unregister(vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const struct of_device_id rpcif_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { .compatible = "renesas,rcar-gen3-rpc-if", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MODULE_DEVICE_TABLE(of, rpcif_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct platform_driver rpcif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .probe = rpcif_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .remove = rpcif_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .name = "rpc-if",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .of_match_table = rpcif_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) module_platform_driver(rpcif_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MODULE_DESCRIPTION("Renesas RPC-IF core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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