^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ARM PL353 SMC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 - 2018 Xilinx, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Punnaiah Choudary Kalluri <punnaiah@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pl353-smc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PL353_SMC_MEMC_STATUS_OFFS 0 /* Controller status reg, RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PL353_SMC_CFG_CLR_OFFS 0xC /* Clear config reg, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PL353_SMC_DIRECT_CMD_OFFS 0x10 /* Direct command reg, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PL353_SMC_SET_CYCLES_OFFS 0x14 /* Set cycles register, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PL353_SMC_SET_OPMODE_OFFS 0x18 /* Set opmode register, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PL353_SMC_ECC_STATUS_OFFS 0x400 /* ECC status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PL353_SMC_ECC_MEMCFG_OFFS 0x404 /* ECC mem config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PL353_SMC_ECC_MEMCMD1_OFFS 0x408 /* ECC mem cmd1 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PL353_SMC_ECC_MEMCMD2_OFFS 0x40C /* ECC mem cmd2 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PL353_SMC_ECC_VALUE0_OFFS 0x418 /* ECC value 0 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Controller status register specific constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Clear configuration register specific constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PL353_SMC_CFG_CLR_INT_CLR_1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PL353_SMC_CFG_CLR_ECC_INT_DIS_1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PL353_SMC_CFG_CLR_INT_DIS_1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PL353_SMC_CFG_CLR_DEFAULT_MASK (PL353_SMC_CFG_CLR_INT_CLR_1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PL353_SMC_CFG_CLR_INT_DIS_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Set cycles register specific constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PL353_SMC_SET_CYCLES_T0_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PL353_SMC_SET_CYCLES_T0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PL353_SMC_SET_CYCLES_T1_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PL353_SMC_SET_CYCLES_T1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PL353_SMC_SET_CYCLES_T2_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PL353_SMC_SET_CYCLES_T2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PL353_SMC_SET_CYCLES_T3_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PL353_SMC_SET_CYCLES_T3_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PL353_SMC_SET_CYCLES_T4_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PL353_SMC_SET_CYCLES_T4_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PL353_SMC_SET_CYCLES_T5_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PL353_SMC_SET_CYCLES_T5_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PL353_SMC_SET_CYCLES_T6_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PL353_SMC_SET_CYCLES_T6_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* ECC status register specific constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PL353_SMC_ECC_STATUS_BUSY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PL353_SMC_ECC_REG_SIZE_OFFS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* ECC memory config register specific constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PL353_SMC_ECC_MEMCFG_MODE_MASK 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PL353_SMC_ECC_MEMCFG_MODE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PL353_SMC_DC_UPT_NAND_REGS ((4 << 23) | /* CS: NAND chip */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (2 << 21)) /* UpdateRegs operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PL353_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (0 << 8) | /* Read command */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (0x30 << 16) | /* Read End command */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (1 << 24)) /* Read End command calid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PL353_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (5 << 8) | /* Read col change cmd */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (0xE0 << 16) | /* Read col change end cmd */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (1 << 24)) /* Read col change end cmd valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PL353_NAND_ECC_BUSY_TIMEOUT (1 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * struct pl353_smc_data - Private smc driver structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @memclk: Pointer to the peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @aclk: Pointer to the APER clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pl353_smc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *memclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk *aclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* SMC virtual register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void __iomem *pl353_smc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * pl353_smc_set_buswidth - Set memory buswidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @bw: Memory buswidth (8 | 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Return: 0 on success or negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int pl353_smc_set_buswidth(unsigned int bw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (bw != PL353_SMC_MEM_WIDTH_8 && bw != PL353_SMC_MEM_WIDTH_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PL353_SMC_DIRECT_CMD_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * pl353_smc_set_cycles - Set memory timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @timings: NAND controller timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Sets NAND chip specific timing parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void pl353_smc_set_cycles(u32 timings[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Set write pulse timing. This one is easy to extract:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * NWE_PULSE = tWP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) timings[0] &= PL353_SMC_SET_CYCLES_T0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) timings[1] = (timings[1] & PL353_SMC_SET_CYCLES_T1_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PL353_SMC_SET_CYCLES_T1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) timings[2] = (timings[2] & PL353_SMC_SET_CYCLES_T2_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PL353_SMC_SET_CYCLES_T2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) timings[3] = (timings[3] & PL353_SMC_SET_CYCLES_T3_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PL353_SMC_SET_CYCLES_T3_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) timings[4] = (timings[4] & PL353_SMC_SET_CYCLES_T4_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PL353_SMC_SET_CYCLES_T4_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) timings[5] = (timings[5] & PL353_SMC_SET_CYCLES_T5_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PL353_SMC_SET_CYCLES_T5_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) timings[6] = (timings[6] & PL353_SMC_SET_CYCLES_T6_MASK) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PL353_SMC_SET_CYCLES_T6_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) timings[0] |= timings[1] | timings[2] | timings[3] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) timings[4] | timings[5] | timings[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(timings[0], pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PL353_SMC_DIRECT_CMD_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) EXPORT_SYMBOL_GPL(pl353_smc_set_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * pl353_smc_ecc_is_busy - Read ecc busy flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bool pl353_smc_ecc_is_busy(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ((readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PL353_SMC_ECC_STATUS_BUSY) == PL353_SMC_ECC_STATUS_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * pl353_smc_get_ecc_val - Read ecc_valueN registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @ecc_reg: Index of the ecc_value reg (0..3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Return: the content of the requested ecc_value register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * There are four valid ecc_value registers. The argument is truncated to stay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * within this valid boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 pl353_smc_get_ecc_val(int ecc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 addr, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) addr = PL353_SMC_ECC_VALUE0_OFFS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (ecc_reg * PL353_SMC_ECC_REG_SIZE_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) reg = readl(pl353_smc_base + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Return: the raw_int_status1 bit from the memc_status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int pl353_smc_get_nand_int_status_raw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) reg &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * pl353_smc_clr_nand_int - Clear NAND interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void pl353_smc_clr_nand_int(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(PL353_SMC_CFG_CLR_INT_CLR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * pl353_smc_set_ecc_mode - Set SMC ECC mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @mode: ECC mode (BYPASS, APB, MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Return: 0 on success or negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case PL353_SMC_ECCMODE_BYPASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case PL353_SMC_ECCMODE_APB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case PL353_SMC_ECCMODE_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * pl353_smc_set_ecc_pg_size - Set SMC ECC page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @pg_sz: ECC page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Return: 0 on success or negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int pl353_smc_set_ecc_pg_size(unsigned int pg_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 reg, sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (pg_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case SZ_512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sz = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case SZ_1K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) sz = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case SZ_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sz = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reg |= sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int __maybe_unused pl353_smc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk_disable(pl353_smc->memclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) clk_disable(pl353_smc->aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int __maybe_unused pl353_smc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = clk_enable(pl353_smc->aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(dev, "Cannot enable axi domain clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = clk_enable(pl353_smc->memclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(dev, "Cannot enable memory clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clk_disable(pl353_smc->aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct amba_driver pl353_smc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pl353_smc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * pl353_smc_init_nand_interface - Initialize the NAND interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @adev: Pointer to the amba_device struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @nand_node: Pointer to the pl353_nand device_node struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void pl353_smc_init_nand_interface(struct amba_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct device_node *nand_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(PL353_SMC_CFG_CLR_INT_CLR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PL353_SMC_DIRECT_CMD_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Wait till the ECC operation is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (pl353_smc_ecc_is_busy())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } while (!time_after_eq(jiffies, timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (time_after_eq(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writel(PL353_NAND_ECC_CMD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel(PL353_NAND_ECC_CMD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct of_device_id pl353_smc_supported_children[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .compatible = "cfi-flash"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .compatible = "arm,pl353-nand-r2p1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .data = pl353_smc_init_nand_interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct pl353_smc_data *pl353_smc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct device_node *of_node = adev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void (*init)(struct amba_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct device_node *nand_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) const struct of_device_id *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pl353_smc = devm_kzalloc(&adev->dev, sizeof(*pl353_smc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!pl353_smc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Get the NAND controller virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) res = &adev->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pl353_smc_base = devm_ioremap_resource(&adev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (IS_ERR(pl353_smc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return PTR_ERR(pl353_smc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pl353_smc->aclk = devm_clk_get(&adev->dev, "apb_pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (IS_ERR(pl353_smc->aclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(&adev->dev, "aclk clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return PTR_ERR(pl353_smc->aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pl353_smc->memclk = devm_clk_get(&adev->dev, "memclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (IS_ERR(pl353_smc->memclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(&adev->dev, "memclk clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return PTR_ERR(pl353_smc->memclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) err = clk_prepare_enable(pl353_smc->aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_err(&adev->dev, "Unable to enable AXI clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err = clk_prepare_enable(pl353_smc->memclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(&adev->dev, "Unable to enable memory clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto out_clk_dis_aper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) amba_set_drvdata(adev, pl353_smc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) writel(PL353_SMC_CFG_CLR_DEFAULT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pl353_smc_base + PL353_SMC_CFG_CLR_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Find compatible children. Only a single child is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) for_each_available_child_of_node(of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) match = of_match_node(pl353_smc_supported_children, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_warn(&adev->dev, "unsupported child node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(&adev->dev, "no matching children\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) init = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) init(adev, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) of_platform_device_create(child, NULL, &adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clk_disable_unprepare(pl353_smc->memclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) out_clk_dis_aper:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) clk_disable_unprepare(pl353_smc->aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void pl353_smc_remove(struct amba_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct pl353_smc_data *pl353_smc = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clk_disable_unprepare(pl353_smc->memclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) clk_disable_unprepare(pl353_smc->aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct amba_id pl353_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .id = 0x00041353,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_DEVICE_TABLE(amba, pl353_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct amba_driver pl353_smc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .name = "pl353-smc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .pm = &pl353_smc_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .id_table = pl353_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .probe = pl353_smc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .remove = pl353_smc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) module_amba_driver(pl353_smc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MODULE_AUTHOR("Xilinx, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODULE_DESCRIPTION("ARM PL353 SMC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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