^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Memory controller driver for ARM PrimeCell PL172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * PrimeCell MultiPort Memory Controller (PL172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPMC_STATIC_CFG(n) (0x200 + 0x20 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPMC_STATIC_CFG_MW_8BIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPMC_STATIC_CFG_MW_16BIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPMC_STATIC_CFG_MW_32BIT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPMC_STATIC_CFG_PM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPMC_STATIC_CFG_PC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPMC_STATIC_CFG_PB BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPMC_STATIC_CFG_EW BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPMC_STATIC_CFG_B BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MPMC_STATIC_CFG_P BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPMC_STATIC_WAIT_WEN_MAX 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPMC_STATIC_WAIT_OEN_MAX 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPMC_STATIC_WAIT_RD_MAX 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPMC_STATIC_WAIT_WR_MAX 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPMC_STATIC_WAIT_TURN_MAX 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Maximum number of static chip selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PL172_MAX_CS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pl172_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int pl172_timing_prop(struct amba_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct device_node *np, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 reg_offset, u32 max, int start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct pl172_data *pl172 = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!of_property_read_u32(np, name, &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (cycles < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } else if (cycles > max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dev_err(&adev->dev, "%s timing too tight\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writel(cycles, pl172->base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) readl(pl172->base + reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int pl172_setup_static(struct amba_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct device_node *np, u32 cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct pl172_data *pl172 = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* MPMC static memory configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (cfg == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cfg = MPMC_STATIC_CFG_MW_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } else if (cfg == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cfg = MPMC_STATIC_CFG_MW_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } else if (cfg == 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) cfg = MPMC_STATIC_CFG_MW_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(&adev->dev, "memory-width property required\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (of_property_read_bool(np, "mpmc,async-page-mode"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cfg |= MPMC_STATIC_CFG_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (of_property_read_bool(np, "mpmc,cs-active-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cfg |= MPMC_STATIC_CFG_PC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (of_property_read_bool(np, "mpmc,byte-lane-low"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) cfg |= MPMC_STATIC_CFG_PB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (of_property_read_bool(np, "mpmc,extended-wait"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cfg |= MPMC_STATIC_CFG_EW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (amba_part(adev) == 0x172 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) of_property_read_bool(np, "mpmc,buffer-enable"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cfg |= MPMC_STATIC_CFG_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (of_property_read_bool(np, "mpmc,write-protect"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) cfg |= MPMC_STATIC_CFG_P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* MPMC static memory timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MPMC_STATIC_WAIT_WEN(cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MPMC_STATIC_WAIT_WEN_MAX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MPMC_STATIC_WAIT_OEN(cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MPMC_STATIC_WAIT_OEN_MAX, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MPMC_STATIC_WAIT_RD(cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MPMC_STATIC_WAIT_RD_MAX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MPMC_STATIC_WAIT_PAGE(cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MPMC_STATIC_WAIT_PAGE_MAX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MPMC_STATIC_WAIT_WR(cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MPMC_STATIC_WAIT_WR_MAX, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MPMC_STATIC_WAIT_TURN(cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MPMC_STATIC_WAIT_TURN_MAX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(&adev->dev, "failed to configure cs%u\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int pl172_parse_cs_config(struct amba_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (cs >= PL172_MAX_CS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(&adev->dev, "cs%u invalid\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return pl172_setup_static(adev, np, cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(&adev->dev, "cs property required\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const char * const pl175_revisions[] = {"r1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const char * const pl176_revisions[] = {"r0"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct device_node *child_np, *np = adev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct device *dev = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const char *rev = "?";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct pl172_data *pl172;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (amba_part(adev) == 0x172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rev = pl172_revisions[amba_rev(adev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else if (amba_part(adev) == 0x175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rev = pl175_revisions[amba_rev(adev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else if (amba_part(adev) == 0x176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rev = pl176_revisions[amba_rev(adev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!pl172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pl172->clk = devm_clk_get(dev, "mpmcclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (IS_ERR(pl172->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(dev, "no mpmcclk provided clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return PTR_ERR(pl172->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = clk_prepare_enable(pl172->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(dev, "unable to mpmcclk enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!pl172->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(dev, "unable to get mpmcclk clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto err_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = amba_request_regions(adev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(dev, "unable to request AMBA regions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) goto err_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pl172->base = devm_ioremap(dev, adev->res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) resource_size(&adev->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!pl172->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(dev, "ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) goto err_no_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) amba_set_drvdata(adev, pl172);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Loop through each child node, which represent a chip select, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * configure parameters and timing. If successful; populate devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * under that node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for_each_available_child_of_node(np, child_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = pl172_parse_cs_config(adev, child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) of_platform_populate(child_np, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) err_no_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) amba_release_regions(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk_disable_unprepare(pl172->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void pl172_remove(struct amba_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct pl172_data *pl172 = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) clk_disable_unprepare(pl172->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) amba_release_regions(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct amba_id pl172_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .id = 0x07041172,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .mask = 0x3f0fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .id = 0x07041175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .mask = 0x3f0fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* PrimeCell MPMC PL176 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .id = 0x89041176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .mask = 0xff0fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DEVICE_TABLE(amba, pl172_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct amba_driver pl172_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "memory-pl172",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .probe = pl172_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .remove = pl172_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .id_table = pl172_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) module_amba_driver(pl172_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_DESCRIPTION("PL172 Memory Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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