^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPMC support functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2006 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Juha Yrjola
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2009 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/omap-gpmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/platform_data/mtd-nand-omap2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DEVICE_NAME "omap-gpmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* GPMC register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPMC_REVISION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPMC_SYSCONFIG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPMC_SYSSTATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPMC_IRQSTATUS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPMC_IRQENABLE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPMC_TIMEOUT_CONTROL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPMC_ERR_ADDRESS 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPMC_ERR_TYPE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPMC_CONFIG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPMC_STATUS 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPMC_PREFETCH_CONFIG1 0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPMC_PREFETCH_CONFIG2 0x1e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPMC_PREFETCH_CONTROL 0x1ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPMC_PREFETCH_STATUS 0x1f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPMC_ECC_CONFIG 0x1f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPMC_ECC_CONTROL 0x1f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPMC_ECC_SIZE_CONFIG 0x1fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPMC_ECC1_RESULT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* GPMC ECC control settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPMC_ECC_CTRL_ECCCLEAR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPMC_ECC_CTRL_ECCDISABLE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPMC_ECC_CTRL_ECCREG1 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPMC_ECC_CTRL_ECCREG2 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPMC_ECC_CTRL_ECCREG3 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPMC_ECC_CTRL_ECCREG4 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPMC_ECC_CTRL_ECCREG5 0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GPMC_ECC_CTRL_ECCREG6 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GPMC_ECC_CTRL_ECCREG7 0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GPMC_ECC_CTRL_ECCREG8 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPMC_ECC_CTRL_ECCREG9 0x009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GPMC_CS0_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GPMC_CS_SIZE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GPMC_BCH_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * The first 1MB of GPMC address space is typically mapped to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * the internal ROM. Never allocate the first page, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * facilitate bug detection; even if we didn't boot from ROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * As GPMC minimum partition size is 16MB we can only start from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPMC_MEM_START 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPMC_MEM_END 0x3FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPMC_SECTION_SHIFT 28 /* 128 MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CS_NUM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ENABLE_PREFETCH (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DMA_MPU_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GPMC_REVISION_MINOR(l) ((l) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPMC_HAS_WR_ACCESS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPMC_HAS_MUX_AAD 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GPMC_NR_WAITPINS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GPMC_CS_CONFIG1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GPMC_CS_CONFIG2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GPMC_CS_CONFIG3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GPMC_CS_CONFIG4 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GPMC_CS_CONFIG5 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GPMC_CS_CONFIG6 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GPMC_CS_CONFIG7 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GPMC_CS_NAND_COMMAND 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPMC_CS_NAND_ADDRESS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GPMC_CS_NAND_DATA 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Control Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GPMC_CONFIG_RDY_BSY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GPMC_CONFIG_DEV_SIZE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GPMC_CONFIG_DEV_TYPE 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /** CLKACTIVATIONTIME Max Ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /** ATTACHEDDEVICEPAGELENGTH Max Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /** WAITMONITORINGTIME Max Ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /** DEVICESIZE Max Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GPMC_CONFIG1_DEVICESIZE_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GPMC_CONFIG7_CSVALID (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* All CONFIG7 bits except reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) GPMC_CONFIG7_CSVALID_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) GPMC_CONFIG7_MASKADDRESS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GPMC_DEVICETYPE_NOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GPMC_DEVICETYPE_NAND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GPMC_CONFIG_WRITEPROTECT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define WR_RD_PIN_MONITORING 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* ECC commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum gpmc_clk_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) GPMC_CD_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct gpmc_cs_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GPMC_CS_RESERVED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct resource mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Structure to save gpmc cs context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct gpmc_cs_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 config3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 config4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 config5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 config6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 config7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int is_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Structure to save/restore gpmc context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * to support core off on OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct omap3_gpmc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 sysconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 irqenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 timeout_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 prefetch_config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 prefetch_config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 prefetch_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct gpmc_cs_config cs_context[GPMC_CS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct gpmc_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int nirqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct irq_domain *gpmc_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct resource gpmc_mem_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static DEFINE_SPINLOCK(gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Define chip-selects as reserved by default until probe completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static unsigned int gpmc_cs_num = GPMC_CS_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static unsigned int gpmc_nr_waitpins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static unsigned int gpmc_capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void __iomem *gpmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct clk *gpmc_l3_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static irqreturn_t gpmc_handle_irq(int irq, void *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void gpmc_write_reg(int idx, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel_relaxed(val, gpmc_base + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static u32 gpmc_read_reg(int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return readl_relaxed(gpmc_base + idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void gpmc_cs_write_reg(int cs, int idx, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void __iomem *reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel_relaxed(val, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static u32 gpmc_cs_read_reg(int cs, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem *reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return readl_relaxed(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* TODO: Add support for gpmc_fck to clock framework and use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static unsigned long gpmc_get_fclk_period(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned long rate = clk_get_rate(gpmc_l3_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rate /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rate = 1000000000 / rate; /* In picoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * gpmc_get_clk_period - get period of selected clock domain in ps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @cs: Chip Select Region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @cd: Clock Domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * prior to calling this function with GPMC_CD_CLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long tick_ps = gpmc_get_fclk_period();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) switch (cd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case GPMC_CD_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* get current clk divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) div = (l & 0x03) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* get GPMC_CLK period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tick_ps *= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case GPMC_CD_FCLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return tick_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) enum gpmc_clk_domain cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long tick_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Calculate in picosecs to yield more exact results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) tick_ps = gpmc_get_clk_period(cs, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return (time_ns * 1000 + tick_ps - 1) / tick_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long tick_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Calculate in picosecs to yield more exact results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tick_ps = gpmc_get_fclk_period();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return (time_ps + tick_ps - 1) / tick_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) enum gpmc_clk_domain cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return ticks * gpmc_get_clk_period(cs, cd) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned int gpmc_ticks_to_ns(unsigned int ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ticks * gpmc_get_fclk_period();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned long ticks = gpmc_ps_to_ticks(time_ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ticks * gpmc_get_fclk_period();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) l = gpmc_cs_read_reg(cs, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) l |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) l &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) gpmc_cs_write_reg(cs, reg, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) GPMC_CONFIG1_TIME_PARA_GRAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) p->time_para_granularity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) p->cycle2cyclesamecsen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) p->cycle2cyclediffcsen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #ifdef CONFIG_OMAP_GPMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @cs: Chip Select Region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @reg: GPMC_CS_CONFIGn register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * @st_bit: Start Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * @end_bit: End Bit. Must be >= @st_bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @max: Maximum parameter value (before optional @shift).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * If 0, maximum is as high as @st_bit and @end_bit allow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @name: DTS node name, w/o "gpmc,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * @cd: Clock Domain of timing parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * @shift: Parameter value left shifts @shift, which is then printed instead of value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * @raw: Raw Format Option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * raw format: gpmc,name = <value>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Where x ns -- y ns result in the same tick value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * When @max is exceeded, "invalid" is printed inside comment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * @noval: Parameter values equal to 0 are not printed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * @return: Specified timing parameter (after optional @shift).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int get_gpmc_timing_reg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* timing specifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int cs, int reg, int st_bit, int end_bit, int max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) const char *name, const enum gpmc_clk_domain cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* value transform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* format specifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) bool raw, bool noval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int nr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) bool invalid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) l = gpmc_cs_read_reg(cs, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) nr_bits = end_bit - st_bit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mask = (1 << nr_bits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) l = (l >> st_bit) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) max = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) invalid = l > max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) l = (shift << l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (noval && (l == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!raw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* DTS tick format for timings in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int time_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int time_ns_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (l)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) name, time_ns, time_ns_min, time_ns, l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) invalid ? "; invalid " : " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* raw format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pr_info("gpmc,%s = <%u>;%s\n", name, l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) invalid ? " /* invalid */" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define GPMC_PRINT_CONFIG(cs, config) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pr_info("cs%i %s: 0x%08x\n", cs, #config, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gpmc_cs_read_reg(cs, config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define GPMC_GET_RAW(reg, st, end, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define GPMC_GET_TICKS(reg, st, end, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void gpmc_show_regs(int cs, const char *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pr_info("gpmc cs%i %s:\n", cs, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * see commit c9fb809.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void gpmc_cs_show_timings(int cs, const char *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) gpmc_show_regs(cs, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pr_info("gpmc cs%i access configuration:\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "burst-length");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pr_info("gpmc cs%i timings configuration:\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (gpmc_capability & GPMC_HAS_MUX_AAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "adv-aad-mux-rd-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "adv-aad-mux-wr-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (gpmc_capability & GPMC_HAS_MUX_AAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) "wait-monitoring-ns", GPMC_CD_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "clk-activation-ns", GPMC_CD_FCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static inline void gpmc_cs_show_timings(int cs, const char *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * prior to calling this function with @cd equal to GPMC_CD_CLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * @cs: Chip Select Region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * @reg: GPMC_CS_CONFIGn register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * @st_bit: Start Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * @end_bit: End Bit. Must be >= @st_bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * @max: Maximum parameter value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * If 0, maximum is as high as @st_bit and @end_bit allow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * @time: Timing parameter in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * @cd: Timing parameter clock domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * @name: Timing parameter name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * @return: 0 on success, -1 on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int time, enum gpmc_clk_domain cd, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int ticks, mask, nr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (time == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ticks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) nr_bits = end_bit - st_bit + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mask = (1 << nr_bits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) max = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ticks > max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) __func__, cs, name, time, ticks, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) l = gpmc_cs_read_reg(cs, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #ifdef CONFIG_OMAP_GPMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) (l >> st_bit) & mask, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) l &= ~(mask << st_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) l |= ticks << st_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) gpmc_cs_write_reg(cs, reg, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * read --> don't sample bus too early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * write --> data is longer on bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * / waitmonitoring_ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * div <= 0 check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * @wait_monitoring: WAITMONITORINGTIME in ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * @return: -1 on failure to scale, else proper divider > 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int div = gpmc_ns_to_ticks(wait_monitoring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (div > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (div <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @sync_clk: GPMC_CLK period in ps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Else, returns -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int gpmc_calc_divider(unsigned int sync_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int div = gpmc_ps_to_ticks(sync_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (div > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (div <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * @cs: Chip Select Region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * @t: GPMC timing parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * @s: GPMC timing settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * @return: 0 on success, -1 on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) const struct gpmc_settings *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int div, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) div = gpmc_calc_divider(t->sync_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (div < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * See if we need to change the divider for waitmonitoringtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * pure asynchronous accesses, i.e. both read and write asynchronous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * However, only do so if WAITMONITORINGTIME is actually used, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * either WAITREADMONITORING or WAITWRITEMONITORING is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * This statement must not change div to scale async WAITMONITORINGTIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * to protect mixed synchronous and asynchronous accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * We raise an error later if WAITMONITORINGTIME does not fit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!s->sync_read && !s->sync_write &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) (s->wait_on_read || s->wait_on_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (div < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) t->wait_monitoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) GPMC_CD_FCLK, "cs_on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) GPMC_CD_FCLK, "cs_rd_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) GPMC_CD_FCLK, "cs_wr_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) GPMC_CD_FCLK, "adv_on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GPMC_CD_FCLK, "adv_rd_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) GPMC_CD_FCLK, "adv_wr_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (gpmc_capability & GPMC_HAS_MUX_AAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) t->adv_aad_mux_on, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "adv_aad_mux_on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "adv_aad_mux_rd_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "adv_aad_mux_wr_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GPMC_CD_FCLK, "oe_on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) GPMC_CD_FCLK, "oe_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (gpmc_capability & GPMC_HAS_MUX_AAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) t->oe_aad_mux_on, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "oe_aad_mux_on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) t->oe_aad_mux_off, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "oe_aad_mux_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GPMC_CD_FCLK, "we_on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GPMC_CD_FCLK, "we_off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) GPMC_CD_FCLK, "rd_cycle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) GPMC_CD_FCLK, "wr_cycle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) GPMC_CD_FCLK, "access");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) t->page_burst_access, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "page_burst_access");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) t->bus_turnaround, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "bus_turnaround");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) t->cycle2cycle_delay, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "cycle2cycle_delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) t->wr_data_mux_bus, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "wr_data_mux_bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) t->wr_access, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "wr_access");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) l &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) l |= (div - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) t->wait_monitoring, GPMC_CD_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "wait_monitoring");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) t->clk_activation, GPMC_CD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "clk_activation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #ifdef CONFIG_OMAP_GPMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) cs, (div * gpmc_get_fclk_period()) / 1000, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) gpmc_cs_bool_timings(cs, &t->bool_timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * Ensure that base address is aligned on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * boundary equal to or greater than size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (base & (size - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) base >>= GPMC_CHUNK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) mask = (1 << GPMC_SECTION_SHIFT) - size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) mask >>= GPMC_CHUNK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) l &= ~GPMC_CONFIG7_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) l |= GPMC_CONFIG7_CSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static void gpmc_cs_enable_mem(int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) l |= GPMC_CONFIG7_CSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static void gpmc_cs_disable_mem(int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) l &= ~GPMC_CONFIG7_CSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) mask = (l >> 8) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int gpmc_cs_mem_enabled(int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return l & GPMC_CONFIG7_CSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static void gpmc_cs_set_reserved(int cs, int reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) gpmc->flags |= GPMC_CS_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static bool gpmc_cs_reserved(int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return gpmc->flags & GPMC_CS_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static unsigned long gpmc_mem_align(unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) order = GPMC_CHUNK_SHIFT - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) size >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) order++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } while (size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) size = 1 << order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct resource *res = &gpmc->mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) size = gpmc_mem_align(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spin_lock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) res->start = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) res->end = base + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) r = request_resource(&gpmc_mem_root, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) spin_unlock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int gpmc_cs_delete_mem(int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct resource *res = &gpmc->mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) spin_lock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) r = release_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) res->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) res->end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) spin_unlock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct resource *res = &gpmc->mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int r = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (cs >= gpmc_cs_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) pr_err("%s: requested chip-select is disabled\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) size = gpmc_mem_align(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (size > (1 << GPMC_SECTION_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) spin_lock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (gpmc_cs_reserved(cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) r = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (gpmc_cs_mem_enabled(cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) r = adjust_resource(res, res->start & ~(size - 1), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) size, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Disable CS while changing base address and size mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) gpmc_cs_disable_mem(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (r < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) release_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Enable CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) gpmc_cs_enable_mem(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) *base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) gpmc_cs_set_reserved(cs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) spin_unlock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) EXPORT_SYMBOL(gpmc_cs_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) void gpmc_cs_free(int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct gpmc_cs_data *gpmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) spin_lock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) spin_unlock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) gpmc = &gpmc_cs[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) res = &gpmc->mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) gpmc_cs_disable_mem(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (res->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) release_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) gpmc_cs_set_reserved(cs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) spin_unlock(&gpmc_mem_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) EXPORT_SYMBOL(gpmc_cs_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * gpmc_configure - write request to configure gpmc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * @cmd: command type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * @wval: value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * @return status of the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int gpmc_configure(int cmd, int wval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case GPMC_CONFIG_WP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) regval = gpmc_read_reg(GPMC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (wval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) gpmc_write_reg(GPMC_CONFIG, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) pr_err("%s: command not supported\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) EXPORT_SYMBOL(gpmc_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static bool gpmc_nand_writebuffer_empty(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static struct gpmc_nand_ops nand_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * @reg: the GPMC NAND register map exclusive for NAND use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * @cs: GPMC chip select number on which the NAND sits. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * register map returned will be specific to this chip select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * Returns NULL on error e.g. invalid cs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (cs >= gpmc_cs_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) GPMC_BCH_SIZE * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) GPMC_BCH_SIZE * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) GPMC_BCH_SIZE * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) GPMC_BCH_SIZE * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) i * GPMC_BCH_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) i * GPMC_BCH_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) i * GPMC_BCH_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return &nand_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct gpmc_settings *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int freq, int latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct gpmc_device_timings dev_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) const int t_cer = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) const int t_avdp = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) const int t_cez = 20; /* max of t_cez, t_oez */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) const int t_wpl = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) const int t_wph = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) switch (freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) case 104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) min_gpmc_clk_period = 9600; /* 104 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) t_ces = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) t_avds = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) t_avdh = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) t_ach = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) t_aavdh = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) t_rdyo = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) case 83:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) min_gpmc_clk_period = 12000; /* 83 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) t_ces = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) t_avds = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) t_avdh = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) t_ach = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) t_aavdh = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) t_rdyo = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) case 66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) min_gpmc_clk_period = 15000; /* 66 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) t_ces = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) t_avds = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) t_avdh = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) t_ach = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) t_aavdh = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) t_rdyo = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) min_gpmc_clk_period = 18500; /* 54 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) t_ces = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) t_avds = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) t_avdh = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) t_ach = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) t_aavdh = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) t_rdyo = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* Set synchronous read timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) memset(&dev_t, 0, sizeof(dev_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!s->sync_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dev_t.t_wpl = t_wpl * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dev_t.t_wph = t_wph * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dev_t.t_aavdh = t_aavdh * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dev_t.ce_xdelay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dev_t.avd_xdelay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_t.oe_xdelay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_t.we_xdelay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dev_t.clk = min_gpmc_clk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_t.t_bacc = dev_t.clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dev_t.t_ces = t_ces * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dev_t.t_avds = t_avds * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dev_t.t_avdh = t_avdh * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dev_t.t_ach = t_ach * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) dev_t.cyc_iaa = (latency + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_t.t_cez_r = t_cez * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dev_t.t_cez_w = dev_t.t_cez_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_t.cyc_aavdh_oe = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) gpmc_calc_timings(t, s, &dev_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct gpmc_onenand_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct gpmc_timings gpmc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct gpmc_settings gpmc_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) gpmc_read_settings_dt(dev->of_node, &gpmc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) info->sync_read = gpmc_s.sync_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) info->sync_write = gpmc_s.sync_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) info->burst_len = gpmc_s.burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!gpmc_s.sync_read && !gpmc_s.sync_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret = gpmc_cs_program_settings(cs, &gpmc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) int gpmc_get_client_irq(unsigned int irq_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!gpmc_irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) pr_warn("%s called before GPMC IRQ domain available\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* we restrict this to NAND IRQs only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (irq_config >= GPMC_NR_NAND_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return irq_create_mapping(gpmc_irq_domain, irq_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static int gpmc_irq_endis(unsigned long hwirq, bool endis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (hwirq >= GPMC_NR_NAND_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) hwirq += 8 - GPMC_NR_NAND_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) regval = gpmc_read_reg(GPMC_IRQENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (endis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) regval |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) regval &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) gpmc_write_reg(GPMC_IRQENABLE, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static void gpmc_irq_disable(struct irq_data *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) gpmc_irq_endis(p->hwirq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static void gpmc_irq_enable(struct irq_data *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) gpmc_irq_endis(p->hwirq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static void gpmc_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) gpmc_irq_endis(d->hwirq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static void gpmc_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) gpmc_irq_endis(d->hwirq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* NAND IRQs polarity is not configurable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (hwirq < GPMC_NR_NAND_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* WAITPIN starts at BIT 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) hwirq += 8 - GPMC_NR_NAND_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) regval = gpmc_read_reg(GPMC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (rising_edge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) regval &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) regval |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) gpmc_write_reg(GPMC_CONFIG, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static void gpmc_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) unsigned int hwirq = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* skip reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (hwirq >= GPMC_NR_NAND_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) hwirq += 8 - GPMC_NR_NAND_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* Setting bit to 1 clears (or Acks) the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* can't set type for NAND IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (d->hwirq < GPMC_NR_NAND_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* We can support either rising or falling edge at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (trigger == IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) gpmc_irq_edge_config(d->hwirq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) else if (trigger == IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) gpmc_irq_edge_config(d->hwirq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct gpmc_device *gpmc = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) irq_set_chip_data(virq, gpmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (hw < GPMC_NR_NAND_IRQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) irq_set_chip_and_handler(virq, &gpmc->irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) irq_set_chip_and_handler(virq, &gpmc->irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static const struct irq_domain_ops gpmc_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .map = gpmc_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static irqreturn_t gpmc_handle_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int hwirq, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) u32 regval, regvalx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct gpmc_device *gpmc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) regval = gpmc_read_reg(GPMC_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) regvalx = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (!regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* skip reserved status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (hwirq == GPMC_NR_NAND_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) regvalx >>= 8 - GPMC_NR_NAND_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (regvalx & BIT(hwirq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) virq = irq_find_mapping(gpmc_irq_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (!virq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dev_warn(gpmc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) "spurious irq detected hwirq %d, virq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) hwirq, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) gpmc_write_reg(GPMC_IRQSTATUS, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int gpmc_setup_irq(struct gpmc_device *gpmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) gpmc_write_reg(GPMC_IRQENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) regval = gpmc_read_reg(GPMC_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) gpmc_write_reg(GPMC_IRQSTATUS, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) gpmc->irq_chip.name = "gpmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) gpmc->irq_chip.irq_enable = gpmc_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) gpmc->irq_chip.irq_disable = gpmc_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) gpmc->irq_chip.irq_ack = gpmc_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) gpmc->irq_chip.irq_mask = gpmc_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) gpmc->nirqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) &gpmc_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) gpmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (!gpmc_irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dev_err(gpmc->dev, "IRQ domain add failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) dev_err(gpmc->dev, "failed to request irq %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) gpmc->irq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) irq_domain_remove(gpmc_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) gpmc_irq_domain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static int gpmc_free_irq(struct gpmc_device *gpmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) free_irq(gpmc->irq, gpmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) irq_domain_remove(gpmc_irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) gpmc_irq_domain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static void gpmc_mem_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) for (cs = 0; cs < gpmc_cs_num; cs++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (!gpmc_cs_mem_enabled(cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) gpmc_cs_delete_mem(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static void gpmc_mem_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) gpmc_mem_root.start = GPMC_MEM_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) gpmc_mem_root.end = GPMC_MEM_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /* Reserve all regions that has been set up by bootloader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) for (cs = 0; cs < gpmc_cs_num; cs++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) u32 base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (!gpmc_cs_mem_enabled(cs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) gpmc_cs_get_memconf(cs, &base, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (gpmc_cs_insert_mem(cs, base, size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) __func__, cs, base, base + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) gpmc_cs_disable_mem(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) div = gpmc_calc_divider(sync_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) temp = gpmc_ps_to_ticks(time_ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) temp = (temp + div - 1) / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return gpmc_ticks_to_ps(temp * div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* XXX: can the cycles be avoided ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct gpmc_device_timings *dev_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) bool mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* adv_rd_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) temp = dev_t->t_avdp_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* XXX: mux check required ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* XXX: t_avdp not to be required for sync, only added for tusb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * this indirectly necessitates requirement of t_avdp_r and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * t_avdp_w instead of having a single t_avdp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* oe_on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) temp = dev_t->t_oeasu; /* XXX: remove this ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) temp = max_t(u32, temp, gpmc_t->adv_rd_off +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* XXX: any scope for improvement ?, by combining oe_on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * and clk_activation, need to check whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * access = clk_activation + round to sync clk ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) temp += gpmc_t->clk_activation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (dev_t->cyc_oe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) temp = max_t(u32, temp, gpmc_t->oe_on +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) gpmc_ticks_to_ps(dev_t->cyc_oe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) gpmc_t->access = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) gpmc_t->cs_rd_off = gpmc_t->oe_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* rd_cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) gpmc_t->access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* XXX: barter t_ce_rdyz with t_cez_r ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (dev_t->t_ce_rdyz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct gpmc_device_timings *dev_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) bool mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* adv_wr_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) temp = dev_t->t_avdp_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) temp = max_t(u32, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) gpmc_t->clk_activation + dev_t->t_avdh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* wr_data_mux_bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) temp = max_t(u32, dev_t->t_weasu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) gpmc_t->clk_activation + dev_t->t_rdyo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * and in that case remember to handle we_on properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) temp = max_t(u32, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) gpmc_t->adv_wr_off + dev_t->t_aavdh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) temp = max_t(u32, temp, gpmc_t->adv_wr_off +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* we_on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* wr_access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) gpmc_t->wr_access = gpmc_t->access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* we_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) temp = gpmc_t->we_on + dev_t->t_wpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) temp = max_t(u32, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) gpmc_t->wr_access + gpmc_ticks_to_ps(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) temp = max_t(u32, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) dev_t->t_wph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* wr_cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) temp += gpmc_t->wr_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* XXX: barter t_ce_rdyz with t_cez_w ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (dev_t->t_ce_rdyz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) temp = max_t(u32, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct gpmc_device_timings *dev_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) bool mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* adv_rd_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) temp = dev_t->t_avdp_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* oe_on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) temp = dev_t->t_oeasu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) gpmc_t->oe_on + dev_t->t_oe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) gpmc_t->access = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) gpmc_t->cs_rd_off = gpmc_t->oe_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* rd_cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) temp = max_t(u32, dev_t->t_rd_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) gpmc_t->cs_rd_off + dev_t->t_cez_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct gpmc_device_timings *dev_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) bool mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* adv_wr_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) temp = dev_t->t_avdp_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /* wr_data_mux_bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) temp = dev_t->t_weasu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) temp = max_t(u32, temp, gpmc_t->adv_wr_off +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* we_on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* we_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) temp = gpmc_t->we_on + dev_t->t_wpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) dev_t->t_wph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /* wr_cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) temp = max_t(u32, dev_t->t_wr_cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) gpmc_t->cs_wr_off + dev_t->t_cez_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) struct gpmc_device_timings *dev_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) gpmc_get_fclk_period();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) dev_t->t_bacc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) gpmc_t->sync_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (dev_t->ce_xdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) gpmc_t->bool_timings.cs_extra_delay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (dev_t->avd_xdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) gpmc_t->bool_timings.adv_extra_delay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (dev_t->oe_xdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) gpmc_t->bool_timings.oe_extra_delay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (dev_t->we_xdelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) gpmc_t->bool_timings.we_extra_delay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) struct gpmc_device_timings *dev_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) bool sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* cs_on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* adv_on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) temp = dev_t->t_avdasu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (dev_t->t_ce_avd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) temp = max_t(u32, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) gpmc_t->cs_on + dev_t->t_ce_avd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) gpmc_calc_sync_common_timings(gpmc_t, dev_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) * TODO: remove this function once all peripherals are confirmed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * work with generic timing. Simultaneously gpmc_cs_set_timings()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) * has to be modified to handle timings in ps instead of ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) t->cs_on /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) t->cs_rd_off /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) t->cs_wr_off /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) t->adv_on /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) t->adv_rd_off /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) t->adv_wr_off /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) t->we_on /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) t->we_off /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) t->oe_on /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) t->oe_off /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) t->page_burst_access /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) t->access /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) t->rd_cycle /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) t->wr_cycle /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) t->bus_turnaround /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) t->cycle2cycle_delay /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) t->wait_monitoring /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) t->clk_activation /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) t->wr_access /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) t->wr_data_mux_bus /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct gpmc_settings *gpmc_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct gpmc_device_timings *dev_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) bool mux = false, sync = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (gpmc_s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) mux = gpmc_s->mux_add_data ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) sync = (gpmc_s->sync_read || gpmc_s->sync_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) memset(gpmc_t, 0, sizeof(*gpmc_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) gpmc_calc_common_timings(gpmc_t, dev_t, sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (gpmc_s && gpmc_s->sync_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (gpmc_s && gpmc_s->sync_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /* TODO: remove, see function definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) gpmc_convert_ps_to_ns(gpmc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * gpmc_cs_program_settings - programs non-timing related settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * @cs: GPMC chip-select to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * @p: pointer to GPMC settings structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) * Programs non-timing related settings for a GPMC chip-select, such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) * bus-width, burst configuration, etc. Function should be called once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * for each chip-select that is being used and must be called before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) * register will be initialised to zero by this function. Returns 0 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * success and appropriate negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) u32 config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) pr_err("%s: invalid width %d!", __func__, p->device_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) /* Address-data multiplexing not supported for NAND devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (p->device_nand && p->mux_add_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) pr_err("%s: invalid configuration!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if ((p->mux_add_data > GPMC_MUX_AD) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ((p->mux_add_data == GPMC_MUX_AAD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) pr_err("%s: invalid multiplex configuration!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (p->burst_read || p->burst_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) switch (p->burst_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) case GPMC_BURST_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) case GPMC_BURST_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) case GPMC_BURST_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) pr_err("%s: invalid page/burst-length (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) __func__, p->burst_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (p->wait_pin > gpmc_nr_waitpins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (p->sync_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) config1 |= GPMC_CONFIG1_READTYPE_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (p->sync_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (p->wait_on_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) config1 |= GPMC_CONFIG1_WAIT_READ_MON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (p->wait_on_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (p->wait_on_read || p->wait_on_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (p->device_nand)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (p->mux_add_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (p->burst_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (p->burst_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (p->burst_read || p->burst_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static const struct of_device_id gpmc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) { .compatible = "ti,omap2420-gpmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) { .compatible = "ti,omap2430-gpmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static void gpmc_cs_set_name(int cs, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) gpmc->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static const char *gpmc_cs_get_name(int cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return gpmc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * gpmc_cs_remap - remaps a chip-select physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * @cs: chip-select to remap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * @base: physical base address to re-map chip-select to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * Re-maps a chip-select to a new physical base address specified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * "base". Returns 0 on success and appropriate negative error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) * on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static int gpmc_cs_remap(int cs, u32 base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) u32 old_base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (cs >= gpmc_cs_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) pr_err("%s: requested chip-select is disabled\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * Make sure we ignore any device offsets from the GPMC partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) * allocated for the chip select and that the new base confirms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) * to the GPMC 16MB minimum granularity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) base &= ~(SZ_16M - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) gpmc_cs_get_memconf(cs, &old_base, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (base == old_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ret = gpmc_cs_delete_mem(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ret = gpmc_cs_insert_mem(cs, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ret = gpmc_cs_set_memconf(cs, base, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) * gpmc_read_settings_dt - read gpmc settings from device-tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * @np: pointer to device-tree node for a gpmc child device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) * @p: pointer to gpmc settings structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * Reads the GPMC settings for a GPMC child device from device-tree and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * stores them in the GPMC settings structure passed. The GPMC settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * structure is initialised to zero by this function and so any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * previously stored settings will be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) memset(p, 0, sizeof(struct gpmc_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) of_property_read_u32(np, "gpmc,device-width", &p->device_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (!p->burst_read && !p->burst_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) pr_warn("%s: page/burst-length set but not used!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) p->wait_on_read = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) "gpmc,wait-on-read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) p->wait_on_write = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) "gpmc,wait-on-write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (!p->wait_on_read && !p->wait_on_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) pr_debug("%s: rd/wr wait monitoring not enabled!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) struct gpmc_timings *gpmc_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) struct gpmc_bool_timings *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (!np || !gpmc_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) memset(gpmc_t, 0, sizeof(*gpmc_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) /* minimum clock period for syncronous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* chip select timtings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) /* ADV signal timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) &gpmc_t->adv_aad_mux_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) &gpmc_t->adv_aad_mux_rd_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) &gpmc_t->adv_aad_mux_wr_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* WE signal timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* OE signal timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) &gpmc_t->oe_aad_mux_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) &gpmc_t->oe_aad_mux_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) /* access and cycle timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) of_property_read_u32(np, "gpmc,page-burst-access-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) &gpmc_t->page_burst_access);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) of_property_read_u32(np, "gpmc,bus-turnaround-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) &gpmc_t->bus_turnaround);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) &gpmc_t->cycle2cycle_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) of_property_read_u32(np, "gpmc,wait-monitoring-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) &gpmc_t->wait_monitoring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) of_property_read_u32(np, "gpmc,clk-activation-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) &gpmc_t->clk_activation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) /* only applicable to OMAP3+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) &gpmc_t->wr_data_mux_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /* bool timing parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) p = &gpmc_t->bool_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) p->cycle2cyclediffcsen =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) p->cycle2cyclesamecsen =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) p->time_para_granularity =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) of_property_read_bool(np, "gpmc,time-para-granularity");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) * gpmc_probe_generic_child - configures the gpmc for a child device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) * @pdev: pointer to gpmc platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * @child: pointer to device-tree node for child device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * Allocates and configures a GPMC chip-select for a child device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * Returns 0 on success and appropriate negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) static int gpmc_probe_generic_child(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct device_node *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) struct gpmc_settings gpmc_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct gpmc_timings gpmc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) int ret, cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) struct gpio_desc *waitpin_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) struct gpmc_device *gpmc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (of_property_read_u32(child, "reg", &cs) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (of_address_to_resource(child, 0, &res) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) * Check if we have multiple instances of the same device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) * on a single chip select. If so, use the already initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) * timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) name = gpmc_cs_get_name(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (name && of_node_name_eq(child, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) goto no_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ret = gpmc_cs_request(cs, resource_size(&res), &base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) gpmc_cs_set_name(cs, child->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) gpmc_read_settings_dt(child, &gpmc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) gpmc_read_timings_dt(child, &gpmc_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) * For some GPMC devices we still need to rely on the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) * timings because the devices can be connected via FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * REVISIT: Add timing support from slls644g.pdf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (!gpmc_t.cs_rd_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) gpmc_cs_show_timings(cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) "please add GPMC bootloader timings to .dts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) goto no_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) /* CS must be disabled while making changes to gpmc configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) gpmc_cs_disable_mem(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) * FIXME: gpmc_cs_request() will map the CS to an arbitrary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) * location in the gpmc address space. When booting with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) * device-tree we want the NOR flash to be mapped to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) * location specified in the device-tree blob. So remap the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) * CS to this location. Once DT migration is complete should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) * just make gpmc_cs_request() map a specific address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) ret = gpmc_cs_remap(cs, res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) cs, &res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (res.start < GPMC_MEM_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) "GPMC CS %d start cannot be lesser than 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) cs, GPMC_MEM_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) } else if (res.end > GPMC_MEM_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) "GPMC CS %d end cannot be greater than 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) cs, GPMC_MEM_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (of_node_name_eq(child, "nand")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* Warn about older DT blobs with no compatible property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (!of_property_read_bool(child, "compatible")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) "Incompatible NAND node: missing compatible");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (of_node_name_eq(child, "onenand")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /* Warn about older DT blobs with no compatible property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (!of_property_read_bool(child, "compatible")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) "Incompatible OneNAND node: missing compatible");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (of_device_is_compatible(child, "ti,omap2-nand")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /* NAND specific setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) val = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) of_property_read_u32(child, "nand-bus-width", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) /* disable write protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) gpmc_configure(GPMC_CONFIG_WP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) gpmc_s.device_nand = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ret = of_property_read_u32(child, "bank-width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) &gpmc_s.device_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (ret < 0 && !gpmc_s.device_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) "%pOF has no 'gpmc,device-width' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /* Reserve wait pin if it is required and valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) unsigned int wait_pin = gpmc_s.wait_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) wait_pin, "WAITPIN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) GPIO_ACTIVE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (IS_ERR(waitpin_desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) ret = PTR_ERR(waitpin_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) ret = gpmc_cs_program_settings(cs, &gpmc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) goto err_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) goto err_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* Clear limited address i.e. enable A26-A11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) val = gpmc_read_reg(GPMC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) val &= ~GPMC_CONFIG_LIMITEDADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) gpmc_write_reg(GPMC_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) /* Enable CS region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) gpmc_cs_enable_mem(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) no_timings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) /* create platform device, NULL on error or when disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (!of_platform_device_create(child, NULL, &pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) goto err_child_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) /* is child a common bus? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (of_match_node(of_default_bus_match_table, child))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /* create children and other common bus children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (of_platform_default_populate(child, NULL, &pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) goto err_child_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) err_child_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) err_cs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) gpiochip_free_own_desc(waitpin_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) gpmc_cs_free(cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static int gpmc_probe_dt(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) of_match_device(gpmc_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) &gpmc_cs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) pr_err("%s: number of chip-selects not defined\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) } else if (gpmc_cs_num < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) pr_err("%s: all chip-selects are disabled\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) } else if (gpmc_cs_num > GPMC_CS_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) pr_err("%s: number of supported chip-selects cannot be > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) __func__, GPMC_CS_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) &gpmc_nr_waitpins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) pr_err("%s: number of wait pins not found!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static void gpmc_probe_dt_children(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) for_each_available_child_of_node(pdev->dev.of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) ret = gpmc_probe_generic_child(pdev, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) child, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) memset(p, 0, sizeof(*p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) static int gpmc_probe_dt(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static void gpmc_probe_dt_children(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return 1; /* we're input only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static int gpmc_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) return 0; /* we're input only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) static int gpmc_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) return -EINVAL; /* we're input only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) offset += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) return !!reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static int gpmc_gpio_init(struct gpmc_device *gpmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) gpmc->gpio_chip.parent = gpmc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) gpmc->gpio_chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) gpmc->gpio_chip.label = DEVICE_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) gpmc->gpio_chip.set = gpmc_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) gpmc->gpio_chip.get = gpmc_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) gpmc->gpio_chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) static int gpmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) struct gpmc_device *gpmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (!gpmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) gpmc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) platform_set_drvdata(pdev, gpmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) gpmc_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if (IS_ERR(gpmc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) return PTR_ERR(gpmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) dev_err(&pdev->dev, "Failed to get resource: irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) gpmc->irq = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (IS_ERR(gpmc_l3_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) dev_err(&pdev->dev, "Failed to get GPMC fck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) return PTR_ERR(gpmc_l3_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) if (!clk_get_rate(gpmc_l3_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) rc = gpmc_probe_dt(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) gpmc_cs_num = GPMC_CS_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) gpmc_nr_waitpins = GPMC_NR_WAITPINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) l = gpmc_read_reg(GPMC_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) * FIXME: Once device-tree migration is complete the below flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) * should be populated based upon the device-tree compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) * string. For now just use the IP revision. OMAP3+ devices have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * the wr_access and wr_data_mux_bus register fields. OMAP4+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * devices support the addr-addr-data multiplex protocol.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) * GPMC IP revisions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) * - OMAP24xx = 2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) * - OMAP3xxx = 5.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) * - OMAP44xx/54xx/AM335x = 6.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if (GPMC_REVISION_MAJOR(l) > 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (GPMC_REVISION_MAJOR(l) > 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) gpmc_capability |= GPMC_HAS_MUX_AAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) GPMC_REVISION_MINOR(l));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) gpmc_mem_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) rc = gpmc_gpio_init(gpmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) goto gpio_init_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) rc = gpmc_setup_irq(gpmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) goto gpio_init_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) gpmc_probe_dt_children(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) gpio_init_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) gpmc_mem_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) static int gpmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) struct gpmc_device *gpmc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) gpmc_free_irq(gpmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) gpmc_mem_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) static int gpmc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) omap3_gpmc_save_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) static int gpmc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) omap3_gpmc_restore_context();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static struct platform_driver gpmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .probe = gpmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .remove = gpmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .name = DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .of_match_table = of_match_ptr(gpmc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .pm = &gpmc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) static __init int gpmc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) return platform_driver_register(&gpmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) postcore_initcall(gpmc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) static struct omap3_gpmc_regs gpmc_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) void omap3_gpmc_save_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) if (!gpmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) for (i = 0; i < gpmc_cs_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if (gpmc_context.cs_context[i].is_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) gpmc_context.cs_context[i].config1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) gpmc_context.cs_context[i].config2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) gpmc_context.cs_context[i].config3 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) gpmc_context.cs_context[i].config4 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) gpmc_context.cs_context[i].config5 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) gpmc_context.cs_context[i].config6 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) gpmc_context.cs_context[i].config7 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) void omap3_gpmc_restore_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) if (!gpmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) for (i = 0; i < gpmc_cs_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (gpmc_context.cs_context[i].is_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) gpmc_context.cs_context[i].config1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) gpmc_context.cs_context[i].config2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) gpmc_context.cs_context[i].config3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) gpmc_context.cs_context[i].config4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) gpmc_context.cs_context[i].config5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) gpmc_context.cs_context[i].config6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) gpmc_context.cs_context[i].config7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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