^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell EBU SoC Device Bus Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (memory controller for NOR/NAND/SRAM/FPGA devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013-2014 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ARMADA_DEV_WIDTH_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ARMADA_BADR_SKEW_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARMADA_RD_HOLD_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ARMADA_ACC_NEXT_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ARMADA_RD_SETUP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ARMADA_ACC_FIRST_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ARMADA_SYNC_ENABLE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ARMADA_WR_HIGH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ARMADA_WR_LOW_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ARMADA_READ_PARAM_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ARMADA_WRITE_PARAM_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ORION_RESERVED (0x2 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ORION_BADR_SKEW_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ORION_WR_HIGH_EXT_BIT BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ORION_WR_HIGH_EXT_MASK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ORION_WR_LOW_EXT_BIT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ORION_WR_LOW_EXT_MASK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ORION_ALE_WR_EXT_BIT BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ORION_ALE_WR_EXT_MASK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ORION_ACC_NEXT_EXT_BIT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ORION_ACC_NEXT_EXT_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ORION_ACC_FIRST_EXT_BIT BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ORION_ACC_FIRST_EXT_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ORION_TURN_OFF_EXT_BIT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ORION_TURN_OFF_EXT_MASK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ORION_DEV_WIDTH_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ORION_WR_HIGH_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ORION_WR_HIGH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ORION_WR_LOW_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ORION_WR_LOW_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ORION_ALE_WR_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ORION_ALE_WR_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ORION_ACC_NEXT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ORION_ACC_NEXT_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ORION_ACC_FIRST_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ORION_ACC_FIRST_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ORION_TURN_OFF_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ORION_TURN_OFF_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct devbus_read_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 badr_skew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 turn_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 acc_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 acc_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 rd_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 rd_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct devbus_write_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 sync_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 wr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 wr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 ale_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct devbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long tick_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int get_timing_param_ps(struct devbus *devbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 *ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 time_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) err = of_property_read_u32(node, name, &time_ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(devbus->dev, "%pOF has no '%s' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) node, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) name, time_ps, *ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int devbus_get_timing_params(struct devbus *devbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct devbus_read_params *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct devbus_write_params *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(devbus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "%pOF has no 'devbus,bus-width' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * The bus width is encoded into the register as 0 for 8 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * and 1 for 16 bits, so we do the necessary conversion here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (r->bus_width == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) r->bus_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } else if (r->bus_width == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) r->bus_width = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &r->badr_skew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &r->turn_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) &r->acc_first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) &r->acc_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (of_device_is_compatible(devbus->dev->of_node, "marvell,mvebu-devbus")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) &r->rd_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &r->rd_hold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err = of_property_read_u32(node, "devbus,sync-enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) &w->sync_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(devbus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "%pOF has no 'devbus,sync-enable' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) &w->ale_wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &w->wr_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &w->wr_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void devbus_orion_set_timing_params(struct devbus *devbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct devbus_read_params *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct devbus_write_params *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * The hardware designers found it would be a good idea to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * split most of the values in the register into two fields:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * one containing all the low-order bits, and another one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * containing just the high-order bit. For all of those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * fields, we have to split the value into these two parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) value = (r->turn_off & ORION_TURN_OFF_MASK) << ORION_TURN_OFF_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (r->acc_first & ORION_ACC_FIRST_MASK) << ORION_ACC_FIRST_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (r->acc_next & ORION_ACC_NEXT_MASK) << ORION_ACC_NEXT_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (w->ale_wr & ORION_ALE_WR_MASK) << ORION_ALE_WR_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (w->wr_low & ORION_WR_LOW_MASK) << ORION_WR_LOW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (w->wr_high & ORION_WR_HIGH_MASK) << ORION_WR_HIGH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) r->bus_width << ORION_DEV_WIDTH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ((r->turn_off & ORION_TURN_OFF_EXT_MASK) ? ORION_TURN_OFF_EXT_BIT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ((r->acc_first & ORION_ACC_FIRST_EXT_MASK) ? ORION_ACC_FIRST_EXT_BIT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ((r->acc_next & ORION_ACC_NEXT_EXT_MASK) ? ORION_ACC_NEXT_EXT_BIT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ((w->ale_wr & ORION_ALE_WR_EXT_MASK) ? ORION_ALE_WR_EXT_BIT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ((w->wr_low & ORION_WR_LOW_EXT_MASK) ? ORION_WR_LOW_EXT_BIT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ((w->wr_high & ORION_WR_HIGH_EXT_MASK) ? ORION_WR_HIGH_EXT_BIT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (r->badr_skew << ORION_BADR_SKEW_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ORION_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(value, devbus->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void devbus_armada_set_timing_params(struct devbus *devbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct devbus_read_params *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct devbus_write_params *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Set read timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) value = r->bus_width << ARMADA_DEV_WIDTH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) r->badr_skew << ARMADA_BADR_SKEW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) r->rd_hold << ARMADA_RD_HOLD_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) r->acc_next << ARMADA_ACC_NEXT_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) r->rd_setup << ARMADA_RD_SETUP_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) r->acc_first << ARMADA_ACC_FIRST_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) r->turn_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) devbus->base + ARMADA_READ_PARAM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Set write timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) value = w->sync_enable << ARMADA_SYNC_ENABLE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) w->wr_low << ARMADA_WR_LOW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) w->wr_high << ARMADA_WR_HIGH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) w->ale_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) devbus->base + ARMADA_WRITE_PARAM_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int mvebu_devbus_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct devbus_read_params r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct devbus_write_params w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct devbus *devbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!devbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) devbus->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) devbus->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (IS_ERR(devbus->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return PTR_ERR(devbus->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Obtain clock period in picoseconds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * we need this in order to convert timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * parameters from cycles to picoseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rate = clk_get_rate(clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) devbus->tick_ps = 1000000000 / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) devbus->tick_ps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!of_property_read_bool(node, "devbus,keep-config")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Read the Device Tree node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) err = devbus_get_timing_params(devbus, node, &r, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Set the new timing parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (of_device_is_compatible(node, "marvell,orion-devbus"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) devbus_orion_set_timing_params(devbus, node, &r, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) devbus_armada_set_timing_params(devbus, node, &r, &w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * We need to create a child device explicitly from here to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * guarantee that the child will be probed after the timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * parameters for the bus are written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) err = of_platform_populate(node, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct of_device_id mvebu_devbus_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { .compatible = "marvell,mvebu-devbus" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .compatible = "marvell,orion-devbus" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct platform_driver mvebu_devbus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .probe = mvebu_devbus_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "mvebu-devbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .of_match_table = mvebu_devbus_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int __init mvebu_devbus_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return platform_driver_register(&mvebu_devbus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) module_init(mvebu_devbus_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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