^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015-2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Yong Wu <yong.wu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/component.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <soc/mediatek/smi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/memory/mt2701-larb-port.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/memory/mtk-memory-port.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* mt8173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SMI_LARB_MMU_EN 0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* mt8167 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT8167_SMI_LARB_MMU_EN 0xfc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* mt2701 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_SMI_SECUR_CON_BASE 0x5c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* every register control 8 port, register offset 0x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_SMI_SECUR_CON_ADDR(id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * every port have 4 bit to control, bit[port + 3] control virtual or physical,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * bit[port + 2 : port + 1] control the domain, bit[port] control the security
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * or non-security.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* mt2701 domain should be set to 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* mt2712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define F_MMU_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BANK_SEL(id) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 _id = (id) & 0x3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* SMI COMMON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SMI_BUS_SEL 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* All are MMU0 defaultly. Only specialize mmu1 here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum mtk_smi_gen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MTK_SMI_GEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MTK_SMI_GEN2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mtk_smi_common_plat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum mtk_smi_gen gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) bool has_gals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct mtk_smi_larb_gen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int port_in_larb[MTK_LARB_NR_MAX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void (*config_port)(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int larb_direct_to_common_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bool has_gals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct mtk_smi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct clk *clk_apb, *clk_smi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk *clk_gals0, *clk_gals1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk *clk_async; /*only needed by mt2701*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *smi_ao_base; /* only for gen1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *base; /* only for gen2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const struct mtk_smi_common_plat *plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mtk_smi_larb { /* larb: local arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mtk_smi smi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct device *smi_common_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct mtk_smi_larb_gen *larb_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int larbid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 *mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned char *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int mtk_smi_clk_enable(const struct mtk_smi *smi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = clk_prepare_enable(smi->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = clk_prepare_enable(smi->clk_smi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) goto err_disable_apb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = clk_prepare_enable(smi->clk_gals0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto err_disable_smi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = clk_prepare_enable(smi->clk_gals1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto err_disable_gals0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) err_disable_gals0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_disable_unprepare(smi->clk_gals0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) err_disable_smi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk_disable_unprepare(smi->clk_smi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err_disable_apb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk_disable_unprepare(smi->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void mtk_smi_clk_disable(const struct mtk_smi *smi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clk_disable_unprepare(smi->clk_gals1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk_disable_unprepare(smi->clk_gals0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clk_disable_unprepare(smi->clk_smi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk_disable_unprepare(smi->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int mtk_smi_larb_get(struct device *larbdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret = pm_runtime_resume_and_get(larbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return (ret < 0) ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void mtk_smi_larb_put(struct device *larbdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pm_runtime_put_sync(larbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct mtk_smi_larb *larb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct mtk_smi_larb_iommu *larb_mmu = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (i = 0; i < MTK_LARB_NR_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (dev == larb_mmu[i].dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) larb->larbid = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) larb->mmu = &larb_mmu[i].mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) larb->bank = larb_mmu[i].bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mtk_smi_larb *larb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) reg |= F_MMU_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) reg |= BANK_SEL(larb->bank[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void mtk_smi_larb_config_port_mt8173(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct mtk_smi_larb *larb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void mtk_smi_larb_config_port_mt8167(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct mtk_smi_larb *larb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void mtk_smi_larb_config_port_gen1(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct mtk_smi_larb *larb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int i, m4u_port_id, larb_port_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 sec_con_val, reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) m4u_port_id = larb_gen->port_in_larb[larb->larbid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) - larb_gen->port_in_larb[larb->larbid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (*larb->mmu & BIT(i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* bit[port + 3] controls the virtual or physical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* do not need to enable m4u for this port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg_val = readl(common->smi_ao_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) reg_val |= sec_con_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) common->smi_ao_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Do nothing as the iommu is always enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct component_ops mtk_smi_larb_component_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .bind = mtk_smi_larb_bind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .unbind = mtk_smi_larb_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* mt8173 do not need the port in larb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .config_port = mtk_smi_larb_config_port_mt8173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* mt8167 do not need the port in larb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .config_port = mtk_smi_larb_config_port_mt8167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .port_in_larb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .config_port = mtk_smi_larb_config_port_gen1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .config_port = mtk_smi_larb_config_port_gen2_general,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .config_port = mtk_smi_larb_config_port_gen2_general,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .larb_direct_to_common_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .has_gals = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .config_port = mtk_smi_larb_config_port_gen2_general,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* IPU0 | IPU1 | CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .config_port = mtk_smi_larb_config_port_gen2_general,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct of_device_id mtk_smi_larb_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .compatible = "mediatek,mt8167-smi-larb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .data = &mtk_smi_larb_mt8167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .compatible = "mediatek,mt8173-smi-larb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .data = &mtk_smi_larb_mt8173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .compatible = "mediatek,mt2701-smi-larb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .data = &mtk_smi_larb_mt2701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .compatible = "mediatek,mt2712-smi-larb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .data = &mtk_smi_larb_mt2712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .compatible = "mediatek,mt6779-smi-larb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .data = &mtk_smi_larb_mt6779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .compatible = "mediatek,mt8183-smi-larb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .data = &mtk_smi_larb_mt8183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .compatible = "mediatek,mt8192-smi-larb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .data = &mtk_smi_larb_mt8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int mtk_smi_larb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct mtk_smi_larb *larb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct device_node *smi_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct platform_device *smi_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!larb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) larb->larb_gen = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) larb->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (IS_ERR(larb->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return PTR_ERR(larb->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) larb->smi.clk_apb = devm_clk_get(dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (IS_ERR(larb->smi.clk_apb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return PTR_ERR(larb->smi.clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) larb->smi.clk_smi = devm_clk_get(dev, "smi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (IS_ERR(larb->smi.clk_smi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return PTR_ERR(larb->smi.clk_smi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (larb->larb_gen->has_gals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* The larbs may still haven't gals even if the SoC support.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) larb->smi.clk_gals0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else if (IS_ERR(larb->smi.clk_gals0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return PTR_ERR(larb->smi.clk_gals0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) larb->smi.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!smi_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) smi_pdev = of_find_device_by_node(smi_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) of_node_put(smi_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (smi_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!platform_get_drvdata(smi_pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) larb->smi_common_dev = &smi_pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(dev, "Failed to get the smi_common device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) platform_set_drvdata(pdev, larb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return component_add(dev, &mtk_smi_larb_component_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int mtk_smi_larb_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) component_del(&pdev->dev, &mtk_smi_larb_component_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct mtk_smi_larb *larb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Power on smi-common. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = pm_runtime_resume_and_get(larb->smi_common_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = mtk_smi_clk_enable(&larb->smi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(dev, "Failed to enable clock(%d).\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pm_runtime_put_sync(larb->smi_common_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Configure the basic setting for this larb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) larb_gen->config_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct mtk_smi_larb *larb = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mtk_smi_clk_disable(&larb->smi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pm_runtime_put_sync(larb->smi_common_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct dev_pm_ops smi_larb_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct platform_driver mtk_smi_larb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .probe = mtk_smi_larb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .remove = mtk_smi_larb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "mtk-smi-larb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .of_match_table = mtk_smi_larb_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .pm = &smi_larb_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .gen = MTK_SMI_GEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .gen = MTK_SMI_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .gen = MTK_SMI_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .has_gals = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .gen = MTK_SMI_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .has_gals = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) F_MMU1_LARB(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .gen = MTK_SMI_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .has_gals = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) F_MMU1_LARB(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct of_device_id mtk_smi_common_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .compatible = "mediatek,mt8173-smi-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .data = &mtk_smi_common_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .compatible = "mediatek,mt8167-smi-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .data = &mtk_smi_common_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .compatible = "mediatek,mt2701-smi-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .data = &mtk_smi_common_gen1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .compatible = "mediatek,mt2712-smi-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .data = &mtk_smi_common_gen2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .compatible = "mediatek,mt6779-smi-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .data = &mtk_smi_common_mt6779,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .compatible = "mediatek,mt8183-smi-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .data = &mtk_smi_common_mt8183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .compatible = "mediatek,mt8192-smi-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .data = &mtk_smi_common_mt8192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int mtk_smi_common_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct mtk_smi *common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!common)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) common->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) common->plat = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) common->clk_apb = devm_clk_get(dev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (IS_ERR(common->clk_apb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return PTR_ERR(common->clk_apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) common->clk_smi = devm_clk_get(dev, "smi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (IS_ERR(common->clk_smi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return PTR_ERR(common->clk_smi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (common->plat->has_gals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) common->clk_gals0 = devm_clk_get(dev, "gals0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (IS_ERR(common->clk_gals0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return PTR_ERR(common->clk_gals0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) common->clk_gals1 = devm_clk_get(dev, "gals1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (IS_ERR(common->clk_gals1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return PTR_ERR(common->clk_gals1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * for mtk smi gen 1, we need to get the ao(always on) base to config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * m4u port, and we need to enable the aync clock for transform the smi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (common->plat->gen == MTK_SMI_GEN1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) common->smi_ao_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (IS_ERR(common->smi_ao_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return PTR_ERR(common->smi_ao_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) common->clk_async = devm_clk_get(dev, "async");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (IS_ERR(common->clk_async))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return PTR_ERR(common->clk_async);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = clk_prepare_enable(common->clk_async);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) common->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (IS_ERR(common->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return PTR_ERR(common->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) platform_set_drvdata(pdev, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int mtk_smi_common_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int __maybe_unused mtk_smi_common_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct mtk_smi *common = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 bus_sel = common->plat->bus_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = mtk_smi_clk_enable(common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) writel(bus_sel, common->base + SMI_BUS_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct mtk_smi *common = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mtk_smi_clk_disable(common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const struct dev_pm_ops smi_common_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static struct platform_driver mtk_smi_common_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .probe = mtk_smi_common_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .remove = mtk_smi_common_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .name = "mtk-smi-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .of_match_table = mtk_smi_common_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .pm = &smi_common_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct platform_driver * const smidrivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) &mtk_smi_common_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) &mtk_smi_larb_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int __init mtk_smi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) module_init(mtk_smi_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static void __exit mtk_smi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) module_exit(mtk_smi_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MODULE_DESCRIPTION("MediaTek SMI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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