^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * JZ4780 NAND/external memory controller (NEMC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Alex Smith <alex@alex-smith.me.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/jz4780-nemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NEMC_NFCSR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NEMC_REG_LEN 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NEMC_SMCR_SMT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NEMC_SMCR_BW_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NEMC_SMCR_BW_8 (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NEMC_SMCR_TAS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NEMC_SMCR_TAS_MASK (0xf << NEMC_SMCR_TAS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NEMC_SMCR_TAH_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NEMC_SMCR_TAH_MASK (0xf << NEMC_SMCR_TAH_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NEMC_SMCR_TBP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NEMC_SMCR_TBP_MASK (0xf << NEMC_SMCR_TBP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NEMC_SMCR_TAW_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NEMC_SMCR_TAW_MASK (0xf << NEMC_SMCR_TAW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NEMC_SMCR_TSTRV_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NEMC_SMCR_TSTRV_MASK (0x3f << NEMC_SMCR_TSTRV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct jz_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 tas_tah_cycles_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct jz4780_nemc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct jz_soc_info *soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) uint32_t clk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long banks_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * jz4780_nemc_num_banks() - count the number of banks referenced by a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @dev: device to count banks for, must be a child of the NEMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Return: The number of unique NEMC banks referred to by the specified NEMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * child device. Unique here means that a device that references the same bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * multiple times in its "reg" property will only count once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int jz4780_nemc_num_banks(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const __be32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int bank, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long referenced = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bank = of_read_number(prop, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!(referenced & BIT(bank))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) referenced |= BIT(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) EXPORT_SYMBOL(jz4780_nemc_num_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * jz4780_nemc_set_type() - set the type of device connected to a bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @dev: child device of the NEMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @bank: bank number to configure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @type: type of device connected to the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void jz4780_nemc_set_type(struct device *dev, unsigned int bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) enum jz4780_nemc_bank_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint32_t nfcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) nfcsr = readl(nemc->base + NEMC_NFCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* TODO: Support toggle NAND devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case JZ4780_NEMC_BANK_SRAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case JZ4780_NEMC_BANK_NAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) nfcsr &= ~NEMC_NFCSR_TNFEn(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) nfcsr |= NEMC_NFCSR_NFEn(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(nfcsr, nemc->base + NEMC_NFCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) EXPORT_SYMBOL(jz4780_nemc_set_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @dev: child device of the NEMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @bank: bank number of device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @assert: whether the chip enable pin should be asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * (De-)asserts the chip enable pin for the NAND device connected to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * specified bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint32_t nfcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) nfcsr = readl(nemc->base + NEMC_NFCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) nfcsr |= NEMC_NFCSR_NFCEn(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) nfcsr &= ~NEMC_NFCSR_NFCEn(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel(nfcsr, nemc->base + NEMC_NFCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) EXPORT_SYMBOL(jz4780_nemc_assert);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rate = clk_get_rate(nemc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Return in picoseconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return div64_ul(1000000000000ull, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) uint32_t smcr, val, cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Conversion of tBP and tAW cycle counts to values supported by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * hardware (round up to the next supported value).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const u8 convert_tBP_tAW[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* 11 - 12 -> 12 cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 11, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* 13 - 15 -> 15 cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 12, 12, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* 16 - 20 -> 20 cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 13, 13, 13, 13, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* 21 - 25 -> 25 cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 14, 14, 14, 14, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* 26 - 31 -> 31 cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 15, 15, 15, 15, 15, 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) smcr = readl(nemc->base + NEMC_SMCRn(bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) smcr &= ~NEMC_SMCR_SMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) smcr &= ~NEMC_SMCR_BW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) smcr |= NEMC_SMCR_BW_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Earlier SoCs support a 16 bit bus width (the 4780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * does not), until those are properly supported, error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(nemc->dev, "unsupported bus width: %u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) smcr &= ~NEMC_SMCR_TAS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cycles = jz4780_nemc_ns_to_cycles(nemc, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (cycles > nemc->soc_info->tas_tah_cycles_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) smcr |= cycles << NEMC_SMCR_TAS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) smcr &= ~NEMC_SMCR_TAH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cycles = jz4780_nemc_ns_to_cycles(nemc, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (cycles > nemc->soc_info->tas_tah_cycles_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) val, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) smcr |= cycles << NEMC_SMCR_TAH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) smcr &= ~NEMC_SMCR_TBP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cycles = jz4780_nemc_ns_to_cycles(nemc, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (cycles > 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) smcr &= ~NEMC_SMCR_TAW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cycles = jz4780_nemc_ns_to_cycles(nemc, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (cycles > 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) smcr &= ~NEMC_SMCR_TSTRV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cycles = jz4780_nemc_ns_to_cycles(nemc, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (cycles > 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(smcr, nemc->base + NEMC_SMCRn(bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int jz4780_nemc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct jz4780_nemc *nemc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) const __be32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long referenced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!nemc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) nemc->soc_info = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (!nemc->soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_lock_init(&nemc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) nemc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * The driver currently only uses the registers up to offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * NEMC registers, we only request the registers we will use for now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * that way the EFUSE driver can probe too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(dev, "unable to request I/O memory region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!nemc->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(dev, "failed to get I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writel(0, nemc->base + NEMC_NFCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) nemc->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (IS_ERR(nemc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_err(dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return PTR_ERR(nemc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = clk_prepare_enable(nemc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(dev, "failed to enable clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) nemc->clk_period = jz4780_nemc_clk_period(nemc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!nemc->clk_period) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(dev, "failed to calculate clock period\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) clk_disable_unprepare(nemc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Iterate over child devices, check that they do not conflict with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * each other, and register child devices for them. If a child device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * has invalid properties, it is ignored and no platform device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * registered for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) for_each_child_of_node(nemc->dev->of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) referenced = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) while ((prop = of_get_address(child, i++, NULL, NULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) bank = of_read_number(prop, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(nemc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "%pOF requests invalid bank %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) child, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Will continue the outer loop below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) referenced = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) referenced |= BIT(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!referenced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(nemc->dev, "%pOF has no addresses\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } else if (nemc->banks_present & referenced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(nemc->dev, "%pOF conflicts with another node\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Configure bank parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!jz4780_nemc_configure_bank(nemc, bank, child)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) referenced = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (referenced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (of_platform_device_create(child, NULL, nemc->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) nemc->banks_present |= referenced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) platform_set_drvdata(pdev, nemc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_info(dev, "JZ4780 NEMC initialised\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int jz4780_nemc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct jz4780_nemc *nemc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) clk_disable_unprepare(nemc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct jz_soc_info jz4740_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .tas_tah_cycles_max = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct jz_soc_info jz4780_soc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .tas_tah_cycles_max = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct of_device_id jz4780_nemc_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct platform_driver jz4780_nemc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .probe = jz4780_nemc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .remove = jz4780_nemc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .name = "jz4780-nemc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .of_match_table = of_match_ptr(jz4780_nemc_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int __init jz4780_nemc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return platform_driver_register(&jz4780_nemc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) subsys_initcall(jz4780_nemc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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