Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Definitions for DDR memories based on JEDEC specs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Aneesh V <aneesh@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef __JEDEC_DDR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define __JEDEC_DDR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* DDR Densities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DDR_DENSITY_64Mb	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DDR_DENSITY_128Mb	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DDR_DENSITY_256Mb	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DDR_DENSITY_512Mb	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DDR_DENSITY_1Gb		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DDR_DENSITY_2Gb		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DDR_DENSITY_4Gb		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DDR_DENSITY_8Gb		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DDR_DENSITY_16Gb	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DDR_DENSITY_32Gb	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* DDR type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DDR_TYPE_DDR2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DDR_TYPE_DDR3		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DDR_TYPE_LPDDR2_S4	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DDR_TYPE_LPDDR2_S2	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DDR_TYPE_LPDDR2_NVM	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DDR_TYPE_LPDDR3		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* DDR IO width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DDR_IO_WIDTH_4		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DDR_IO_WIDTH_8		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DDR_IO_WIDTH_16		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DDR_IO_WIDTH_32		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Number of Row bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define R9			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define R10			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define R11			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define R12			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define R13			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define R14			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define R15			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define R16			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Number of Column bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define C7			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define C8			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define C9			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define C10			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define C11			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define C12			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* Number of Banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define B1			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define B2			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define B4			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define B8			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Refresh rate in nano-seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define T_REFI_15_6		15600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define T_REFI_7_8		7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define T_REFI_3_9		3900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* tRFC values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define T_RFC_90		90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define T_RFC_110		110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define T_RFC_130		130000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define T_RFC_160		160000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define T_RFC_210		210000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define T_RFC_300		300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define T_RFC_350		350000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* Mode register numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define DDR_MR0			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DDR_MR1			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DDR_MR2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define DDR_MR3			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DDR_MR4			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DDR_MR5			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DDR_MR6			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DDR_MR7			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DDR_MR8			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DDR_MR9			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DDR_MR10		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DDR_MR11		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define DDR_MR16		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DDR_MR17		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DDR_MR18		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * LPDDR2 related defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* MR4 register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MR4_SDRAM_REF_RATE_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MR4_SDRAM_REF_RATE_MASK				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MR4_TUF_SHIFT					7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MR4_TUF_MASK					(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* MR4 SDRAM Refresh Rate field values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SDRAM_TEMP_NOMINAL				0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SDRAM_TEMP_RESERVED_4				0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NUM_DDR_ADDR_TABLE_ENTRIES			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NUM_DDR_TIMING_TABLE_ENTRIES			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Structure for DDR addressing info from the JEDEC spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct lpddr2_addressing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 num_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 tREFI_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 tRFCab_ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * Structure for timings from the LPDDR2 datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * All parameters are in pico seconds(ps) unless explicitly indicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * with a suffix like tRAS_max_ns below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct lpddr2_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32 min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 tRPab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u32 tRCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 tWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 tRAS_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 tRRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u32 tWTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u32 tXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32 tRTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u32 tCKESR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32 tDQSCK_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u32 tDQSCK_max_derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u32 tFAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u32 tZQCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32 tZQCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32 tZQinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32 tRAS_max_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * Min value for some parameters in terms of number of tCK cycles(nCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * Please set to zero parameters that are not valid for a given memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct lpddr2_min_tck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32 tRPab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 tRCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32 tWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u32 tRASmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32 tRRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32 tWTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32 tXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32 tRTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32 tCKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 tCKESR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u32 tFAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) extern const struct lpddr2_addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) extern const struct lpddr2_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * All parameters are in pico seconds(ps) excluding max_freq, min_freq which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * are in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct lpddr3_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32 max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u32 min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 tRFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 tRRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 tRPab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 tRPpb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u32 tRCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u32 tRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u32 tRAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u32 tWTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u32 tWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 tRTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 tW2W_C2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u32 tR2R_C2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	u32 tWL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	u32 tDQSCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32 tRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 tFAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 tXSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 tXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 tCKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u32 tCKESR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u32 tMRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * Min value for some parameters in terms of number of tCK cycles(nCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * Please set to zero parameters that are not valid for a given memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct lpddr3_min_tck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	u32 tRFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u32 tRRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u32 tRPab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u32 tRPpb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 tRCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	u32 tRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 tRAS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u32 tWTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	u32 tWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u32 tRTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	u32 tW2W_C2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	u32 tR2R_C2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u32 tWL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 tDQSCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u32 tRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u32 tFAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u32 tXSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	u32 tXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u32 tCKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u32 tCKESR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u32 tMRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif /* __JEDEC_DDR_H */