Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2011 Freescale Semiconductor, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Freescale Integrated Flash Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/fsl_ifc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * convert_ifc_address - convert the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @addr_base:	base address of the memory bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) unsigned int convert_ifc_address(phys_addr_t addr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	return addr_base & CSPR_BA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) EXPORT_SYMBOL(convert_ifc_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * fsl_ifc_find - find IFC bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @addr_base:	base address of the memory bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * This function walks IFC banks comparing "Base address" field of the CSPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * registers with the supplied addr_base argument. When bases match this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * function returns bank number (starting with 0), otherwise it returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * appropriate errno value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) int fsl_ifc_find(phys_addr_t addr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 				convert_ifc_address(addr_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) EXPORT_SYMBOL(fsl_ifc_find);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * Clear all the common status and event registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* enable all error and events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* enable all error and event interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ifc_out32(0x0, &ifc->cm_erattr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ifc_out32(0x0, &ifc->cm_erattr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int fsl_ifc_ctrl_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	free_irq(ctrl->nand_irq, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	free_irq(ctrl->irq, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	irq_dispose_mapping(ctrl->nand_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	irq_dispose_mapping(ctrl->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	iounmap(ctrl->gregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	dev_set_drvdata(&dev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * NAND events are split between an operational interrupt which only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * receives OPC, and an error interrupt that receives everything else,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * including non-NAND errors.  Whichever interrupt gets to it first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * records the status and wakes the wait queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static DEFINE_SPINLOCK(nand_irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	spin_lock_irqsave(&nand_irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		ctrl->nand_stat = stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		wake_up(&ctrl->nand_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	spin_unlock_irqrestore(&nand_irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct fsl_ifc_ctrl *ctrl = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (check_nand_stat(ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * NOTE: This interrupt is used to report ifc events of various kinds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * such as transaction errors on the chipselects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct fsl_ifc_ctrl *ctrl = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u32 err_axiid, err_srcid, status, cs_err, err_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/* read for chip select error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	cs_err = ifc_in32(&ifc->cm_evter_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (cs_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to any memory bank 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			cs_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		/* clear the chip select error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		/* read error attribute registers print the error information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		status = ifc_in32(&ifc->cm_erattr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		err_addr = ifc_in32(&ifc->cm_erattr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (status & IFC_CM_ERATTR0_ERTYP_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			dev_err(ctrl->dev, "Read transaction error CM_ERATTR0 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			dev_err(ctrl->dev, "Write transaction error CM_ERATTR0 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 					IFC_CM_ERATTR0_ERAID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		dev_err(ctrl->dev, "AXI ID of the error transaction 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			err_axiid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					IFC_CM_ERATTR0_ESRCID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		dev_err(ctrl->dev, "SRC ID of the error transaction 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			err_srcid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev_err(ctrl->dev, "Transaction Address corresponding to error ERADDR 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			err_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (check_nand_stat(ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * fsl_ifc_ctrl_probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * called by device layer when it finds a device matching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * one our driver can handled. This code allocates all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * the resources needed for the controller only.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * resources for the NAND banks themselves are allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * in the chip probe function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int fsl_ifc_ctrl_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int version, banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	fsl_ifc_ctrl_dev = devm_kzalloc(&dev->dev, sizeof(*fsl_ifc_ctrl_dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 					GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (!fsl_ifc_ctrl_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* IOMAP the entire IFC region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!fsl_ifc_ctrl_dev->gregs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		dev_err(&dev->dev, "failed to get memory region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		fsl_ifc_ctrl_dev->little_endian = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		fsl_ifc_ctrl_dev->little_endian = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			FSL_IFC_VERSION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		version >> 24, (version >> 16) & 0xf, banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	fsl_ifc_ctrl_dev->version = version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	fsl_ifc_ctrl_dev->banks = banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	addr = fsl_ifc_ctrl_dev->gregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (version >= FSL_IFC_VERSION_2_0_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		addr += PGOFFSET_64K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		addr += PGOFFSET_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	fsl_ifc_ctrl_dev->rregs = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	/* get the Controller level irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (fsl_ifc_ctrl_dev->irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		dev_err(&dev->dev, "failed to get irq resource for IFC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* get the nand machine irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	fsl_ifc_ctrl_dev->nand_irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			irq_of_parse_and_map(dev->dev.of_node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	fsl_ifc_ctrl_dev->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		goto err_unmap_nandirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			  "fsl-ifc", fsl_ifc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		dev_err(&dev->dev, "failed to install irq (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			fsl_ifc_ctrl_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		goto err_unmap_nandirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (fsl_ifc_ctrl_dev->nand_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			dev_err(&dev->dev, "failed to install irq (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				fsl_ifc_ctrl_dev->nand_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err_unmap_nandirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	iounmap(fsl_ifc_ctrl_dev->gregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct of_device_id fsl_ifc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.compatible = "fsl,ifc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct platform_driver fsl_ifc_ctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.name	= "fsl-ifc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.of_match_table = fsl_ifc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.probe       = fsl_ifc_ctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.remove      = fsl_ifc_ctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int __init fsl_ifc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return platform_driver_register(&fsl_ifc_ctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) subsys_initcall(fsl_ifc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_AUTHOR("Freescale Semiconductor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");