^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Defines for the EMIF driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __EMIF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __EMIF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Maximum number of different frequencies supported by EMIF driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Determines the number of entries in the pointer array for register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EMIF_MAX_NUM_FREQUENCIES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* State of the core voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DDR_VOLTAGE_STABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DDR_VOLTAGE_RAMPING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Defines for timing De-rating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EMIF_NORMAL_TIMINGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EMIF_DERATED_TIMINGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Length of the forced read idle period in terms of cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EMIF_READ_IDLE_LEN_VAL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * forced read idle interval to be used when voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * is changed as part of DVFS/DPS - 1ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define READ_IDLE_INTERVAL_DVFS (1*1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Forced read idle interval to be used when voltage is stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 50us - or maximum value will do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define READ_IDLE_INTERVAL_NORMAL (50*1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* DLL calibration interval when voltage is NOT stable - 1us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DLL_CALIB_INTERVAL_DVFS (1*1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DLL_CALIB_ACK_WAIT_VAL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Interval between ZQCS commands - hw team recommended value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EMIF_ZQCS_INTERVAL_US (50*1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Enable ZQ Calibration on exiting Self-refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ZQ_SFEXITEN_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * ZQ Calibration simultaneously on both chip-selects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Needs one calibration resistor per CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ZQ_DUALCALEN_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ZQ_DUALCALEN_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define T_ZQCS_DEFAULT_NS 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define T_ZQCL_DEFAULT_NS 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define T_ZQINIT_DEFAULT_NS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* DPD_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DPD_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DPD_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Default values for the low-power entry to be used if not provided by user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EMIF_LP_MODE_TIMEOUT_POWER 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EMIF_LP_MODE_FREQ_THRESHOLD 400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define EMIF_T_CSTA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define EMIF_T_PDLL_UL 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* External PHY control registers magic values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Registers offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EMIF_MODULE_ID_AND_REVISION 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EMIF_STATUS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EMIF_SDRAM_CONFIG 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EMIF_SDRAM_CONFIG_2 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EMIF_SDRAM_REFRESH_CONTROL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EMIF_SDRAM_TIMING_1 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EMIF_SDRAM_TIMING_1_SHDW 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EMIF_SDRAM_TIMING_2 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EMIF_SDRAM_TIMING_2_SHDW 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define EMIF_SDRAM_TIMING_3 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EMIF_SDRAM_TIMING_3_SHDW 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EMIF_LPDDR2_NVM_TIMING 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EMIF_LPDDR2_MODE_REG_DATA 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EMIF_OCP_CONFIG 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EMIF_OCP_CONFIG_VALUE_1 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EMIF_OCP_CONFIG_VALUE_2 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EMIF_PERFORMANCE_COUNTER_1 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EMIF_PERFORMANCE_COUNTER_2 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EMIF_MISC_REG 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define EMIF_DLL_CALIB_CTRL 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EMIF_END_OF_INTERRUPT 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EMIF_OCP_ERROR_LOG 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EMIF_DDR_PHY_CTRL_1 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EMIF_DDR_PHY_CTRL_2 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define EMIF_COS_CONFIG 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EMIF_PHY_STATUS_1 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EMIF_PHY_STATUS_2 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EMIF_PHY_STATUS_3 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EMIF_PHY_STATUS_4 0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EMIF_PHY_STATUS_5 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EMIF_PHY_STATUS_6 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EMIF_PHY_STATUS_7 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EMIF_PHY_STATUS_8 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EMIF_PHY_STATUS_9 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EMIF_PHY_STATUS_10 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EMIF_PHY_STATUS_11 0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EMIF_PHY_STATUS_12 0x016c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define EMIF_PHY_STATUS_13 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EMIF_PHY_STATUS_14 0x0174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EMIF_PHY_STATUS_15 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EMIF_PHY_STATUS_16 0x017c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EMIF_PHY_STATUS_17 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EMIF_PHY_STATUS_18 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EMIF_PHY_STATUS_19 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define EMIF_PHY_STATUS_20 0x018c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define EMIF_PHY_STATUS_21 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define EMIF_EXT_PHY_CTRL_1 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EMIF_EXT_PHY_CTRL_2 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EMIF_EXT_PHY_CTRL_3 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EMIF_EXT_PHY_CTRL_4 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EMIF_EXT_PHY_CTRL_5 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define EMIF_EXT_PHY_CTRL_6 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EMIF_EXT_PHY_CTRL_7 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EMIF_EXT_PHY_CTRL_8 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EMIF_EXT_PHY_CTRL_9 0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define EMIF_EXT_PHY_CTRL_10 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define EMIF_EXT_PHY_CTRL_11 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define EMIF_EXT_PHY_CTRL_12 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define EMIF_EXT_PHY_CTRL_13 0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EMIF_EXT_PHY_CTRL_14 0x0268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define EMIF_EXT_PHY_CTRL_15 0x0270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define EMIF_EXT_PHY_CTRL_16 0x0278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define EMIF_EXT_PHY_CTRL_17 0x0280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define EMIF_EXT_PHY_CTRL_18 0x0288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define EMIF_EXT_PHY_CTRL_19 0x0290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define EMIF_EXT_PHY_CTRL_20 0x0298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define EMIF_EXT_PHY_CTRL_21 0x02a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define EMIF_EXT_PHY_CTRL_22 0x02a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define EMIF_EXT_PHY_CTRL_23 0x02b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define EMIF_EXT_PHY_CTRL_24 0x02b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define EMIF_EXT_PHY_CTRL_25 0x02c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define EMIF_EXT_PHY_CTRL_26 0x02c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define EMIF_EXT_PHY_CTRL_27 0x02d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define EMIF_EXT_PHY_CTRL_28 0x02d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define EMIF_EXT_PHY_CTRL_29 0x02e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define EMIF_EXT_PHY_CTRL_30 0x02e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Registers shifts and masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* EMIF_MODULE_ID_AND_REVISION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SCHEME_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SCHEME_MASK (0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MODULE_ID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MODULE_ID_MASK (0xfff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define RTL_VERSION_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define RTL_VERSION_MASK (0x1f << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MAJOR_REVISION_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MAJOR_REVISION_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MINOR_REVISION_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MINOR_REVISION_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define BE_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define BE_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DUAL_CLK_MODE_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DUAL_CLK_MODE_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define FAST_INIT_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FAST_INIT_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RDLVLGATETO_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define RDLVLGATETO_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define RDLVLTO_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define RDLVLTO_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define WRLVLTO_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define WRLVLTO_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PHY_DLL_READY_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PHY_DLL_READY_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* SDRAM_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SDRAM_TYPE_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SDRAM_TYPE_MASK (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IBANK_POS_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IBANK_POS_MASK (0x3 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DDR_TERM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DDR_TERM_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DDR2_DDQS_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DDR2_DDQS_MASK (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DYN_ODT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DYN_ODT_MASK (0x3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DDR_DISABLE_DLL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DDR_DISABLE_DLL_MASK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SDRAM_DRIVE_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SDRAM_DRIVE_MASK (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CWL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CWL_MASK (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define NARROW_MODE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define NARROW_MODE_MASK (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CL_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CL_MASK (0xf << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ROWSIZE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ROWSIZE_MASK (0x7 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IBANK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IBANK_MASK (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define EBANK_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define EBANK_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PAGESIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PAGESIZE_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* SDRAM_CONFIG_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CS1NVMEN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CS1NVMEN_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define EBANK_POS_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define EBANK_POS_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RDBNUM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define RDBNUM_MASK (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define RDBSIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define RDBSIZE_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* SDRAM_REFRESH_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define INITREF_DIS_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define INITREF_DIS_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SRT_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SRT_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ASR_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ASR_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PASR_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define PASR_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define REFRESH_RATE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define REFRESH_RATE_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* SDRAM_TIMING_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define T_RTW_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define T_RTW_MASK (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define T_RP_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define T_RP_MASK (0xf << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define T_RCD_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define T_RCD_MASK (0xf << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define T_WR_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define T_WR_MASK (0xf << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define T_RAS_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define T_RAS_MASK (0x1f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define T_RC_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define T_RC_MASK (0x3f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define T_RRD_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define T_RRD_MASK (0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define T_WTR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define T_WTR_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* SDRAM_TIMING_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define T_XP_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define T_XP_MASK (0x7 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define T_ODT_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define T_ODT_MASK (0x7 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define T_XSNR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define T_XSNR_MASK (0x1ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define T_XSRD_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define T_XSRD_MASK (0x3ff << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define T_RTP_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define T_RTP_MASK (0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define T_CKE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define T_CKE_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* SDRAM_TIMING_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define T_PDLL_UL_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define T_PDLL_UL_MASK (0xf << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define T_CSTA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define T_CSTA_MASK (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define T_CKESR_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define T_CKESR_MASK (0x7 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ZQ_ZQCS_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ZQ_ZQCS_MASK (0x3f << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define T_TDQSCKMAX_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define T_TDQSCKMAX_MASK (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define T_RFC_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define T_RFC_MASK (0x1ff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define T_RAS_MAX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define T_RAS_MAX_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* POWER_MANAGEMENT_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PD_TIM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PD_TIM_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DPD_EN_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DPD_EN_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define LP_MODE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define LP_MODE_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SR_TIM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SR_TIM_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CS_TIM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CS_TIM_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* LPDDR2_MODE_REG_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define VALUE_0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define VALUE_0_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* LPDDR2_MODE_REG_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CS_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CS_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define REFRESH_EN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define REFRESH_EN_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define ADDRESS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define ADDRESS_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* OCP_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SYS_THRESH_MAX_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SYS_THRESH_MAX_MASK (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define MPU_THRESH_MAX_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MPU_THRESH_MAX_MASK (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define LL_THRESH_MAX_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define LL_THRESH_MAX_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* PERFORMANCE_COUNTER_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define COUNTER1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define COUNTER1_MASK (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* PERFORMANCE_COUNTER_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define COUNTER2_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define COUNTER2_MASK (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* PERFORMANCE_COUNTER_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CNTR2_MCONNID_EN_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CNTR2_MCONNID_EN_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CNTR2_REGION_EN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CNTR2_REGION_EN_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CNTR2_CFG_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CNTR2_CFG_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CNTR1_MCONNID_EN_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CNTR1_MCONNID_EN_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CNTR1_REGION_EN_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define CNTR1_REGION_EN_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CNTR1_CFG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CNTR1_CFG_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MCONNID2_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MCONNID2_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define REGION_SEL2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define REGION_SEL2_MASK (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MCONNID1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MCONNID1_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define REGION_SEL1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define REGION_SEL1_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* PERFORMANCE_COUNTER_TIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TOTAL_TIME_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define TOTAL_TIME_MASK (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* DLL_CALIB_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define ACK_WAIT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define ACK_WAIT_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define DLL_CALIB_INTERVAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* END_OF_INTERRUPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define EOI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define EOI_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* SYSTEM_OCP_INTERRUPT_RAW_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define DNV_SYS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define DNV_SYS_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define TA_SYS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define TA_SYS_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define ERR_SYS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define ERR_SYS_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define DNV_LL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define DNV_LL_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define TA_LL_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define TA_LL_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define ERR_LL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define ERR_LL_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* SYSTEM_OCP_INTERRUPT_ENABLE_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define EN_DNV_SYS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define EN_DNV_SYS_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define EN_TA_SYS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define EN_TA_SYS_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define EN_ERR_SYS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define EN_ERR_SYS_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define EN_DNV_LL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define EN_DNV_LL_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define EN_TA_LL_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define EN_TA_LL_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define EN_ERR_LL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define EN_ERR_LL_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define ZQ_CS1EN_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define ZQ_CS1EN_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define ZQ_CS0EN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define ZQ_CS0EN_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define ZQ_DUALCALEN_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define ZQ_DUALCALEN_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define ZQ_SFEXITEN_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define ZQ_SFEXITEN_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define ZQ_ZQINIT_MULT_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define ZQ_ZQINIT_MULT_MASK (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define ZQ_ZQCL_MULT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define ZQ_ZQCL_MULT_MASK (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define ZQ_REFINTERVAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define ZQ_REFINTERVAL_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* TEMPERATURE_ALERT_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define TA_CS1EN_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define TA_CS1EN_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define TA_CS0EN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define TA_CS0EN_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define TA_SFEXITEN_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define TA_SFEXITEN_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define TA_DEVWDT_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define TA_DEVWDT_MASK (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define TA_DEVCNT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define TA_DEVCNT_MASK (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define TA_REFINTERVAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define TA_REFINTERVAL_MASK (0x3fffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* OCP_ERROR_LOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define MADDRSPACE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define MADDRSPACE_MASK (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define MBURSTSEQ_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define MBURSTSEQ_MASK (0x7 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define MCMD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define MCMD_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define MCONNID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define MCONNID_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* READ_WRITE_LEVELING_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define RDWRLVLFULL_START 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* DDR_PHY_CTRL_1 - EMIF4D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define READ_LATENCY_SHIFT_4D 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define READ_LATENCY_MASK_4D (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* DDR_PHY_CTRL_1 - EMIF4D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define DLL_HALF_DELAY_SHIFT_4D5 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define DLL_HALF_DELAY_MASK_4D5 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define READ_LATENCY_SHIFT_4D5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define READ_LATENCY_MASK_4D5 (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* DDR_PHY_CTRL_1_SHDW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define DDR_PHY_CTRL_1_SHDW_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define READ_LATENCY_SHDW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define READ_LATENCY_SHDW_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define EMIF_SRAM_AM33_REG_LAYOUT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define EMIF_SRAM_AM43_REG_LAYOUT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Structure containing shadow of important registers in EMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * The calculation function fills in this structure to be later used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * initialisation and DVFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct emif_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 ref_ctrl_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 ref_ctrl_shdw_derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 sdram_tim1_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 sdram_tim1_shdw_derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 sdram_tim2_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u32 sdram_tim3_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 sdram_tim3_shdw_derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 pwr_mgmt_ctrl_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 read_idle_ctrl_shdw_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u32 dll_calib_ctrl_shdw_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 read_idle_ctrl_shdw_volt_ramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 dll_calib_ctrl_shdw_volt_ramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 phy_ctrl_1_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u32 ext_phy_ctrl_2_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 ext_phy_ctrl_3_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 ext_phy_ctrl_4_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct ti_emif_pm_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) extern unsigned int ti_emif_sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) extern unsigned int ti_emif_sram_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) extern struct ti_emif_pm_data ti_emif_pm_sram_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) extern struct emif_regs_amx3 ti_emif_regs_amx3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) void ti_emif_save_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) void ti_emif_restore_context(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) void ti_emif_run_hw_leveling(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void ti_emif_enter_sr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void ti_emif_exit_sr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) void ti_emif_abort_sr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #endif /* __EMIF_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags