^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * EMIF driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Aneesh V <aneesh@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_data/emif_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "emif.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "jedec_ddr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "of_memory.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * struct emif_data - Per device static data for driver's use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @duplicate: Whether the DDR devices attached to this EMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * instance are exactly same as that on EMIF1. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * this case we can save some memory and processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @temperature_level: Maximum temperature of LPDDR2 devices attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * to this EMIF - read from MR4 register. If there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * are two devices attached to this EMIF, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * value is the maximum of the two temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * levels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @node: node in the device list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @base: base address of memory-mapped IO registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @dev: device pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @addressing table with addressing information from the spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @regs_cache: An array of 'struct emif_regs' that stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * calculated register values for different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * frequencies, to avoid re-calculating them on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * each DVFS transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @curr_regs: The set of register values used in the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * frequency change (i.e. corresponding to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * frequency in effect at the moment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @plat_data: Pointer to saved platform data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @debugfs_root: dentry to the root folder for EMIF in debugfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @np_ddr: Pointer to ddr device tree node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct emif_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 duplicate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 temperature_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 lpmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long irq_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct lpddr2_addressing *addressing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct emif_regs *curr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct emif_platform_data *plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct dentry *debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct device_node *np_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct emif_data *emif1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static spinlock_t emif_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static unsigned long irq_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static u32 t_ck; /* DDR clock period in ps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static LIST_HEAD(device_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct emif_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 type = emif->plat_data->device_info->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 ip_rev = emif->plat_data->ip_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) seq_printf(s, "EMIF register cache dump for %dMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regs->freq/1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ip_rev == EMIF_4D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) regs->read_idle_ctrl_shdw_normal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regs->read_idle_ctrl_shdw_volt_ramp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else if (ip_rev == EMIF_4D5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regs->dll_calib_ctrl_shdw_normal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) regs->dll_calib_ctrl_shdw_volt_ramp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) regs->ref_ctrl_shdw_derated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regs->sdram_tim1_shdw_derated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) regs->sdram_tim3_shdw_derated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int emif_regdump_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct emif_data *emif = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct emif_regs **regs_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (emif->duplicate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regs_cache = emif1->regs_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) regs_cache = emif->regs_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) do_emif_regdump_show(s, emif, regs_cache[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) seq_putc(s, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEFINE_SHOW_ATTRIBUTE(emif_regdump);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int emif_mr4_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct emif_data *emif = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) seq_printf(s, "MR4=%d\n", emif->temperature_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEFINE_SHOW_ATTRIBUTE(emif_mr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int __init_or_module emif_debugfs_init(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) &emif_regdump_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) debugfs_create_file("mr4", S_IRUGO, emif->debugfs_root, emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) &emif_mr4_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void __exit emif_debugfs_exit(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) debugfs_remove_recursive(emif->debugfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) emif->debugfs_root = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline void __exit emif_debugfs_exit(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Calculate the period of DDR clock from frequency value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void set_ddr_clk_period(u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Divide 10^12 by frequency to get period in ps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Get bus width used by EMIF. Note that this may be different from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * bus width of the DDR devices used. For instance two 16-bit DDR devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * may be connected to a given CS of EMIF. In this case bus width as far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static u32 get_emif_bus_width(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) >> NARROW_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) width = width == 0 ? 32 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Get the CL from SDRAM_CONFIG register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static u32 get_cl(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void set_lpmode(struct emif_data *emif, u8 lpmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Workaround for errata i743 - LPDDR2 Power-Down State is Not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Efficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * i743 DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * The EMIF supports power-down state for low power. The EMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * automatically puts the SDRAM into power-down after the memory is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * not accessed for a defined number of cycles and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * As the EMIF supports automatic output impedance calibration, a ZQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * calibration long command is issued every time it exits active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * power-down and precharge power-down modes. The EMIF waits and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * blocks any other command during this calibration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * The EMIF does not allow selective disabling of ZQ calibration upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * exit of power-down mode. Due to very short periods of power-down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * cycles, ZQ calibration overhead creates bandwidth issues and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * increases overall system power consumption. On the other hand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * issuing ZQ calibration long commands when exiting self-refresh is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * still required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * WORKAROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Because there is no power consumption benefit of the power-down due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * to the calibration and there is a performance risk, the guideline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * is to not allow power-down state and, therefore, to not have set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if ((emif->plat_data->ip_rev == EMIF_4D) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (lpmode == EMIF_LP_MODE_PWR_DN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) WARN_ONCE(1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* rollback LP_MODE to Self-refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) lpmode = EMIF_LP_MODE_SELF_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) temp &= ~LP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) temp |= (lpmode << LP_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void do_freq_update(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct emif_data *emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * i728 DESCRIPTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * The EMIF automatically puts the SDRAM into self-refresh mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * after the EMIF has not performed accesses during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * to 0x2. If during a small window the following three events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * occur:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * - The SR_TIMING counter expires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * - And frequency change is requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * - And OCP access is requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Then it causes instable clock on the DDR interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * WORKAROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * To avoid the occurrence of the three events, the workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * is to disable the self-refresh when requesting a frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * change. Before requesting a frequency change the software must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * frequency change has been done, the software can reprogram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) list_for_each_entry(emif, &device_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) set_lpmode(emif, EMIF_LP_MODE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * TODO: Do FREQ_UPDATE here when an API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * is available for this as part of the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) list_for_each_entry(emif, &device_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Find addressing table entry based on the device's type and density */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct lpddr2_addressing *get_addressing_table(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct ddr_device_info *device_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 index, type, density;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) type = device_info->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) density = device_info->density;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case DDR_TYPE_LPDDR2_S4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) index = density - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case DDR_TYPE_LPDDR2_S2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) switch (density) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case DDR_DENSITY_1Gb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case DDR_DENSITY_2Gb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) index = density + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) index = density - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return &lpddr2_jedec_addressing_table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Find the the right timing table from the array of timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * tables of the device using DDR clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 i, min, max, freq_nearest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) const struct lpddr2_timings *timings = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const struct lpddr2_timings *timings_arr = emif->plat_data->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct device *dev = emif->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Start with a very high frequency - 1GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) freq_nearest = 1000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Find the timings table such that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * 1. the frequency range covers the required frequency(safe) AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * 2. the max_freq is closest to the required frequency(optimal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) max = timings_arr[i].max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) min = timings_arr[i].min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) freq_nearest = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) timings = &timings_arr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(dev, "%s: couldn't find timings for - %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __func__, freq, freq_nearest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static u32 get_sdram_ref_ctrl_shdw(u32 freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct lpddr2_addressing *addressing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Scale down frequency and t_refi to avoid overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) freq_khz = freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) t_refi = addressing->tREFI_ns / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * refresh rate to be set is 'tREFI(in us) * freq in MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * division by 10000 to account for change in units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) val = t_refi * freq_khz / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ref_ctrl_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) const struct lpddr2_min_tck *min_tck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) const struct lpddr2_addressing *addressing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 tim1 = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tim1 |= val << T_WTR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (addressing->num_banks == B8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tim1 |= (val - 1) << T_RRD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tim1 |= val << T_RC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tim1 |= (val - 1) << T_RAS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) tim1 |= val << T_WR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) tim1 |= val << T_RCD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) tim1 |= val << T_RP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return tim1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const struct lpddr2_min_tck *min_tck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) const struct lpddr2_addressing *addressing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 tim1 = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) tim1 = val << T_WTR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * to tFAW for de-rating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (addressing->num_banks == B8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val = max(min_tck->tRRD, val) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tim1 |= val << T_RRD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tim1 |= (val - 1) << T_RC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) val = max(min_tck->tRASmin, val) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) tim1 |= val << T_RAS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) tim1 |= val << T_WR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) tim1 |= (val - 1) << T_RCD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) tim1 |= (val - 1) << T_RP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return tim1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const struct lpddr2_min_tck *min_tck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) const struct lpddr2_addressing *addressing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 tim2 = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val = min_tck->tCKE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) tim2 |= val << T_CKE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) tim2 |= val << T_RTP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tim2 |= val << T_XSNR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* XSRD same as XSNR for LPDDR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) tim2 |= val << T_XSRD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) tim2 |= val << T_XP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return tim2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const struct lpddr2_min_tck *min_tck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) const struct lpddr2_addressing *addressing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 type, u32 ip_rev, u32 derated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 tim3 = 0, val = 0, t_dqsck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val = val > 0xF ? 0xF : val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tim3 |= val << T_RAS_MAX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) tim3 |= val << T_RFC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) timings->tDQSCK_max_derated : timings->tDQSCK_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ip_rev == EMIF_4D5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) tim3 |= val << T_TDQSCKMAX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) tim3 |= val << ZQ_ZQCS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) val = DIV_ROUND_UP(timings->tCKESR, t_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) val = max(min_tck->tCKESR, val) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) tim3 |= val << T_CKESR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ip_rev == EMIF_4D5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tim3 |= val << T_PDLL_UL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return tim3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bool cs1_used, bool cal_resistors_per_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 zq = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) zq |= val << ZQ_REFINTERVAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) zq |= val << ZQ_ZQCL_MULT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) zq |= val << ZQ_ZQINIT_MULT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (cal_resistors_per_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val = cs1_used ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) zq |= val << ZQ_CS1EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return zq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) const struct emif_custom_configs *custom_configs, bool cs1_used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 sdram_io_width, u32 emif_bus_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 alert = 0, interval, devcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (custom_configs && (custom_configs->mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) interval = custom_configs->temp_alert_poll_interval_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) interval *= 1000000; /* Convert to ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) interval /= addressing->tREFI_ns; /* Convert to refresh cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) alert |= (interval << TA_REFINTERVAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * also to this form and subtract to get TA_DEVCNT, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * in log2(x) form.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) emif_bus_width = __fls(emif_bus_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) devcnt = emif_bus_width - sdram_io_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) alert |= devcnt << TA_DEVCNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* DEVWDT is in 'log2(x) - 3' form */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) alert |= 1 << TA_SFEXITEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) alert |= 1 << TA_CS0EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return alert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 idle = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * Maximum value in normal conditions and increased frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * when voltage is ramping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (volt_ramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) val = 0x1FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * READ_IDLE_CTRL register in EMIF4D has same offset and fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) idle |= val << DLL_CALIB_INTERVAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 calib = 0, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (volt_ramp == DDR_VOLTAGE_RAMPING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val = 0; /* Disabled when voltage is stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) calib |= val << DLL_CALIB_INTERVAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return calib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 freq, u8 RL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) phy |= val << READ_LATENCY_SHIFT_4D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (freq <= 100000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) else if (freq <= 200000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * half-delay is not needed else set half-delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (freq >= 265000000 && freq < 267000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) half_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) half_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 fifo_we_slave_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) fifo_we_slave_ratio << 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 fifo_we_slave_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 fifo_we_slave_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) fifo_we_slave_ratio = DIV_ROUND_CLOSEST(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256, t_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) fifo_we_slave_ratio << 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 pwr_mgmt_ctrl = 0, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 lpmode = EMIF_LP_MODE_SELF_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) lpmode = cust_cfgs->lpmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) timeout_perf = cust_cfgs->lpmode_timeout_performance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) timeout_pwr = cust_cfgs->lpmode_timeout_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) freq_threshold = cust_cfgs->lpmode_freq_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Timeout based on DDR frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * The value to be set in register is "log2(timeout) - 3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * if timeout < 16 load 0 in register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * if timeout is not a power of 2, round to next highest power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (timeout < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (timeout & (timeout - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) timeout <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) timeout = __fls(timeout) - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) switch (lpmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case EMIF_LP_MODE_CLOCK_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) shift = CS_TIM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mask = CS_TIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case EMIF_LP_MODE_SELF_REFRESH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Workaround for errata i735 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (timeout < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) timeout = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) shift = SR_TIM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mask = SR_TIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case EMIF_LP_MODE_PWR_DN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) shift = PD_TIM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mask = PD_TIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case EMIF_LP_MODE_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Round to maximum in case of overflow, BUT warn! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) lpmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) timeout_perf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) timeout_pwr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) freq_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) timeout, mask >> shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) timeout = mask >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Setup required timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pwr_mgmt_ctrl = (timeout << shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* setup a default mask for rest of the modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* No CS_TIM in EMIF_4D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ip_rev == EMIF_4D5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pwr_mgmt_ctrl &= ~CS_TIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return pwr_mgmt_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * Get the temperature level of the EMIF instance:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * Reads the MR4 register of attached SDRAM parts to find out the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * level. If there are two parts attached(one on each CS), then the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * level for the EMIF instance is the higher of the two temperatures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void get_temperature_level(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 temp, temperature_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Read mode register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) MR4_SDRAM_REF_RATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (emif->plat_data->device_info->cs1_used) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) temp = (temp & MR4_SDRAM_REF_RATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) >> MR4_SDRAM_REF_RATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) temperature_level = max(temp, temperature_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* treat everything less than nominal(3) in MR4 as nominal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) temperature_level = SDRAM_TEMP_NOMINAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* if we get reserved value in MR4 persist with the existing value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) emif->temperature_level = temperature_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * Program EMIF shadow registers that are not dependent on temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * or voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) writel(regs->pwr_mgmt_ctrl_shdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Settings specific for EMIF4D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (emif->plat_data->ip_rev != EMIF_4D5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * When voltage ramps dll calibration and forced read idle should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * happen more often
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static void setup_volt_sensitive_regs(struct emif_data *emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct emif_regs *regs, u32 volt_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 calib_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * is an alias of the respective read_idle_ctrl_shdw_* (members of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * a union). So, the below code takes care of both cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (volt_state == DDR_VOLTAGE_RAMPING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * setup_temperature_sensitive_regs() - set the timings for temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * sensitive registers. This happens once at initialisation time based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * on the temperature at boot time and subsequently based on the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * alert interrupt. Temperature alert can happen when the temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * increases or drops. So this function can have the effect of either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * derating the timings or going back to nominal values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static void setup_temperature_sensitive_regs(struct emif_data *emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct emif_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 tim1, tim3, ref_ctrl, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 temperature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) type = emif->plat_data->device_info->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) tim1 = regs->sdram_tim1_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) tim3 = regs->sdram_tim3_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ref_ctrl = regs->ref_ctrl_shdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* No de-rating for non-lpddr2 devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) temperature = emif->temperature_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ref_ctrl = regs->ref_ctrl_shdw_derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) tim1 = regs->sdram_tim1_shdw_derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) tim3 = regs->sdram_tim3_shdw_derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ref_ctrl = regs->ref_ctrl_shdw_derated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u32 old_temp_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct emif_custom_configs *custom_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) spin_lock_irqsave(&emif_lock, irq_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) old_temp_level = emif->temperature_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) get_temperature_level(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (unlikely(emif->temperature_level == old_temp_level)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) } else if (!emif->curr_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) custom_configs = emif->plat_data->custom_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * IF we detect higher than "nominal rating" from DDR sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * on an unsupported DDR part, shutdown system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (custom_configs && !(custom_configs->mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(emif->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "%s:NOT Extended temperature capable memory. Converting MR4=0x%02x as shutdown event\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) __func__, emif->temperature_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Temperature far too high - do kernel_power_off()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * from thread context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (emif->temperature_level < old_temp_level ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * Temperature coming down - defer handling to thread OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * Temperature far too high - do kernel_power_off() from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * thread context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* Temperature is going up - handle immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) setup_temperature_sensitive_regs(emif, emif->curr_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) do_freq_update();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) spin_unlock_irqrestore(&emif_lock, irq_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u32 interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct emif_data *emif = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct device *dev = emif->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Save the status and clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Handle temperature alert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * Temperature alert should be same for all ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * So, it's enough to process it only for one of the ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (interrupts & TA_SYS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret = handle_temp_alert(base, emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (interrupts & ERR_SYS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dev_err(dev, "Access error from SYS port - %x\n", interrupts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Save the status and clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (interrupts & ERR_LL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) dev_err(dev, "Access error from LL port - %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) interrupts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct emif_data *emif = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* If we have Power OFF ability, use it, else try restarting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (pm_power_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) kernel_power_off();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) kernel_restart("SDRAM Over-temp Emergency restart");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) spin_lock_irqsave(&emif_lock, irq_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (emif->curr_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) setup_temperature_sensitive_regs(emif, emif->curr_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) do_freq_update();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) spin_unlock_irqrestore(&emif_lock, irq_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static void clear_all_interrupts(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) base + EMIF_LL_OCP_INTERRUPT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static void disable_and_clear_all_interrupts(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) clear_all_interrupts(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u32 interrupts, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) type = emif->plat_data->device_info->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) clear_all_interrupts(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* Enable interrupts for SYS interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) interrupts = EN_ERR_SYS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) interrupts |= EN_TA_SYS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* Enable interrupts for LL interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* TA need not be enabled for LL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) interrupts = EN_ERR_LL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* setup IRQ handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return devm_request_threaded_irq(emif->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) emif_interrupt_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) emif_threaded_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) 0, dev_name(emif->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void __init_or_module emif_onetime_settings(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u32 pwr_mgmt_ctrl, zq, temp_alert_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) void __iomem *base = emif->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) const struct lpddr2_addressing *addressing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) const struct ddr_device_info *device_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) device_info = emif->plat_data->device_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) addressing = get_addressing_table(device_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * Init power management settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * We don't know the frequency yet. Use a high frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * value for a conservative timeout setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) emif->plat_data->ip_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* Init ZQ calibration settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) zq = get_zq_config_reg(addressing, device_info->cs1_used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) device_info->cal_resistors_per_cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* Check temperature level temperature level*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) get_temperature_level(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* Init temperature polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) temp_alert_cfg = get_temp_alert_config(addressing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) emif->plat_data->custom_configs, device_info->cs1_used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) device_info->io_width, get_emif_bus_width(emif));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * Program external PHY control registers that are not frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static void get_default_timings(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct emif_platform_data *pd = emif->plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pd->timings = lpddr2_jedec_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dev_warn(emif->dev, "%s: using default timings\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u32 ip_rev, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) int valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) valid = (type == DDR_TYPE_LPDDR2_S4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) type == DDR_TYPE_LPDDR2_S2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) && (density >= DDR_DENSITY_64Mb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) && density <= DDR_DENSITY_8Gb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) && (io_width >= DDR_IO_WIDTH_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) && io_width <= DDR_IO_WIDTH_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Combinations of EMIF and PHY revisions that we support today */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) switch (ip_rev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case EMIF_4D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) case EMIF_4D5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (!valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dev_err(dev, "%s: invalid DDR details\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) int valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) valid = cust_cfgs->lpmode_freq_threshold &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) cust_cfgs->lpmode_timeout_performance &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) cust_cfgs->lpmode_timeout_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (!valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dev_warn(dev, "%s: invalid custom configs\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct emif_custom_configs *cust_cfgs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) const __be32 *lpmode, *poll_intvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) lpmode = of_get_property(np_emif, "low-power-mode", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (lpmode || poll_intvl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (!cust_cfgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (lpmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) cust_cfgs->lpmode = be32_to_cpup(lpmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) of_property_read_u32(np_emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "low-power-mode-timeout-performance",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) &cust_cfgs->lpmode_timeout_performance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) of_property_read_u32(np_emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) "low-power-mode-timeout-power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) &cust_cfgs->lpmode_timeout_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) of_property_read_u32(np_emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) "low-power-mode-freq-threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) &cust_cfgs->lpmode_freq_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (poll_intvl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) cust_cfgs->mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) cust_cfgs->temp_alert_poll_interval_ms =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) be32_to_cpup(poll_intvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (of_find_property(np_emif, "extended-temp-part", &len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) devm_kfree(emif->dev, cust_cfgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) emif->plat_data->custom_configs = cust_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct device_node *np_ddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct ddr_device_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u32 density = 0, io_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (of_find_property(np_emif, "cs1-used", &len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_info->cs1_used = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) dev_info->cal_resistors_per_cs = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s4"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_info->type = DDR_TYPE_LPDDR2_S4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) else if (of_device_is_compatible(np_ddr, "jedec,lpddr2-s2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) dev_info->type = DDR_TYPE_LPDDR2_S2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) of_property_read_u32(np_ddr, "density", &density);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) of_property_read_u32(np_ddr, "io-width", &io_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* Convert from density in Mb to the density encoding in jedc_ddr.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (density & (density - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_info->density = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_info->density = __fls(density) - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (io_width & (io_width - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) dev_info->io_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_info->io_width = __fls(io_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static struct emif_data * __init_or_module of_get_memory_device_details(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct device_node *np_emif, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct emif_data *emif = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct ddr_device_info *dev_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct emif_platform_data *pd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct device_node *np_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (!np_ddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (!emif || !pd || !dev_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_err(dev, "%s: Out of memory!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) emif->plat_data = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pd->device_info = dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) emif->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) emif->np_ddr = np_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) emif->temperature_level = SDRAM_TEMP_NOMINAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (of_device_is_compatible(np_emif, "ti,emif-4d"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) emif->plat_data->ip_rev = EMIF_4D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) emif->plat_data->ip_rev = EMIF_4D5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) of_get_ddr_info(np_emif, np_ddr, dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) pd->device_info->io_width, pd->phy_type, pd->ip_rev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) emif->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) dev_err(dev, "%s: invalid device data!!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * For EMIF instances other than EMIF1 see if the devices connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * are exactly same as on EMIF1(which is typically the case). If so,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * mark it as a duplicate of EMIF1. This will save some memory and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * computation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (emif1 && emif1->np_ddr == np_ddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) emif->duplicate = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) } else if (emif1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) of_get_custom_configs(np_emif, emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) emif->plat_data->device_info->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) &emif->plat_data->timings_arr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static struct emif_data * __init_or_module of_get_memory_device_details(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct device_node *np_emif, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static struct emif_data *__init_or_module get_device_details(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct emif_data *emif = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct ddr_device_info *dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct emif_custom_configs *cust_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct emif_platform_data *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) pd = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) pd->device_info->density, pd->device_info->io_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) pd->phy_type, pd->ip_rev, dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dev_err(dev, "%s: invalid device data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (!emif || !temp || !dev_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) memcpy(temp, pd, sizeof(*pd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pd = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) memcpy(dev_info, pd->device_info, sizeof(*dev_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) pd->device_info = dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) emif->plat_data = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) emif->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) emif->temperature_level = SDRAM_TEMP_NOMINAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * For EMIF instances other than EMIF1 see if the devices connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * are exactly same as on EMIF1(which is typically the case). If so,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * mark it as a duplicate of EMIF1 and skip copying timings data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * This will save some memory and some computation later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) emif->duplicate = emif1 && (memcmp(dev_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) emif1->plat_data->device_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) sizeof(struct ddr_device_info)) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (emif->duplicate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) pd->timings = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) pd->min_tck = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) } else if (emif1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * Copy custom configs - ignore allocation error, if any, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * custom_configs is not very critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) cust_cfgs = pd->custom_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) dev_warn(dev, "%s:%d: allocation error\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) pd->custom_configs = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * Copy timings and min-tck values from platform data. If it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * available or if memory allocation fails, use JEDEC defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (pd->timings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) temp = devm_kzalloc(dev, size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) memcpy(temp, pd->timings, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) pd->timings = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) dev_warn(dev, "%s:%d: allocation error\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) get_default_timings(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) get_default_timings(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (pd->min_tck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) pd->min_tck = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dev_warn(dev, "%s:%d: allocation error\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) pd->min_tck = &lpddr2_jedec_min_tck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) pd->min_tck = &lpddr2_jedec_min_tck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static int __init_or_module emif_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct emif_data *emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) emif = get_device_details(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (!emif) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) pr_err("%s: error getting device data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) list_add(&emif->node, &device_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) emif->addressing = get_addressing_table(emif->plat_data->device_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* Save pointers to each other in emif and device structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) emif->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) platform_set_drvdata(pdev, emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) emif->base = devm_ioremap_resource(emif->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (IS_ERR(emif->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) emif_onetime_settings(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) emif_debugfs_init(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) disable_and_clear_all_interrupts(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ret = setup_interrupts(emif, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* One-time actions taken on probing the first device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (!emif1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) emif1 = emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) spin_lock_init(&emif_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * TODO: register notifiers for frequency and voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * change here once the respective frameworks are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) __func__, emif->base, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static int __exit emif_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct emif_data *emif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) emif_debugfs_exit(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static void emif_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) struct emif_data *emif = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) disable_and_clear_all_interrupts(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static int get_emif_reg_values(struct emif_data *emif, u32 freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) struct emif_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) u32 ip_rev, phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) u32 cl, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) const struct lpddr2_timings *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) const struct lpddr2_min_tck *min_tck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) const struct ddr_device_info *device_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) const struct lpddr2_addressing *addressing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct emif_data *emif_for_calc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) dev = emif->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * If the devices on this EMIF instance is duplicate of EMIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * use EMIF1 details for the calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) emif_for_calc = emif->duplicate ? emif1 : emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) timings = get_timings_table(emif_for_calc, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) addressing = emif_for_calc->addressing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (!timings || !addressing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) dev_err(dev, "%s: not enough data available for %dHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) device_info = emif_for_calc->plat_data->device_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) type = device_info->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ip_rev = emif_for_calc->plat_data->ip_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) phy_type = emif_for_calc->plat_data->phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) min_tck = emif_for_calc->plat_data->min_tck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) set_ddr_clk_period(freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) addressing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) addressing, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) cl = get_cl(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) timings, freq, cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* Only timeout values in pwr_mgmt_ctrl_shdw register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) regs->pwr_mgmt_ctrl_shdw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (ip_rev & EMIF_4D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) regs->read_idle_ctrl_shdw_normal =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) regs->read_idle_ctrl_shdw_volt_ramp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) } else if (ip_rev & EMIF_4D5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) regs->dll_calib_ctrl_shdw_normal =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) regs->dll_calib_ctrl_shdw_volt_ramp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) addressing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) regs->sdram_tim1_shdw_derated =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) get_sdram_tim_1_shdw_derated(timings, min_tck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) addressing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) min_tck, addressing, type, ip_rev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) EMIF_DERATED_TIMINGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) regs->freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * get_regs() - gets the cached emif_regs structure for a given EMIF instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) * given frequency(freq):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * As an optimisation, every EMIF instance other than EMIF1 shares the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * register cache with EMIF1 if the devices connected on this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * are same as that on EMIF1(indicated by the duplicate flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * If we do not have an entry corresponding to the frequency given, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * allocate a new entry and calculate the values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * Upon finding the right reg dump, save it in curr_regs. It can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * directly used for thermal de-rating and voltage ramping changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct emif_regs **regs_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) struct emif_regs *regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) dev = emif->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (emif->curr_regs && emif->curr_regs->freq == freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return emif->curr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (emif->duplicate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) regs_cache = emif1->regs_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) regs_cache = emif->regs_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (regs_cache[i]->freq == freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) regs = regs_cache[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) "%s: reg dump found in reg cache for %u Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) __func__, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * If we don't have an entry for this frequency in the cache create one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * and calculate the values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (get_emif_reg_values(emif, freq, regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) devm_kfree(emif->dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * Now look for an un-used entry in the cache and save the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * newly created struct. If there are no free entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) * over-write the last entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (i >= EMIF_MAX_NUM_FREQUENCIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) i = EMIF_MAX_NUM_FREQUENCIES - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) devm_kfree(emif->dev, regs_cache[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) regs_cache[i] = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) volt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (!emif->curr_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) dev_err(emif->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) "%s: volt-notify before registers are ready: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) __func__, volt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * TODO: voltage notify handling should be hooked up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * regulator framework as soon as the necessary support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * is available in mainline kernel. This function is un-used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * right now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct emif_data *emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) spin_lock_irqsave(&emif_lock, irq_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) list_for_each_entry(emif, &device_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) do_volt_notify_handling(emif, volt_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) do_freq_update();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) spin_unlock_irqrestore(&emif_lock, irq_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct emif_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) regs = get_regs(emif, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) emif->curr_regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * Update the shadow registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * Temperature and voltage-ramp sensitive settings are also configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * in terms of DDR cycles. So, we need to update them too when there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * is a freq change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) __func__, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) setup_registers(emif, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) setup_temperature_sensitive_regs(emif, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * Part of workaround for errata i728. See do_freq_update()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) * for more details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) set_lpmode(emif, EMIF_LP_MODE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * TODO: frequency notify handling should be hooked up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * clock framework as soon as the necessary support is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) * available in mainline kernel. This function is un-used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * right now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) struct emif_data *emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * NOTE: we are taking the spin-lock here and releases it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * only in post-notifier. This doesn't look good and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) * Sparse complains about it, but this seems to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * un-avoidable. We need to lock a sequence of events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) * that is split between EMIF and clock framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * 1. EMIF driver updates EMIF timings in shadow registers in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * frequency pre-notify callback from clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * 2. clock framework sets up the registers for the new frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * 3. clock framework initiates a hw-sequence that updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * the frequency EMIF timings synchronously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * All these 3 steps should be performed as an atomic operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * vis-a-vis similar sequence in the EMIF interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) * for temperature events. Otherwise, there could be race
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) * conditions that could result in incorrect EMIF timings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * a given frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) spin_lock_irqsave(&emif_lock, irq_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) list_for_each_entry(emif, &device_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) do_freq_pre_notify_handling(emif, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static void do_freq_post_notify_handling(struct emif_data *emif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * Part of workaround for errata i728. See do_freq_update()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * for more details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * TODO: frequency notify handling should be hooked up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) * clock framework as soon as the necessary support is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) * available in mainline kernel. This function is un-used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) * right now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static void __attribute__((unused)) freq_post_notify_handling(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) struct emif_data *emif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) list_for_each_entry(emif, &device_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) do_freq_post_notify_handling(emif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * Lock is done in pre-notify handler. See freq_pre_notify_handling()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) * for more details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) spin_unlock_irqrestore(&emif_lock, irq_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static const struct of_device_id emif_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) { .compatible = "ti,emif-4d" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) { .compatible = "ti,emif-4d5" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) MODULE_DEVICE_TABLE(of, emif_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static struct platform_driver emif_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .remove = __exit_p(emif_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .shutdown = emif_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .name = "emif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .of_match_table = of_match_ptr(emif_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) module_platform_driver_probe(emif_driver, emif_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) MODULE_ALIAS("platform:emif");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) MODULE_AUTHOR("Texas Instruments Inc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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