^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI da8xx DDR2/mDDR controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 BayLibre SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Bartosz Golaszewski <bgolaszewski@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * REVISIT: Linux doesn't have a good framework for the kind of performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * knobs this driver controls. We can't use device tree properties as it deals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * with hardware configuration rather than description. We also don't want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * commit to maintaining some random sysfs attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * For now we just hardcode the register values for the boards that need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * some changes (as is the case for the LCD controller on da850-lcdk - the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * first board we support here). When linux gets an appropriate framework,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * we'll easily convert the driver to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct da8xx_ddrctl_config_knob {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct da8xx_ddrctl_config_knob da8xx_ddrctl_knobs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = "da850-pbbpr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .reg = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .mask = 0xffffff00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct da8xx_ddrctl_setting {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct da8xx_ddrctl_board_settings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const char *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const struct da8xx_ddrctl_setting *settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct da8xx_ddrctl_setting da850_lcdk_ddrctl_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = "da850-pbbpr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .val = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct da8xx_ddrctl_board_settings da8xx_ddrctl_board_confs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .board = "ti,da850-lcdk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .settings = da850_lcdk_ddrctl_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct da8xx_ddrctl_config_knob *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) da8xx_ddrctl_match_knob(const struct da8xx_ddrctl_setting *setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct da8xx_ddrctl_config_knob *knob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for (i = 0; i < ARRAY_SIZE(da8xx_ddrctl_knobs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) knob = &da8xx_ddrctl_knobs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (strcmp(knob->name, setting->name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return knob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct da8xx_ddrctl_setting *da8xx_ddrctl_get_board_settings(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const struct da8xx_ddrctl_board_settings *board_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (i = 0; i < ARRAY_SIZE(da8xx_ddrctl_board_confs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) board_settings = &da8xx_ddrctl_board_confs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (of_machine_is_compatible(board_settings->board))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return board_settings->settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int da8xx_ddrctl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct da8xx_ddrctl_config_knob *knob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const struct da8xx_ddrctl_setting *setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void __iomem *ddrctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) setting = da8xx_ddrctl_get_board_settings();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!setting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(dev, "no settings defined for this board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ddrctl = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (IS_ERR(ddrctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(dev, "unable to map memory controller registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return PTR_ERR(ddrctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) for (; setting->name; setting++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) knob = da8xx_ddrctl_match_knob(setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!knob) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "no such config option: %s\n", setting->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (knob->reg + sizeof(u32) > resource_size(res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "register offset of '%s' exceeds mapped memory size\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) knob->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) reg = readl(ddrctl + knob->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) reg &= knob->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg |= setting->val << knob->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_dbg(dev, "writing 0x%08x to %s\n", reg, setting->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(reg, ddrctl + knob->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct of_device_id da8xx_ddrctl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .compatible = "ti,da850-ddr-controller", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct platform_driver da8xx_ddrctl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .probe = da8xx_ddrctl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "da850-ddr-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .of_match_table = da8xx_ddrctl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) module_platform_driver(da8xx_ddrctl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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