^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This driver provides access to the DPFE interface of Broadcom STB SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The firmware running on the DCPU inside the DDR PHY can provide current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * information about the system's RAM, for instance the DRAM refresh rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This can be used as an indirect indicator for the DRAM's temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Slower refresh rate means cooler RAM, higher refresh rate means hotter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Note regarding the loading of the firmware image: we use be32_to_cpu()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * and le_32_to_cpu(), so we can support the following four cases:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - LE kernel + LE firmware image (the most common case)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - LE kernel + BE firmware image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - BE kernel + LE firmware image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - BE kernel + BE firmware image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * The DPCU always runs in big endian mode. The firmware image, however, can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * be in either format. Also, communication between host CPU and DCPU is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * always in little endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRVNAME "brcmstb-dpfe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* DCPU register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_DCPU_RESET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_TO_DCPU_MBOX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_TO_HOST_MBOX 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Macros to process offsets returned by the DCPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRAM_MSG_ADDR_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRAM_MSG_TYPE_OFFSET 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DRAM_MSG_TYPE_MASK ((1UL << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Message RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DCPU_MSG_RAM_START 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DCPU_MSG_RAM(x) (DCPU_MSG_RAM_START + (x) * sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* DRAM Info Offsets & Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DRAM_INFO_INTERVAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DRAM_INFO_MR4 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRAM_INFO_ERROR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRAM_INFO_MR4_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRAM_INFO_MR4_SHIFT 24 /* We need to look at byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* DRAM MR4 Offsets & Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRAM_MR4_REFRESH 0x0 /* Refresh rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DRAM_MR4_REFRESH_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRAM_MR4_SR_ABORT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DRAM_MR4_PPRE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DRAM_MR4_TH_OFFS_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DRAM_MR4_TUF_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* DRAM Vendor Offsets & Masks (API v2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DRAM_VENDOR_MR5 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DRAM_VENDOR_MR6 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DRAM_VENDOR_MR7 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DRAM_VENDOR_MR8 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DRAM_VENDOR_ERROR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DRAM_VENDOR_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DRAM_VENDOR_SHIFT 24 /* We need to look at byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* DRAM Information Offsets & Masks (API v3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DRAM_DDR_INFO_MR4 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DRAM_DDR_INFO_MR5 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DRAM_DDR_INFO_MR6 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DRAM_DDR_INFO_MR7 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DRAM_DDR_INFO_MR8 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DRAM_DDR_INFO_ERROR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DRAM_DDR_INFO_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Reset register bits & masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DCPU_RESET_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DCPU_RESET_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DCPU_CLK_DISABLE_SHIFT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* DCPU return codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DCPU_RET_ERROR_BIT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DCPU_RET_SUCCESS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* This error code is not firmware defined and only used in the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Firmware magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DPFE_BE_MAGIC 0xfe1010fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DPFE_LE_MAGIC 0xfe0101fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Error codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ERR_INVALID_MAGIC -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ERR_INVALID_SIZE -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ERR_INVALID_CHKSUM -3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Message types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DPFE_MSG_TYPE_COMMAND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DPFE_MSG_TYPE_RESPONSE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DELAY_LOOP_MAX 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum dpfe_msg_fields {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MSG_HEADER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MSG_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MSG_ARG_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MSG_ARG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MSG_FIELD_MAX = 16 /* Max number of arguments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum dpfe_commands {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DPFE_CMD_GET_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DPFE_CMD_GET_REFRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DPFE_CMD_GET_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DPFE_CMD_MAX /* Last entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Format of the binary firmware file:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * 0 header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * value: 0xfe0101fe <== little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * 0xfe1010fe <== big endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * 1 sequence:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * [31:16] total segments on this build
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * [15:0] this segment sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * 2 FW version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * 3 IMEM byte size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * 4 DMEM byte size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * IMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * DMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * last checksum ==> sum of everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct dpfe_firmware_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 imem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 dmem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Things we only need during initialization. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int dmem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int imem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bool is_big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* API version and corresponding commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct dpfe_api {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *fw_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct attribute_group **sysfs_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Things we need for as long as we are active. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct brcmstb_dpfe_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void __iomem *dmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *imem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct dpfe_api *dpfe_api;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Forward declaration of our sysfs attribute functions, so we can declare the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * attribute data structures early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static ssize_t show_info(struct device *, struct device_attribute *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static ssize_t show_refresh(struct device *, struct device_attribute *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static ssize_t store_refresh(struct device *, struct device_attribute *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const char *, size_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static ssize_t show_vendor(struct device *, struct device_attribute *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static ssize_t show_dram(struct device *, struct device_attribute *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Declare our attributes early, so they can be referenced in the API data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * structure. We need to do this, because the attributes depend on the API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* API v2 sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static struct attribute *dpfe_v2_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) &dev_attr_dpfe_info.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) &dev_attr_dpfe_refresh.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &dev_attr_dpfe_vendor.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ATTRIBUTE_GROUPS(dpfe_v2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* API v3 sysfs attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct attribute *dpfe_v3_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) &dev_attr_dpfe_info.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) &dev_attr_dpfe_dram.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ATTRIBUTE_GROUPS(dpfe_v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Old API v2 firmware commands, as defined in the rev 0.61 specification, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * use a version set to 1 to denote that it is not compatible with the new API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * v2 and onwards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct dpfe_api dpfe_api_old_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .version = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .fw_name = "dpfe.bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .sysfs_attrs = dpfe_v2_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .command = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [DPFE_CMD_GET_INFO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [MSG_COMMAND] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [MSG_ARG_COUNT] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [MSG_ARG0] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [DPFE_CMD_GET_REFRESH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [MSG_COMMAND] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [MSG_ARG_COUNT] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [MSG_ARG0] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [DPFE_CMD_GET_VENDOR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [MSG_COMMAND] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [MSG_ARG_COUNT] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [MSG_ARG0] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * API v2 firmware commands, as defined in the rev 0.8 specification, named new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * v2 here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct dpfe_api dpfe_api_new_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .version = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .fw_name = NULL, /* We expect the firmware to have been downloaded! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .sysfs_attrs = dpfe_v2_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .command = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [DPFE_CMD_GET_INFO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [MSG_COMMAND] = 0x101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [DPFE_CMD_GET_REFRESH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [MSG_COMMAND] = 0x201,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [DPFE_CMD_GET_VENDOR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [MSG_COMMAND] = 0x202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* API v3 firmware commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct dpfe_api dpfe_api_v3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .version = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .fw_name = NULL, /* We expect the firmware to have been downloaded! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .sysfs_attrs = dpfe_v3_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .command = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [DPFE_CMD_GET_INFO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [MSG_COMMAND] = 0x0101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [MSG_ARG_COUNT] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [MSG_ARG0] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [DPFE_CMD_GET_REFRESH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [MSG_COMMAND] = 0x0202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [MSG_ARG_COUNT] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* There's no GET_VENDOR command in API v3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const char *get_error_text(unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const char * const error_text[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "Success", "Header code incorrect",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "Unknown command or argument", "Incorrect checksum",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "Malformed command", "Timed out", "Unknown error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (unlikely(i >= ARRAY_SIZE(error_text)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) i = ARRAY_SIZE(error_text) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return error_text[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val = readl_relaxed(priv->regs + REG_DCPU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return !(val & DCPU_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void __disable_dcpu(struct brcmstb_dpfe_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!is_dcpu_enabled(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Put DCPU in reset if it's running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) val = readl_relaxed(priv->regs + REG_DCPU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val |= (1 << DCPU_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel_relaxed(val, priv->regs + REG_DCPU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static void __enable_dcpu(struct brcmstb_dpfe_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Clear mailbox registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel_relaxed(0, regs + REG_TO_HOST_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Disable DCPU clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) val = readl_relaxed(regs + REG_DCPU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) val &= ~(1 << DCPU_CLK_DISABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) writel_relaxed(val, regs + REG_DCPU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Take DCPU out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) val = readl_relaxed(regs + REG_DCPU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val &= ~(1 << DCPU_RESET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel_relaxed(val, regs + REG_DCPU_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static unsigned int get_msg_chksum(const u32 msg[], unsigned int max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Don't include the last field in the checksum. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) for (i = 0; i < max; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sum += msg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) char *buf, ssize_t *size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) void __iomem *ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* There is no need to use this function for API v3 or later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (unlikely(priv->dpfe_api->version >= 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * msg_type == 1: the offset is relative to the message RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * msg_type == 0: the offset is relative to the data RAM (this is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * previous way of passing data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * msg_type is anything else: there's critical hardware problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) switch (msg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ptr = priv->regs + DCPU_MSG_RAM_START + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ptr = priv->dmem + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (buf && size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *size = sprintf(buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "FATAL: communication error with DCPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void __finalize_command(struct brcmstb_dpfe_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int release_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * It depends on the API version which MBOX register we have to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * to signal we are done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) release_mbox = (priv->dpfe_api->version < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writel_relaxed(0, priv->regs + release_mbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 result[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) const u32 *msg = priv->dpfe_api->command[cmd];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) void __iomem *regs = priv->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int i, chksum, chksum_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (cmd >= DPFE_CMD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Wait for DCPU to become ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (i = 0; i < DELAY_LOOP_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (resp == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (resp != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -ffs(DCPU_RET_ERR_TIMEDOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Compute checksum over the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) chksum_idx = msg[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) chksum = get_msg_chksum(msg, chksum_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Write command and arguments to message area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) for (i = 0; i < MSG_FIELD_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (i == chksum_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) writel_relaxed(chksum, regs + DCPU_MSG_RAM(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Tell DCPU there is a command waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writel_relaxed(1, regs + REG_TO_DCPU_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Wait for DCPU to process the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) for (i = 0; i < DELAY_LOOP_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Read response code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) resp = readl_relaxed(regs + REG_TO_HOST_MBOX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (resp > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (i == DELAY_LOOP_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = -ffs(resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Read response data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) for (i = 0; i < MSG_FIELD_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Tell DCPU we are done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) __finalize_command(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Verify response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) chksum = get_msg_chksum(result, chksum_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (chksum != result[chksum_idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) resp = DCPU_RET_ERR_CHKSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (resp != DCPU_RET_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) resp &= ~DCPU_RET_ERROR_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = -ffs(resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Ensure that the firmware file loaded meets all the requirements. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int __verify_firmware(struct init_data *init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct dpfe_firmware_header *header = (void *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int dmem_size, imem_size, total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) bool is_big_endian = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) const u32 *chksum_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (header->magic == DPFE_BE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) is_big_endian = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) else if (header->magic != DPFE_LE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return ERR_INVALID_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (is_big_endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dmem_size = be32_to_cpu(header->dmem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) imem_size = be32_to_cpu(header->imem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dmem_size = le32_to_cpu(header->dmem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) imem_size = le32_to_cpu(header->imem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Data and instruction sections are 32 bit words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ERR_INVALID_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * The header + the data section + the instruction section + the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * checksum must be equal to the total firmware size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) total_size = dmem_size + imem_size + sizeof(*header) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) sizeof(*chksum_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (total_size != fw->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ERR_INVALID_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* The checksum comes at the very end. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) init->is_big_endian = is_big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) init->dmem_len = dmem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) init->imem_len = imem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) init->chksum = (is_big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Verify checksum by reading back the firmware from co-processor RAM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int __verify_fw_checksum(struct init_data *init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct brcmstb_dpfe_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) const struct dpfe_firmware_header *header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 checksum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 magic, sequence, version, sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 __iomem *dmem = priv->dmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 __iomem *imem = priv->imem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (init->is_big_endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) magic = be32_to_cpu(header->magic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) sequence = be32_to_cpu(header->sequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) version = be32_to_cpu(header->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) magic = le32_to_cpu(header->magic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sequence = le32_to_cpu(header->sequence);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) version = le32_to_cpu(header->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) sum = magic + sequence + version + init->dmem_len + init->imem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) for (i = 0; i < init->dmem_len / sizeof(u32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) sum += readl_relaxed(dmem + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) for (i = 0; i < init->imem_len / sizeof(u32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) sum += readl_relaxed(imem + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return (sum == checksum) ? 0 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int __write_firmware(u32 __iomem *mem, const u32 *fw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int size, bool is_big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Convert size to 32-bit words. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) size /= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* It is recommended to clear the firmware area first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) writel_relaxed(0, mem + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Now copy it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (is_big_endian) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writel_relaxed(be32_to_cpu(fw[i]), mem + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) writel_relaxed(le32_to_cpu(fw[i]), mem + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) const struct dpfe_firmware_header *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned int dmem_size, imem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) bool is_big_endian = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) const u32 *dmem, *imem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) const void *fw_blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Skip downloading the firmware if the DCPU is already running and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * responding to commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (is_dcpu_enabled(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 response[MSG_FIELD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = __send_command(priv, DPFE_CMD_GET_INFO, response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * If the firmware filename is NULL it means the boot firmware has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * download the DCPU firmware for us. If that didn't work, we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * bail, since downloading it ourselves wouldn't work either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!priv->dpfe_api->fw_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = firmware_request_nowarn(&fw, priv->dpfe_api->fw_name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * Defer the firmware download if the firmware file couldn't be found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * The root file system may not be available yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return (ret == -ENOENT) ? -EPROBE_DEFER : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = __verify_firmware(&init, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto release_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) __disable_dcpu(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) is_big_endian = init.is_big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dmem_size = init.dmem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) imem_size = init.imem_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* At the beginning of the firmware blob is a header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) header = (struct dpfe_firmware_header *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Void pointer to the beginning of the actual firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) fw_blob = fw->data + sizeof(*header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* IMEM comes right after the header. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) imem = fw_blob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* DMEM follows after IMEM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dmem = fw_blob + imem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) goto release_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) goto release_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = __verify_fw_checksum(&init, priv, header, init.chksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) goto release_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __enable_dcpu(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) release_fw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static ssize_t generic_show(unsigned int command, u32 response[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct brcmstb_dpfe_priv *priv, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return sprintf(buf, "ERROR: driver private data not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = __send_command(priv, command, response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return sprintf(buf, "ERROR: %s\n", get_error_text(-ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u32 response[MSG_FIELD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct brcmstb_dpfe_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned int info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) info = response[MSG_ARG0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return sprintf(buf, "%u.%u.%u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (info >> 24) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (info >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (info >> 8) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) info & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static ssize_t show_refresh(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct device_attribute *devattr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u32 response[MSG_FIELD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) void __iomem *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct brcmstb_dpfe_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u8 refresh, sr_abort, ppre, thermal_offs, tuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 mr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) DRAM_INFO_MR4_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) readl_relaxed(info + DRAM_INFO_INTERVAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) refresh, sr_abort, ppre, thermal_offs, tuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) readl_relaxed(info + DRAM_INFO_ERROR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 response[MSG_FIELD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct brcmstb_dpfe_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) void __iomem *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (kstrtoul(buf, 0, &val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) writel_relaxed(val, info + DRAM_INFO_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 response[MSG_FIELD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct brcmstb_dpfe_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) void __iomem *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 mr5, mr6, mr7, mr8, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) DRAM_VENDOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) DRAM_VENDOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DRAM_VENDOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) DRAM_VENDOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static ssize_t show_dram(struct device *dev, struct device_attribute *devattr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 response[MSG_FIELD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct brcmstb_dpfe_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 mr4, mr5, mr6, mr7, mr8, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mr8, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int brcmstb_dpfe_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct brcmstb_dpfe_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return brcmstb_dpfe_download_firmware(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int brcmstb_dpfe_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct brcmstb_dpfe_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) priv->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (IS_ERR(priv->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(dev, "couldn't map DCPU registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) priv->dmem = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (IS_ERR(priv->dmem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dev_err(dev, "Couldn't map DCPU data memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) priv->imem = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (IS_ERR(priv->imem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_err(dev, "Couldn't map DCPU instruction memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) priv->dpfe_api = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (unlikely(!priv->dpfe_api)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * It should be impossible to end up here, but to be safe we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * check anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_err(dev, "Couldn't determine API\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = brcmstb_dpfe_download_firmware(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return dev_err_probe(dev, ret, "Couldn't download firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dev_info(dev, "registered with API v%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) priv->dpfe_api->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int brcmstb_dpfe_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct of_device_id brcmstb_dpfe_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* Use legacy API v2 for a select number of chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) { .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_old_v2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) { .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_old_v2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) { .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_old_v2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) { .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_new_v2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* API v3 is the default going forward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) { .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static struct platform_driver brcmstb_dpfe_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .name = DRVNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .of_match_table = brcmstb_dpfe_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .probe = brcmstb_dpfe_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .remove = brcmstb_dpfe_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .resume = brcmstb_dpfe_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) module_platform_driver(brcmstb_dpfe_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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