^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) # Memory devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) menuconfig MEMORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) bool "Memory Controller drivers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) This option allows to enable specific memory controller drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) useful mostly on embedded systems. These could be controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) vary from memory tuning and frequency scaling to enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) access to attached peripherals through memory bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) if MEMORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) config DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Data from JEDEC specs for DDR SDRAM memories,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) particularly the AC timing parameters and addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) information. This data is useful for drivers handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DDR SDRAM controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) config ARM_PL172_MPMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) tristate "ARM PL172 MPMC driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) depends on ARM_AMBA && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) If you have an embedded system with an AMBA bus and a PL172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) controller, say Y or M here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) config ATMEL_SDRAMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bool "Atmel (Multi-port DDR-)SDRAM Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) default y if ARCH_AT91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) depends on ARCH_AT91 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) This driver is for Atmel SDRAM Controller or Atmel Multi-port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Starting with the at91sam9g45, this controller supports SDR, DDR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) LP-DDR memories.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) config ATMEL_EBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bool "Atmel EBI driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) default y if ARCH_AT91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) depends on ARCH_AT91 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) select MFD_ATMEL_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Driver for Atmel EBI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Used to configure the EBI (external bus interface) when the device-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tree is used. This bus supports NANDs, external ethernet controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SRAMs, ATA devices, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) config BRCMSTB_DPFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bool "Broadcom STB DPFE driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) default y if ARCH_BRCMSTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) depends on ARCH_BRCMSTB || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) This driver provides access to the DPFE interface of Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) STB SoCs. The firmware running on the DCPU inside the DDR PHY can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) provide current information about the system's RAM, for instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) the DRAM refresh rate. This can be used as an indirect indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for the DRAM's temperature. Slower refresh rate means cooler RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) higher refresh rate means hotter RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) config BT1_L2_CTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) depends on MIPS_BAIKAL_T1 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) resides Coherency Manager v2 with embedded 1MB L2-cache. It's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) possible to tune the L2 cache performance up by setting the data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tags and way-select latencies of RAM access. This driver provides a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dt properties-based and sysfs interface for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) config TI_AEMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tristate "Texas Instruments AEMIF driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) This driver is for the AEMIF module available in Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SoCs. AEMIF stands for Asynchronous External Memory Interface and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) is intended to provide a glue-less interface to a variety of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) of 256M bytes of any of these memories can be accessed at a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) time via four chip selects with 64M byte access per chip select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) config TI_EMIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tristate "Texas Instruments EMIF driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) depends on ARCH_OMAP2PLUS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) select DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) This driver is for the EMIF module available in Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SoCs. EMIF is an SDRAM controller that, based on its revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) This driver takes care of only LPDDR2 memories presently. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) functions of the driver includes re-configuring AC timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) parameters and other settings during frequency, voltage and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) temperature changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) config OMAP_GPMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bool "Texas Instruments OMAP SoC GPMC driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) depends on OF_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) select GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) This driver is for the General Purpose Memory Controller (GPMC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) interfacing to a variety of asynchronous as well as synchronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) memory drives like NOR, NAND, OneNAND, SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) config OMAP_GPMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool "Enable GPMC debug output and skip reset of GPMC during init"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) depends on OMAP_GPMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) Enables verbose debugging mostly to decode the bootloader provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) timings. To preserve the bootloader provided timings, the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) of GPMC is skipped during init. Enable this during development to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) configure devices connected to the GPMC bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) NOTE: In addition to matching the register setup with the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) you also need to match the GPMC FCLK frequency used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bootloader or else the GPMC timings won't be identical with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bootloader timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) config TI_EMIF_SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tristate "Texas Instruments EMIF SRAM driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) depends on SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) This driver is for the EMIF module available on Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) AM33XX and AM43XX SoCs and is required for PM. Certain parts of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) the EMIF PM code must run from on-chip SRAM late in the suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) sequence so this driver provides several relocatable PM functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) for the SoC PM code to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) config MVEBU_DEVBUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool "Marvell EBU Device Bus Controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default y if PLAT_ORION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) depends on PLAT_ORION || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) This driver is for the Device Bus controller available in some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) Armada 370 and Armada XP. This controller allows to handle flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) devices such as NOR, NAND, SRAM, and FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) config FSL_CORENET_CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tristate "Freescale CoreNet Error Reporting"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) depends on FSL_SOC_BOOKE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) Say Y for reporting of errors from the Freescale CoreNet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) Coherency Fabric. Errors reported include accesses to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) physical addresses that mapped by no local access window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (LAW) or an invalid LAW, as well as bad cache state that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) represents a coherency violation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) config FSL_IFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bool "Freescale IFC driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) config JZ4780_NEMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool "Ingenic JZ4780 SoC NEMC driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) depends on MIPS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) depends on HAS_IOMEM && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) This driver is for the NAND/External Memory Controller (NEMC) in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) the Ingenic JZ4780. This controller is used to handle external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) memory devices such as NAND and SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) config MTK_SMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tristate "MediaTek SoC Memory Controller driver" if COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) depends on ARCH_MEDIATEK || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) This driver is for the Memory Controller module in MediaTek SoCs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mainly help enable/disable iommu and control the power domain and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clocks for each local arbiter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) config DA8XX_DDRCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bool "Texas Instruments da8xx DDR2/mDDR driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) This driver is for the DDR2/mDDR Memory Controller present on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) Texas Instruments da8xx SoCs. It's used to tweak various memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) controller configuration options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) config PL353_SMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tristate "ARM PL35X Static Memory Controller(SMC) driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) default y if ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) depends on ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) depends on ARM_AMBA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) This driver is for the ARM PL351/PL353 Static Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) Controller(SMC) module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) config RENESAS_RPCIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) tristate "Renesas RPC-IF driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) depends on ARCH_RENESAS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) select REGMAP_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) This supports Renesas R-Car Gen3 RPC-IF which provides either SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) host or HyperFlash. You'll have to select individual components
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) under the corresponding menu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) config STM32_FMC2_EBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) depends on MACH_STM32MP157 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) Select this option to enable the STM32 FMC2 External Bus Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) controller. This driver configures the transactions with external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SOCs containing the FMC2 External Bus Interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) source "drivers/memory/samsung/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) source "drivers/memory/tegra/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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