^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // tm6000-stds.c - driver for TM5600/TM6000/TM6010 USB video capture devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright (c) 2007 Mauro Carvalho Chehab <mchehab@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "tm6000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "tm6000-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static unsigned int tm6010_a_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) module_param(tm6010_a_mode, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) MODULE_PARM_DESC(tm6010_a_mode, "set tm6010 sif audio mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct tm6000_reg_settings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) unsigned char req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct tm6000_std_settings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) v4l2_std_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct tm6000_reg_settings *common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct tm6000_reg_settings composite_pal_m[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct tm6000_reg_settings composite_pal_nc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct tm6000_reg_settings composite_pal[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct tm6000_reg_settings composite_secam[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct tm6000_reg_settings composite_ntsc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct tm6000_std_settings composite_stds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .id = V4L2_STD_PAL_M, .common = composite_pal_m, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .id = V4L2_STD_PAL_Nc, .common = composite_pal_nc, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .id = V4L2_STD_PAL, .common = composite_pal, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .id = V4L2_STD_SECAM, .common = composite_secam, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .id = V4L2_STD_NTSC, .common = composite_ntsc, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct tm6000_reg_settings svideo_pal_m[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct tm6000_reg_settings svideo_pal_nc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct tm6000_reg_settings svideo_pal[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct tm6000_reg_settings svideo_secam[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct tm6000_reg_settings svideo_ntsc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { TM6010_REQ07_R3F_RESET, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { TM6010_REQ07_R3F_RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 0, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct tm6000_std_settings svideo_stds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { .id = V4L2_STD_PAL_M, .common = svideo_pal_m, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { .id = V4L2_STD_PAL_Nc, .common = svideo_pal_nc, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { .id = V4L2_STD_PAL, .common = svideo_pal, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { .id = V4L2_STD_SECAM, .common = svideo_secam, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { .id = V4L2_STD_NTSC, .common = svideo_ntsc, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int tm6000_set_audio_std(struct tm6000_core *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) uint8_t areg_02 = 0x04; /* GC1 Fixed gain 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) uint8_t areg_05 = 0x01; /* Auto 4.5 = M Japan, Auto 6.5 = DK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) uint8_t areg_06 = 0x02; /* Auto de-emphasis, manual channel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (dev->radio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* set mono or stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (dev->amode == V4L2_TUNER_MODE_MONO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else if (dev->amode == V4L2_TUNER_MODE_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * STD/MN shouldn't be affected by tm6010_a_mode, as there's just one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * audio standard for each V4L2_STD type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if ((dev->norm & V4L2_STD_NTSC) == V4L2_STD_NTSC_M_KR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) areg_05 |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else if ((dev->norm & V4L2_STD_NTSC) == V4L2_STD_NTSC_M_JP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) areg_05 |= 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else if (dev->norm & V4L2_STD_MN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) areg_05 |= 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } else switch (tm6010_a_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if ((dev->norm & V4L2_STD_SECAM) == V4L2_STD_SECAM_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) areg_05 |= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else /* Other PAL/SECAM standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) areg_05 |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (dev->norm & V4L2_STD_DK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) areg_05 = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) areg_05 = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* NICAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (dev->norm & V4L2_STD_DK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) areg_05 = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } else if (dev->norm & V4L2_STD_PAL_I) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) areg_05 = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } else if (dev->norm & V4L2_STD_SECAM_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) areg_05 = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) areg_02 = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) areg_05 = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* other */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (dev->norm & V4L2_STD_DK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) areg_05 = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) areg_05 = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, areg_02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, areg_05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, areg_06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0x91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tm6000_set_reg(dev, TM6010_REQ08_R0B_A_ASD_THRES1, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) tm6000_set_reg(dev, TM6010_REQ08_R0E_A_MONO_THRES1, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) tm6000_set_reg(dev, TM6010_REQ08_R0F_A_MONO_THRES2, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tm6000_set_reg(dev, TM6010_REQ08_R10_A_MUTE_THRES1, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) tm6000_set_reg(dev, TM6010_REQ08_R11_A_MUTE_THRES2, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) tm6000_set_reg(dev, TM6010_REQ08_R12_A_AGC_U, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) tm6000_set_reg(dev, TM6010_REQ08_R13_A_AGC_ERR_T, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tm6000_set_reg(dev, TM6010_REQ08_R14_A_AGC_GAIN_INIT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) tm6000_set_reg(dev, TM6010_REQ08_R15_A_AGC_STEP_THR, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tm6000_set_reg(dev, TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tm6000_set_reg(dev, TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tm6000_set_reg(dev, TM6010_REQ08_R18_A_TR_CTRL, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tm6000_set_reg(dev, TM6010_REQ08_R19_A_FH_2FH_GAIN, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tm6000_set_reg(dev, TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tm6000_set_reg(dev, TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1d, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void tm6000_get_std_res(struct tm6000_core *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Currently, those are the only supported resoltions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (dev->norm & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev->height = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev->height = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev->width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int tm6000_load_std(struct tm6000_core *dev, struct tm6000_reg_settings *set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Load board's initialization table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for (i = 0; set[i].req; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) rc = tm6000_set_reg(dev, set[i].req, set[i].reg, set[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) printk(KERN_ERR "Error %i while setting req %d, reg %d to value %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) rc, set[i].req, set[i].reg, set[i].value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int tm6000_set_standard(struct tm6000_core *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct tm6000_input *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int i, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u8 reg_07_fe = 0x8a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 reg_08_f1 = 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 reg_08_e2 = 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u8 reg_08_e6 = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) tm6000_get_std_res(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!dev->radio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) input = &dev->vinput[dev->input];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) input = &dev->rinput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (dev->dev_type == TM6010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch (input->vmux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case TM6000_VMUX_VIDEO_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) reg_07_fe |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case TM6000_VMUX_VIDEO_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) reg_07_fe |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case TM6000_VMUX_VIDEO_AB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reg_08_e6 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) switch (input->amux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case TM6000_AMUX_ADC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 0x00, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Mux overflow workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0x10, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case TM6000_AMUX_ADC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0x08, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Mux overflow workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0x10, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case TM6000_AMUX_SIF1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) reg_08_e2 |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reg_08_e6 = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) reg_07_fe |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) reg_08_f1 |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x02, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Mux overflow workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0x30, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case TM6000_AMUX_SIF2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) reg_08_e2 |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) reg_08_e6 = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) reg_07_fe |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) reg_08_f1 |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x02, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Mux overflow workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) tm6000_set_reg_mask(dev, TM6010_REQ07_R07_OUTPUT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x30, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, reg_08_e2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, reg_08_e6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, reg_08_f1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, reg_07_fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) switch (input->vmux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case TM6000_VMUX_VIDEO_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) tm6000_set_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) REQ_03_SET_GET_MCU_PIN, input->v_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case TM6000_VMUX_VIDEO_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tm6000_set_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) REQ_03_SET_GET_MCU_PIN, input->v_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case TM6000_VMUX_VIDEO_AB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tm6000_set_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) REQ_03_SET_GET_MCU_PIN, input->v_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) switch (input->amux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case TM6000_AMUX_ADC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tm6000_set_reg_mask(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) TM6000_REQ07_REB_VADC_AADC_MODE, 0x00, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case TM6000_AMUX_ADC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) tm6000_set_reg_mask(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) TM6000_REQ07_REB_VADC_AADC_MODE, 0x04, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (input->type == TM6000_INPUT_SVIDEO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) for (i = 0; i < ARRAY_SIZE(svideo_stds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (dev->norm & svideo_stds[i].id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) rc = tm6000_load_std(dev, svideo_stds[i].common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) for (i = 0; i < ARRAY_SIZE(composite_stds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (dev->norm & composite_stds[i].id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) rc = tm6000_load_std(dev, composite_stds[i].common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) goto ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if ((dev->dev_type == TM6010) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ((input->amux == TM6000_AMUX_SIF1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) (input->amux == TM6000_AMUX_SIF2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tm6000_set_audio_std(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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