^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * STK1160 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Ezequiel Garcia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * <elezegarcia--a.t--gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on Easycap driver by R.M. Thomas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2010 R.M. Thomas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * <rmthomas--a.t--sciolus.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* GPIO Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STK1160_GCTRL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Remote Wakeup Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STK1160_RMCTL 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Power-on Strapping Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STK1160_POSVA 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STK1160_POSV_L 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STK1160_POSV_M 0x011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STK1160_POSV_H 0x012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STK1160_POSV_L_ACDOUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STK1160_POSV_L_ACSYNC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Decoder Control Register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This byte controls capture start/stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * with bit #7 (0x?? OR 0x80 to activate).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STK1160_DCTRL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Decimation Control Register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Byte 104: Horizontal Decimation Line Unit Count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Byte 105: Vertical Decimation Line Unit Count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Byte 106: Decimation Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Bit 0 - Horizontal Decimation Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 0 Horizontal decimation is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 1 Horizontal decimation is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Bit 1 - Decimates Half or More Column
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 0 Decimates less than half from original column,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * send count unit (0x105) before each unit skipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 1 Decimates half or more from original column,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * skip count unit (0x105) before each unit sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Bit 2 - Vertical Decimation Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 0 Vertical decimation is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 1 Vertical decimation is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Bit 3 - Vertical Greater or Equal to Half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 0 Decimates less than half from original row,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * send count unit (0x105) before each unit skipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 1 Decimates half or more from original row,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * skip count unit (0x105) before each unit sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Bit 4 - Decimation Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 0 Decimation will work with 2 rows or columns per unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 1 Decimation will work with 4 rows or columns per unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STK1160_DMCTRL_H_UNITS 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STK1160_DMCTRL_V_UNITS 0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STK1160_DMCTRL 0x106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STK1160_H_DEC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STK1160_H_DEC_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STK1160_V_DEC_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STK1160_V_DEC_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STK1160_DEC_UNIT_SIZE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Capture Frame Start Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STK116_CFSPO 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STK116_CFSPO_STX_L 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STK116_CFSPO_STX_H 0x111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STK116_CFSPO_STY_L 0x112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STK116_CFSPO_STY_H 0x113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Capture Frame End Position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STK116_CFEPO 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STK116_CFEPO_ENX_L 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STK116_CFEPO_ENX_H 0x115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STK116_CFEPO_ENY_L 0x116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STK116_CFEPO_ENY_H 0x117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Serial Interface Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STK1160_SICTL 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STK1160_SICTL_CD 0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STK1160_SICTL_SDA 0x203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Serial Bus Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define STK1160_SBUSW 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define STK1160_SBUSW_WA 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STK1160_SBUSW_WD 0x205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Serial Bus Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STK1160_SBUSR 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STK1160_SBUSR_RA 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STK1160_SBUSR_RD 0x209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Alternate Serial Interface Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STK1160_ASIC 0x2fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* PLL Select Options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STK1160_PLLSO 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PLL Frequency Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STK1160_PLLFD 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Timing Generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STK1160_TIGEN 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Timing Control Parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define STK1160_TICTL 0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* AC97 Audio Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define STK1160_AC97CTL_0 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define STK1160_AC97CTL_1 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STK1160_AC97CTL_0_CR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define STK1160_AC97CTL_0_CW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Use [0:6] bits of register 0x504 to set codec command address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define STK1160_AC97_ADDR 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Use [16:31] bits of register 0x500 to set codec command data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define STK1160_AC97_CMD 0x502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Audio I2S Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define STK1160_I2SCTL 0x50c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* EEPROM Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define STK1160_EEPROM_SZ 0x5f0
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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