^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Linux driver for Philips webcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) USB and Video4Linux interface part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) (C) 1999-2004 Nemosoft Unv.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) (C) 2004-2006 Luc Saillard (luc@saillard.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) (C) 2011 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) NOTE: this version of pwc is an unofficial (modified) release of pwc & pcwx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) driver and thus may have bugs that are not present in the original version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Please send bug reports and support requests to <luc@saillard.org>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) The decompression routines have been implemented by reverse-engineering the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Nemosoft binary pwcx module. Caveat emptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pwc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PWC_CID_CUSTOM(ctrl) ((V4L2_CID_USER_BASE | 0xf000) + custom_ ## ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int pwc_g_volatile_ctrl(struct v4l2_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int pwc_s_ctrl(struct v4l2_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct v4l2_ctrl_ops pwc_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .g_volatile_ctrl = pwc_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .s_ctrl = pwc_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum { awb_indoor, awb_outdoor, awb_fl, awb_manual, awb_auto };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum { custom_autocontour, custom_contour, custom_noise_reduction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) custom_awb_speed, custom_awb_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) custom_save_user, custom_restore_user, custom_restore_factory };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const char * const pwc_auto_whitebal_qmenu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "Indoor (Incandescant Lighting) Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "Outdoor (Sunlight) Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "Indoor (Fluorescent Lighting) Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "Manual Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "Auto Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct v4l2_ctrl_config pwc_auto_white_balance_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .id = V4L2_CID_AUTO_WHITE_BALANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .type = V4L2_CTRL_TYPE_MENU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .max = awb_auto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .qmenu = pwc_auto_whitebal_qmenu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct v4l2_ctrl_config pwc_autocontour_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .id = PWC_CID_CUSTOM(autocontour),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .type = V4L2_CTRL_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "Auto contour",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct v4l2_ctrl_config pwc_contour_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .id = PWC_CID_CUSTOM(contour),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "Contour",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .flags = V4L2_CTRL_FLAG_SLIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .max = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct v4l2_ctrl_config pwc_backlight_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .id = V4L2_CID_BACKLIGHT_COMPENSATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .type = V4L2_CTRL_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct v4l2_ctrl_config pwc_flicker_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .id = V4L2_CID_BAND_STOP_FILTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .type = V4L2_CTRL_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct v4l2_ctrl_config pwc_noise_reduction_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .id = PWC_CID_CUSTOM(noise_reduction),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "Dynamic Noise Reduction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .max = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct v4l2_ctrl_config pwc_save_user_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .id = PWC_CID_CUSTOM(save_user),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .type = V4L2_CTRL_TYPE_BUTTON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "Save User Settings",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct v4l2_ctrl_config pwc_restore_user_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .id = PWC_CID_CUSTOM(restore_user),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .type = V4L2_CTRL_TYPE_BUTTON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "Restore User Settings",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct v4l2_ctrl_config pwc_restore_factory_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .id = PWC_CID_CUSTOM(restore_factory),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .type = V4L2_CTRL_TYPE_BUTTON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "Restore Factory Settings",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct v4l2_ctrl_config pwc_awb_speed_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .id = PWC_CID_CUSTOM(awb_speed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .name = "Auto White Balance Speed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .max = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct v4l2_ctrl_config pwc_awb_delay_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .ops = &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .id = PWC_CID_CUSTOM(awb_delay),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "Auto White Balance Delay",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .max = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int pwc_init_controls(struct pwc_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int r, def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) hdl = &pdev->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) r = v4l2_ctrl_handler_init(hdl, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Brightness, contrast, saturation, gamma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL, BRIGHTNESS_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (r || def > 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) def = 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pdev->brightness = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) V4L2_CID_BRIGHTNESS, 0, 127, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL, CONTRAST_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (r || def > 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) def = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pdev->contrast = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) V4L2_CID_CONTRAST, 0, 63, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (pdev->type >= 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (pdev->type < 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pdev->saturation_fmt = SATURATION_MODE_FORMATTER2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pdev->saturation_fmt = SATURATION_MODE_FORMATTER1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) r = pwc_get_s8_ctrl(pdev, GET_CHROM_CTL, pdev->saturation_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (r || def < -100 || def > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pdev->saturation = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) V4L2_CID_SATURATION, -100, 100, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL, GAMMA_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (r || def > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) def = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pdev->gamma = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) V4L2_CID_GAMMA, 0, 31, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* auto white balance, red gain, blue gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) r = pwc_get_u8_ctrl(pdev, GET_CHROM_CTL, WB_MODE_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (r || def > awb_auto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) def = awb_auto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cfg = pwc_auto_white_balance_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cfg.name = v4l2_ctrl_get_name(cfg.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cfg.def = def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pdev->auto_white_balance = v4l2_ctrl_new_custom(hdl, &cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* check auto controls to avoid NULL deref in v4l2_ctrl_auto_cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!pdev->auto_white_balance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) r = pwc_get_u8_ctrl(pdev, GET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PRESET_MANUAL_RED_GAIN_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) def = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pdev->red_balance = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) V4L2_CID_RED_BALANCE, 0, 255, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) r = pwc_get_u8_ctrl(pdev, GET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PRESET_MANUAL_BLUE_GAIN_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) def = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pdev->blue_balance = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) V4L2_CID_BLUE_BALANCE, 0, 255, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) v4l2_ctrl_auto_cluster(3, &pdev->auto_white_balance, awb_manual, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* autogain, gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL, AGC_MODE_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (r || (def != 0 && def != 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Note a register value if 0 means auto gain is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pdev->autogain = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) V4L2_CID_AUTOGAIN, 0, 1, 1, def == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!pdev->autogain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL, PRESET_AGC_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (r || def > 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) def = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pdev->gain = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) V4L2_CID_GAIN, 0, 63, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* auto exposure, exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (DEVICE_USE_CODEC2(pdev->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL, SHUTTER_MODE_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (r || (def != 0 && def != 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * def = 0 auto, def = ff manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * menu idx 0 = auto, idx 1 = manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pdev->exposure_auto = v4l2_ctrl_new_std_menu(hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) V4L2_CID_EXPOSURE_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 1, 0, def != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!pdev->exposure_auto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* GET_LUM_CTL, PRESET_SHUTTER_FORMATTER is unreliable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) r = pwc_get_u16_ctrl(pdev, GET_STATUS_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) READ_SHUTTER_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (r || def > 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) def = 655;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pdev->exposure = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) V4L2_CID_EXPOSURE, 0, 655, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* CODEC2: separate auto gain & auto exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) v4l2_ctrl_auto_cluster(2, &pdev->autogain, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) v4l2_ctrl_auto_cluster(2, &pdev->exposure_auto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) V4L2_EXPOSURE_MANUAL, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else if (DEVICE_USE_CODEC3(pdev->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* GET_LUM_CTL, PRESET_SHUTTER_FORMATTER is unreliable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) r = pwc_get_u16_ctrl(pdev, GET_STATUS_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) READ_SHUTTER_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (r || def > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) def = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pdev->exposure = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) V4L2_CID_EXPOSURE, 0, 255, 1, def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* CODEC3: both gain and exposure controlled by autogain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pdev->autogain_expo_cluster[0] = pdev->autogain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pdev->autogain_expo_cluster[1] = pdev->gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pdev->autogain_expo_cluster[2] = pdev->exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) v4l2_ctrl_auto_cluster(3, pdev->autogain_expo_cluster,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* color / bw setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) r = pwc_get_u8_ctrl(pdev, GET_CHROM_CTL, COLOUR_MODE_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (r || (def != 0 && def != 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) def = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* def = 0 bw, def = ff color, menu idx 0 = color, idx 1 = bw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pdev->colorfx = v4l2_ctrl_new_std_menu(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) V4L2_CID_COLORFX, 1, 0, def == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* autocontour, contour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL, AUTO_CONTOUR_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (r || (def != 0 && def != 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cfg = pwc_autocontour_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cfg.def = def == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pdev->autocontour = v4l2_ctrl_new_custom(hdl, &cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!pdev->autocontour)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL, PRESET_CONTOUR_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (r || def > 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) def = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cfg = pwc_contour_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cfg.def = def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pdev->contour = v4l2_ctrl_new_custom(hdl, &cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) v4l2_ctrl_auto_cluster(2, &pdev->autocontour, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* backlight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) BACK_LIGHT_COMPENSATION_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (r || (def != 0 && def != 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cfg = pwc_backlight_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cfg.name = v4l2_ctrl_get_name(cfg.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) cfg.def = def == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pdev->backlight = v4l2_ctrl_new_custom(hdl, &cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* flikker rediction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FLICKERLESS_MODE_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (r || (def != 0 && def != 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) cfg = pwc_flicker_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cfg.name = v4l2_ctrl_get_name(cfg.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cfg.def = def == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pdev->flicker = v4l2_ctrl_new_custom(hdl, &cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Dynamic noise reduction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) r = pwc_get_u8_ctrl(pdev, GET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DYNAMIC_NOISE_CONTROL_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (r || def > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) def = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) cfg = pwc_noise_reduction_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cfg.def = def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pdev->noise_reduction = v4l2_ctrl_new_custom(hdl, &cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Save / Restore User / Factory Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pdev->save_user = v4l2_ctrl_new_custom(hdl, &pwc_save_user_cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pdev->restore_user = v4l2_ctrl_new_custom(hdl, &pwc_restore_user_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (pdev->restore_user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pdev->restore_user->flags |= V4L2_CTRL_FLAG_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pdev->restore_factory = v4l2_ctrl_new_custom(hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) &pwc_restore_factory_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (pdev->restore_factory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pdev->restore_factory->flags |= V4L2_CTRL_FLAG_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Auto White Balance speed & delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) r = pwc_get_u8_ctrl(pdev, GET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) AWB_CONTROL_SPEED_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (r || def < 1 || def > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) def = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cfg = pwc_awb_speed_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cfg.def = def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pdev->awb_speed = v4l2_ctrl_new_custom(hdl, &cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) r = pwc_get_u8_ctrl(pdev, GET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) AWB_CONTROL_DELAY_FORMATTER, &def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (r || def > 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) cfg = pwc_awb_delay_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cfg.def = def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pdev->awb_delay = v4l2_ctrl_new_custom(hdl, &cfg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!(pdev->features & FEATURE_MOTOR_PANTILT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Motor pan / tilt / reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pdev->motor_pan = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) V4L2_CID_PAN_RELATIVE, -4480, 4480, 64, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!pdev->motor_pan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pdev->motor_tilt = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) V4L2_CID_TILT_RELATIVE, -1920, 1920, 64, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pdev->motor_pan_reset = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) V4L2_CID_PAN_RESET, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pdev->motor_tilt_reset = v4l2_ctrl_new_std(hdl, &pwc_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) V4L2_CID_TILT_RESET, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) v4l2_ctrl_cluster(4, &pdev->motor_pan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void pwc_vidioc_fill_fmt(struct v4l2_format *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int width, int height, u32 pixfmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) memset(&f->fmt.pix, 0, sizeof(struct v4l2_pix_format));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) f->fmt.pix.width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) f->fmt.pix.height = height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) f->fmt.pix.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) f->fmt.pix.pixelformat = pixfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) f->fmt.pix.bytesperline = f->fmt.pix.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.width * 3 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PWC_DEBUG_IOCTL("pwc_vidioc_fill_fmt() width=%d, height=%d, bytesperline=%d, sizeimage=%d, pixelformat=%c%c%c%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) f->fmt.pix.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) f->fmt.pix.height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) f->fmt.pix.bytesperline,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) f->fmt.pix.sizeimage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) (f->fmt.pix.pixelformat)&255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (f->fmt.pix.pixelformat>>8)&255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (f->fmt.pix.pixelformat>>16)&255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) (f->fmt.pix.pixelformat>>24)&255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* ioctl(VIDIOC_TRY_FMT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int pwc_vidioc_try_fmt(struct pwc_device *pdev, struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PWC_DEBUG_IOCTL("Bad video type must be V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) switch (f->fmt.pix.pixelformat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case V4L2_PIX_FMT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case V4L2_PIX_FMT_PWC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (DEVICE_USE_CODEC23(pdev->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PWC_DEBUG_IOCTL("codec1 is only supported for old pwc webcam\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case V4L2_PIX_FMT_PWC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (DEVICE_USE_CODEC1(pdev->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PWC_DEBUG_IOCTL("codec23 is only supported for new pwc webcam\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PWC_DEBUG_IOCTL("Unsupported pixel format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) size = pwc_get_size(pdev, f->fmt.pix.width, f->fmt.pix.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pwc_vidioc_fill_fmt(f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pwc_image_sizes[size][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pwc_image_sizes[size][1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) f->fmt.pix.pixelformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* ioctl(VIDIOC_SET_FMT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int pwc_s_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ret, pixelformat, compression = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = pwc_vidioc_try_fmt(pdev, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (vb2_is_busy(&pdev->vb_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pixelformat = f->fmt.pix.pixelformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PWC_DEBUG_IOCTL("Trying to set format to: width=%d height=%d fps=%d format=%c%c%c%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) f->fmt.pix.width, f->fmt.pix.height, pdev->vframes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) (pixelformat)&255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (pixelformat>>8)&255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) (pixelformat>>16)&255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) (pixelformat>>24)&255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = pwc_set_video_mode(pdev, f->fmt.pix.width, f->fmt.pix.height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pixelformat, 30, &compression, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PWC_DEBUG_IOCTL("pwc_set_video_mode(), return=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pwc_vidioc_fill_fmt(f, pdev->width, pdev->height, pdev->pixfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int pwc_querycap(struct file *file, void *fh, struct v4l2_capability *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) strscpy(cap->driver, PWC_NAME, sizeof(cap->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) strscpy(cap->card, pdev->vdev.name, sizeof(cap->card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) usb_make_path(pdev->udev, cap->bus_info, sizeof(cap->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int pwc_enum_input(struct file *file, void *fh, struct v4l2_input *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (i->index) /* Only one INPUT is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) strscpy(i->name, "Camera", sizeof(i->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) i->type = V4L2_INPUT_TYPE_CAMERA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int pwc_g_input(struct file *file, void *fh, unsigned int *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) *i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int pwc_s_input(struct file *file, void *fh, unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return i ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int pwc_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct pwc_device *pdev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) container_of(ctrl->handler, struct pwc_device, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (pdev->color_bal_valid &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) (pdev->auto_white_balance->val != awb_auto ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) time_before(jiffies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pdev->last_color_bal_update + HZ / 4))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pdev->red_balance->val = pdev->last_red_balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pdev->blue_balance->val = pdev->last_blue_balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = pwc_get_u8_ctrl(pdev, GET_STATUS_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) READ_RED_GAIN_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &pdev->red_balance->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = pwc_get_u8_ctrl(pdev, GET_STATUS_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) READ_BLUE_GAIN_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &pdev->blue_balance->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pdev->last_red_balance = pdev->red_balance->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pdev->last_blue_balance = pdev->blue_balance->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pdev->last_color_bal_update = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pdev->color_bal_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (pdev->gain_valid && time_before(jiffies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pdev->last_gain_update + HZ / 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pdev->gain->val = pdev->last_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = pwc_get_u8_ctrl(pdev, GET_STATUS_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) READ_AGC_FORMATTER, &pdev->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pdev->last_gain = pdev->gain->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pdev->last_gain_update = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) pdev->gain_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!DEVICE_USE_CODEC3(pdev->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* For CODEC3 where autogain also controls expo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (pdev->exposure_valid && time_before(jiffies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pdev->last_exposure_update + HZ / 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pdev->exposure->val = pdev->last_exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = pwc_get_u16_ctrl(pdev, GET_STATUS_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) READ_SHUTTER_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) &pdev->exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pdev->last_exposure = pdev->exposure->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pdev->last_exposure_update = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pdev->exposure_valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PWC_ERROR("g_ctrl %s error %d\n", ctrl->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int pwc_set_awb(struct pwc_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (pdev->auto_white_balance->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = pwc_set_u8_ctrl(pdev, SET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) WB_MODE_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pdev->auto_white_balance->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (pdev->auto_white_balance->val != awb_manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pdev->color_bal_valid = false; /* Force cache update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * If this is a preset, update our red / blue balance values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * so that events get generated for the new preset values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (pdev->auto_white_balance->val == awb_indoor ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pdev->auto_white_balance->val == awb_outdoor ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pdev->auto_white_balance->val == awb_fl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pwc_g_volatile_ctrl(pdev->auto_white_balance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (pdev->auto_white_balance->val != awb_manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (pdev->red_balance->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret = pwc_set_u8_ctrl(pdev, SET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PRESET_MANUAL_RED_GAIN_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) pdev->red_balance->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (pdev->blue_balance->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = pwc_set_u8_ctrl(pdev, SET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PRESET_MANUAL_BLUE_GAIN_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pdev->blue_balance->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* For CODEC2 models which have separate autogain and auto exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int pwc_set_autogain(struct pwc_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (pdev->autogain->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) AGC_MODE_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) pdev->autogain->val ? 0 : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (pdev->autogain->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pdev->gain_valid = false; /* Force cache update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (pdev->autogain->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (pdev->gain->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PRESET_AGC_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pdev->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* For CODEC2 models which have separate autogain and auto exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int pwc_set_exposure_auto(struct pwc_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int is_auto = pdev->exposure_auto->val == V4L2_EXPOSURE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (pdev->exposure_auto->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SHUTTER_MODE_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) is_auto ? 0 : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (is_auto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pdev->exposure_valid = false; /* Force cache update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (is_auto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (pdev->exposure->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = pwc_set_u16_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PRESET_SHUTTER_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pdev->exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* For CODEC3 models which have autogain controlling both gain and exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int pwc_set_autogain_expo(struct pwc_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (pdev->autogain->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) AGC_MODE_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) pdev->autogain->val ? 0 : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (pdev->autogain->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pdev->gain_valid = false; /* Force cache update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pdev->exposure_valid = false; /* Force cache update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (pdev->autogain->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (pdev->gain->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PRESET_AGC_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pdev->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (pdev->exposure->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = pwc_set_u16_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PRESET_SHUTTER_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pdev->exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int pwc_set_motor(struct pwc_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pdev->ctrl_buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (pdev->motor_pan_reset->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pdev->ctrl_buf[0] |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (pdev->motor_tilt_reset->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pdev->ctrl_buf[0] |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (pdev->motor_pan_reset->is_new || pdev->motor_tilt_reset->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = send_control_msg(pdev, SET_MPT_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PT_RESET_CONTROL_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pdev->ctrl_buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) memset(pdev->ctrl_buf, 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (pdev->motor_pan->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pdev->ctrl_buf[0] = pdev->motor_pan->val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pdev->ctrl_buf[1] = (pdev->motor_pan->val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (pdev->motor_tilt->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pdev->ctrl_buf[2] = pdev->motor_tilt->val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pdev->ctrl_buf[3] = (pdev->motor_tilt->val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (pdev->motor_pan->is_new || pdev->motor_tilt->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = send_control_msg(pdev, SET_MPT_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PT_RELATIVE_CONTROL_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) pdev->ctrl_buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int pwc_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct pwc_device *pdev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) container_of(ctrl->handler, struct pwc_device, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) BRIGHTNESS_FORMATTER, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) CONTRAST_FORMATTER, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = pwc_set_s8_ctrl(pdev, SET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pdev->saturation_fmt, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case V4L2_CID_GAMMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) GAMMA_FORMATTER, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = pwc_set_awb(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (DEVICE_USE_CODEC2(pdev->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = pwc_set_autogain(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) else if (DEVICE_USE_CODEC3(pdev->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = pwc_set_autogain_expo(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (DEVICE_USE_CODEC2(pdev->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = pwc_set_exposure_auto(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) case V4L2_CID_COLORFX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = pwc_set_u8_ctrl(pdev, SET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) COLOUR_MODE_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ctrl->val ? 0 : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case PWC_CID_CUSTOM(autocontour):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (pdev->autocontour->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) AUTO_CONTOUR_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) pdev->autocontour->val ? 0 : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ret == 0 && pdev->contour->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PRESET_CONTOUR_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pdev->contour->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case V4L2_CID_BACKLIGHT_COMPENSATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) BACK_LIGHT_COMPENSATION_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ctrl->val ? 0 : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case V4L2_CID_BAND_STOP_FILTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) FLICKERLESS_MODE_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ctrl->val ? 0 : 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case PWC_CID_CUSTOM(noise_reduction):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = pwc_set_u8_ctrl(pdev, SET_LUM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) DYNAMIC_NOISE_CONTROL_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case PWC_CID_CUSTOM(save_user):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = pwc_button_ctrl(pdev, SAVE_USER_DEFAULTS_FORMATTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case PWC_CID_CUSTOM(restore_user):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = pwc_button_ctrl(pdev, RESTORE_USER_DEFAULTS_FORMATTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case PWC_CID_CUSTOM(restore_factory):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = pwc_button_ctrl(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) RESTORE_FACTORY_DEFAULTS_FORMATTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case PWC_CID_CUSTOM(awb_speed):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = pwc_set_u8_ctrl(pdev, SET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) AWB_CONTROL_SPEED_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case PWC_CID_CUSTOM(awb_delay):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = pwc_set_u8_ctrl(pdev, SET_CHROM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) AWB_CONTROL_DELAY_FORMATTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case V4L2_CID_PAN_RELATIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = pwc_set_motor(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PWC_ERROR("s_ctrl %s error %d\n", ctrl->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int pwc_enum_fmt_vid_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* We only support two format: the raw format, and YUV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) switch (f->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* RAW format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) f->pixelformat = pdev->type <= 646 ? V4L2_PIX_FMT_PWC1 : V4L2_PIX_FMT_PWC2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) f->pixelformat = V4L2_PIX_FMT_YUV420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static int pwc_g_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PWC_DEBUG_IOCTL("ioctl(VIDIOC_G_FMT) return size %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pdev->width, pdev->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) pwc_vidioc_fill_fmt(f, pdev->width, pdev->height, pdev->pixfmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int pwc_try_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return pwc_vidioc_try_fmt(pdev, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int pwc_enum_framesizes(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct v4l2_frmsizeenum *fsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) unsigned int i = 0, index = fsize->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (fsize->pixel_format == V4L2_PIX_FMT_YUV420 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) (fsize->pixel_format == V4L2_PIX_FMT_PWC1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) DEVICE_USE_CODEC1(pdev->type)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) (fsize->pixel_format == V4L2_PIX_FMT_PWC2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) DEVICE_USE_CODEC23(pdev->type))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) for (i = 0; i < PSZ_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!(pdev->image_mask & (1UL << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!index--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) fsize->discrete.width = pwc_image_sizes[i][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) fsize->discrete.height = pwc_image_sizes[i][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int pwc_enum_frameintervals(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct v4l2_frmivalenum *fival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) int size = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) for (i = 0; i < PSZ_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (pwc_image_sizes[i][0] == fival->width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) pwc_image_sizes[i][1] == fival->height) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) size = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* TODO: Support raw format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (size < 0 || fival->pixel_format != V4L2_PIX_FMT_YUV420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) i = pwc_get_fps(pdev, fival->index, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) fival->discrete.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) fival->discrete.denominator = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int pwc_g_parm(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct v4l2_streamparm *parm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) memset(parm, 0, sizeof(*parm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) parm->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) parm->parm.capture.readbuffers = MIN_FRAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) parm->parm.capture.capability |= V4L2_CAP_TIMEPERFRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) parm->parm.capture.timeperframe.denominator = pdev->vframes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) parm->parm.capture.timeperframe.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int pwc_s_parm(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct v4l2_streamparm *parm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct pwc_device *pdev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int compression = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int ret, fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* If timeperframe == 0, then reset the framerate to the nominal value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) We pick a high framerate here, and let pwc_set_video_mode() figure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) out the best match. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (parm->parm.capture.timeperframe.numerator == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) parm->parm.capture.timeperframe.denominator == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) fps = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) fps = parm->parm.capture.timeperframe.denominator /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) parm->parm.capture.timeperframe.numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (vb2_is_busy(&pdev->vb_queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = pwc_set_video_mode(pdev, pdev->width, pdev->height, pdev->pixfmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) fps, &compression, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) pwc_g_parm(file, fh, parm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) const struct v4l2_ioctl_ops pwc_ioctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .vidioc_querycap = pwc_querycap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .vidioc_enum_input = pwc_enum_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .vidioc_g_input = pwc_g_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .vidioc_s_input = pwc_s_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .vidioc_enum_fmt_vid_cap = pwc_enum_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .vidioc_g_fmt_vid_cap = pwc_g_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .vidioc_s_fmt_vid_cap = pwc_s_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .vidioc_try_fmt_vid_cap = pwc_try_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .vidioc_reqbufs = vb2_ioctl_reqbufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .vidioc_querybuf = vb2_ioctl_querybuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .vidioc_qbuf = vb2_ioctl_qbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .vidioc_dqbuf = vb2_ioctl_dqbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .vidioc_streamon = vb2_ioctl_streamon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .vidioc_streamoff = vb2_ioctl_streamoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .vidioc_log_status = v4l2_ctrl_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .vidioc_enum_framesizes = pwc_enum_framesizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .vidioc_enum_frameintervals = pwc_enum_frameintervals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .vidioc_g_parm = pwc_g_parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .vidioc_s_parm = pwc_s_parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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