^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005 Mike Isely <isely@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __PVRUSB2_HDW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __PVRUSB2_HDW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <media/v4l2-dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pvrusb2-io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pvrusb2-ctrl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Private internal control ids, look these up with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) pvr2_hdw_get_ctrl_by_id() - these are NOT visible in V4L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PVR2_CID_STDCUR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PVR2_CID_STDAVAIL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PVR2_CID_INPUT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PVR2_CID_AUDIOMODE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PVR2_CID_FREQUENCY 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PVR2_CID_HRES 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PVR2_CID_VRES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PVR2_CID_CROPL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PVR2_CID_CROPT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PVR2_CID_CROPW 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PVR2_CID_CROPH 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PVR2_CID_CROPCAPPAN 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PVR2_CID_CROPCAPPAD 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PVR2_CID_CROPCAPBL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PVR2_CID_CROPCAPBT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PVR2_CID_CROPCAPBW 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PVR2_CID_CROPCAPBH 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PVR2_CID_STDDETECT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Legal values for the INPUT state variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PVR2_CVAL_INPUT_TV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PVR2_CVAL_INPUT_DTV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PVR2_CVAL_INPUT_COMPOSITE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PVR2_CVAL_INPUT_SVIDEO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PVR2_CVAL_INPUT_RADIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PVR2_CVAL_INPUT_MAX PVR2_CVAL_INPUT_RADIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum pvr2_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pvr2_config_empty, /* No configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pvr2_config_mpeg, /* Encoded / compressed video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pvr2_config_vbi, /* Standard vbi info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pvr2_config_pcm, /* Audio raw pcm stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pvr2_config_rawvideo, /* Video raw frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum pvr2_v4l_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pvr2_v4l_type_video,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pvr2_v4l_type_vbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pvr2_v4l_type_radio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Major states that we can be in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * DEAD - Device is in an unusable state and cannot be recovered. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * can happen if we completely lose the ability to communicate with it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * (but it might still on the bus). In this state there's nothing we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * do; it must be replugged in order to recover.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * COLD - Device is in an unusable state, needs microcontroller firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * WARM - We can communicate with the device and the proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * microcontroller firmware is running, but other device initialization is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * still needed (e.g. encoder firmware).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ERROR - A problem prevents capture operation (e.g. encoder firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * missing).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * READY - Device is operational, but not streaming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * RUN - Device is streaming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PVR2_STATE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PVR2_STATE_DEAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PVR2_STATE_COLD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PVR2_STATE_WARM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PVR2_STATE_ERROR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PVR2_STATE_READY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PVR2_STATE_RUN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Translate configuration enum to a string label */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char *pvr2_config_get_name(enum pvr2_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pvr2_hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Create and return a structure for interacting with the underlying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct usb_device_id *devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Perform second stage initialization, passing in a notification callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for when the master state changes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int pvr2_hdw_initialize(struct pvr2_hdw *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void (*callback_func)(void *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void *callback_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Destroy hardware interaction structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void pvr2_hdw_destroy(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Return true if in the ready (normal) state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int pvr2_hdw_dev_ok(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Return small integer number [1..N] for logical instance number of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) device. This is useful for indexing array-valued module parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int pvr2_hdw_get_unit_number(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Get pointer to underlying USB device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Retrieve serial number of device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Retrieve bus location info of device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Retrieve per-instance string identifier for this specific device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Called when hardware has been unplugged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void pvr2_hdw_disconnect(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Sets v4l2_dev of a video_device struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *, struct video_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Get the number of defined controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Retrieve a control handle given its index (0..count-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *,unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Retrieve a control handle given its internal ID (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *,unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Retrieve a control handle given its V4L ID (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *,unsigned int ctl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Retrieve a control handle given its immediate predecessor V4L ID (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int ctl_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Commit all control changes made up to this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int pvr2_hdw_commit_ctl(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Return a bit mask of valid input selections for this device. Mask bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * will be according to PVR_CVAL_INPUT_xxxx definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Return a bit mask of allowed input selections for this device. Mask bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * will be according to PVR_CVAL_INPUT_xxxx definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Change the set of allowed input selections for this device. Both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) change_mask and change_valu are mask bits according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PVR_CVAL_INPUT_xxxx definitions. The change_mask parameter indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) which settings are being changed and the change_val parameter indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) whether corresponding settings are being set or cleared. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int pvr2_hdw_set_input_allowed(struct pvr2_hdw *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int change_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int change_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Return name for this driver instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Mark tuner status stale so that it will be re-fetched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Return information about the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int pvr2_hdw_get_tuner_status(struct pvr2_hdw *,struct v4l2_tuner *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Return information about cropping capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int pvr2_hdw_get_cropcap(struct pvr2_hdw *, struct v4l2_cropcap *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Query device and see if it thinks it is on a high-speed USB link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int pvr2_hdw_is_hsm(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Return a string token representative of the hardware type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const char *pvr2_hdw_get_type(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Return a single line description of the hardware type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const char *pvr2_hdw_get_desc(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Turn streaming on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int pvr2_hdw_set_streaming(struct pvr2_hdw *,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Find out if streaming is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int pvr2_hdw_get_streaming(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Retrieve driver overall state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int pvr2_hdw_get_state(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Configure the type of stream to generate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int pvr2_hdw_set_stream_type(struct pvr2_hdw *, enum pvr2_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Get handle to video output stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Enable / disable retrieval of CPU firmware or prom contents. This must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) be enabled before pvr2_hdw_cpufw_get() will function. Note that doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) this may prevent the device from running (and leaving this mode may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) imply a device reset). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int mode, /* 0=8KB FX2, 1=16KB FX2, 2=PROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int enable_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Return true if we're in a mode for retrieval CPU firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Retrieve a piece of the CPU's firmware at the given offset. Return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) value is the number of bytes retrieved or zero if we're past the end or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) an error otherwise (e.g. if firmware retrieval is not enabled). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int pvr2_hdw_cpufw_get(struct pvr2_hdw *,unsigned int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) char *buf,unsigned int cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Retrieve a previously stored v4l minor device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *,enum pvr2_v4l_type index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Store a v4l minor device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) enum pvr2_v4l_type index,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* The following entry points are all lower level things you normally don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) want to worry about. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Issue a command and get a response from the device. LOTS of higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) level stuff is built on this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int pvr2_send_request(struct pvr2_hdw *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void *write_ptr,unsigned int write_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void *read_ptr,unsigned int read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Slightly higher level device communication functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int pvr2_write_register(struct pvr2_hdw *, u16, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Call if for any reason we can't talk to the hardware anymore - this will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cause the driver to stop flailing on the device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void pvr2_hdw_render_useless(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Set / clear 8051's reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void pvr2_hdw_cpureset_assert(struct pvr2_hdw *,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Execute a USB-commanded device reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void pvr2_hdw_device_reset(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Reset worker's error trapping circuit breaker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int pvr2_hdw_untrip(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Execute hard reset command (after this point it's likely that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) encoder will have to be reconfigured). This also clears the "useless"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Execute simple reset command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int pvr2_hdw_cmd_powerup(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Order decoder to reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Direct manipulation of GPIO bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* This data structure is specifically for the next function... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct pvr2_hdw_debug_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int big_lock_held;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ctl_lock_held;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int flag_disconnected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int flag_init_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int flag_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int fw1_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int flag_decoder_missed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int flag_tripped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int state_encoder_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int state_encoder_run;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int state_decoder_run;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int state_decoder_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int state_usbstream_run;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int state_decoder_quiescent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int state_pipeline_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int state_pipeline_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int state_pipeline_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int state_pipeline_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int cmd_debug_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int cmd_debug_write_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int cmd_debug_read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int cmd_debug_write_pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int cmd_debug_read_pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int cmd_debug_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int cmd_debug_rstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int cmd_debug_wstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned char cmd_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Non-intrusively retrieve internal state info - this is useful for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) diagnosing lockups. Note that this operation is completed without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) kind of locking and so it is not atomic and may yield inconsistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) results. This is *purely* a debugging aid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct pvr2_hdw_debug_info *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Intrusively retrieve internal state info - this is useful for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) diagnosing overall driver state. This operation synchronizes against
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) the overall driver mutex - so if there are locking problems this will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) likely hang! This is *purely* a debugging aid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct pvr2_hdw_debug_info *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Report out several lines of text that describes driver internal state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) Results are written into the passed-in buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) char *buf_ptr,unsigned int buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Cause modules to log their state once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Cause encoder firmware to be uploaded into the device. This is normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) done autonomously, but the interface is exported here because it is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) a debugging aid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int pvr2_upload_firmware2(struct pvr2_hdw *hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif /* __PVRUSB2_HDW_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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