^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005 Mike Isely <isely@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <media/tuner.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pvrusb2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pvrusb2-std.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pvrusb2-util.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pvrusb2-hdw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "pvrusb2-i2c-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pvrusb2-eeprom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pvrusb2-hdw-internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pvrusb2-encoder.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pvrusb2-debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pvrusb2-fx2-cmd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "pvrusb2-wm8775.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pvrusb2-video-v4l.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "pvrusb2-cx2584x-v4l.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "pvrusb2-cs53l32a.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "pvrusb2-audio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TV_MIN_FREQ 55250000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TV_MAX_FREQ 850000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* This defines a minimum interval that the decoder must remain quiet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) before we are allowed to start it running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TIME_MSEC_DECODER_WAIT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* This defines a minimum interval that the decoder must be allowed to run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) before we can safely begin using its streaming output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* This defines a minimum interval that the encoder must remain quiet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) before we are allowed to configure it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TIME_MSEC_ENCODER_WAIT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* This defines the minimum interval that the encoder must successfully run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) before we consider that the encoder has run at least once since its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) firmware has been loaded. This measurement is in important for cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) where we can't do something until we know that the encoder has been run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) at least once. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TIME_MSEC_ENCODER_OK 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static DEFINE_MUTEX(pvr2_unit_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int ctlchg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int procreload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int init_pause_msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) module_param(ctlchg, int, S_IRUGO|S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) module_param(procreload, int, S_IRUGO|S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MODULE_PARM_DESC(procreload,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "Attempt init failure recovery with firmware reload");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) module_param_array(tuner, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_PARM_DESC(tuner,"specify installed tuner type");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) module_param_array(video_std, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_PARM_DESC(video_std,"specify initial video standard");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) module_param_array(tolerance, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* US Broadcast channel 3 (61.25 MHz), to help with testing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int default_tv_freq = 61250000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* 104.3 MHz, a usable FM station for my area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int default_radio_freq = 104300000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) module_param_named(tv_freq, default_tv_freq, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) module_param_named(radio_freq, default_radio_freq, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PVR2_CTL_WRITE_ENDPOINT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PVR2_CTL_READ_ENDPOINT 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PVR2_GPIO_IN 0x9008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PVR2_GPIO_OUT 0x900c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PVR2_GPIO_DIR 0x9020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PVR2_FIRMWARE_ENDPOINT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* size of a firmware chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FIRMWARE_CHUNK_SIZE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct v4l2_subdev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const char *module_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [PVR2_CLIENT_ID_MSP3400] = "msp3400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [PVR2_CLIENT_ID_CX25840] = "cx25840",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [PVR2_CLIENT_ID_SAA7115] = "saa7115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [PVR2_CLIENT_ID_TUNER] = "tuner",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [PVR2_CLIENT_ID_DEMOD] = "tuner",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [PVR2_CLIENT_ID_WM8775] = "wm8775",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const unsigned char *module_i2c_addresses[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [PVR2_CLIENT_ID_DEMOD] = "\x43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [PVR2_CLIENT_ID_MSP3400] = "\x40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [PVR2_CLIENT_ID_SAA7115] = "\x21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [PVR2_CLIENT_ID_WM8775] = "\x1b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [PVR2_CLIENT_ID_CX25840] = "\x44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [PVR2_CLIENT_ID_CS53L32A] = "\x11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char *ir_scheme_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [PVR2_IR_SCHEME_NONE] = "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [PVR2_IR_SCHEME_29XXX] = "29xxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [PVR2_IR_SCHEME_ZILOG] = "Zilog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Define the list of additional controls we'll dynamically construct based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) on query of the cx2341x module. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pvr2_mpeg_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *strid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct pvr2_mpeg_ids mpeg_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .strid = "audio_layer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .id = V4L2_CID_MPEG_AUDIO_ENCODING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .strid = "audio_bitrate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Already using audio_mode elsewhere :-( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .strid = "mpeg_audio_mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .id = V4L2_CID_MPEG_AUDIO_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .strid = "mpeg_audio_mode_extension",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .strid = "audio_emphasis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .strid = "audio_crc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .id = V4L2_CID_MPEG_AUDIO_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .strid = "video_aspect",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .id = V4L2_CID_MPEG_VIDEO_ASPECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .strid = "video_b_frames",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .strid = "video_gop_size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .strid = "video_gop_closure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .strid = "video_bitrate_mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .strid = "video_bitrate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .id = V4L2_CID_MPEG_VIDEO_BITRATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .strid = "video_bitrate_peak",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .strid = "video_temporal_decimation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .strid = "stream_type",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .id = V4L2_CID_MPEG_STREAM_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .strid = "video_spatial_filter_mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .strid = "video_spatial_filter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .strid = "video_luma_spatial_filter_type",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .strid = "video_chroma_spatial_filter_type",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .strid = "video_temporal_filter_mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .strid = "video_temporal_filter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .strid = "video_median_filter_type",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .strid = "video_luma_median_filter_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .strid = "video_luma_median_filter_bottom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .strid = "video_chroma_median_filter_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .strid = "video_chroma_median_filter_bottom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const char *control_values_srate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char *control_values_input[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [PVR2_CVAL_INPUT_DTV] = "dtv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [PVR2_CVAL_INPUT_RADIO] = "radio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const char *control_values_audiomode[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [V4L2_TUNER_MODE_MONO] = "Mono",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [V4L2_TUNER_MODE_STEREO] = "Stereo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [V4L2_TUNER_MODE_LANG1] = "Lang1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [V4L2_TUNER_MODE_LANG2] = "Lang2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char *control_values_hsm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [PVR2_CVAL_HSM_FAIL] = "Fail",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [PVR2_CVAL_HSM_HIGH] = "High",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [PVR2_CVAL_HSM_FULL] = "Full",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char *pvr2_state_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [PVR2_STATE_NONE] = "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [PVR2_STATE_DEAD] = "dead",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [PVR2_STATE_COLD] = "cold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [PVR2_STATE_WARM] = "warm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [PVR2_STATE_ERROR] = "error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [PVR2_STATE_READY] = "ready",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [PVR2_STATE_RUN] = "run",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct pvr2_fx2cmd_descdef {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned char id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {FX2CMD_REG_WRITE, "write encoder register"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {FX2CMD_REG_READ, "read encoder register"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {FX2CMD_MEMSEL, "encoder memsel"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {FX2CMD_I2C_WRITE, "i2c write"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {FX2CMD_I2C_READ, "i2c read"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {FX2CMD_GET_USB_SPEED, "get USB speed"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {FX2CMD_STREAMING_ON, "stream on"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {FX2CMD_STREAMING_OFF, "stream off"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {FX2CMD_FWPOST1, "fwpost1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {FX2CMD_POWER_OFF, "power off"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {FX2CMD_POWER_ON, "power on"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {FX2CMD_DEEP_RESET, "deep reset"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {FX2CMD_GET_IR_CODE, "get IR code"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {FX2CMD_HCW_DEMOD_RESET_PIN, "hcw demod reset pin"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {FX2CMD_HCW_MAKO_SLEEP_PIN, "hcw mako sleep pin"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void pvr2_hdw_state_sched(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int pvr2_hdw_state_eval(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void pvr2_hdw_worker_poll(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void pvr2_hdw_quiescent_timeout(struct timer_list *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void pvr2_hdw_encoder_wait_timeout(struct timer_list *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void pvr2_hdw_encoder_run_timeout(struct timer_list *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int timeout,int probe_fl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void *write_data,unsigned int write_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) void *read_data,unsigned int read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void trace_stbit(const char *name,int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pvr2_trace(PVR2_TRACE_STBITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "State bit %s <-- %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) name,(val ? "true" : "false"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *vp = hdw->freqTable[hdw->freqProgSlot-1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) *vp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int slotId = hdw->freqProgSlot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) hdw->freqTable[slotId-1] = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Handle side effects correctly - if we're tuned to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) slot, then forgot the slot id relation since the stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) frequency has been changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (hdw->freqSelector) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (hdw->freqSlotRadio == slotId) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) hdw->freqSlotRadio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (hdw->freqSlotTelevision == slotId) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hdw->freqSlotTelevision = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *vp = cptr->hdw->freqProgSlot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hdw->freqProgSlot = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (slotId > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) freq = hdw->freqTable[slotId-1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!freq) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pvr2_hdw_set_cur_freq(hdw,freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (hdw->freqSelector) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) hdw->freqSlotRadio = slotId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) hdw->freqSlotTelevision = slotId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return cptr->hdw->freqDirty != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cptr->hdw->freqDirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pvr2_hdw_set_cur_freq(cptr->hdw,v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *left = cap->bounds.left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *left = cap->bounds.left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (cap->bounds.width > cptr->hdw->cropw_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *left += cap->bounds.width - cptr->hdw->cropw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *top = cap->bounds.top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *top = cap->bounds.top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (cap->bounds.height > cptr->hdw->croph_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *top += cap->bounds.height - cptr->hdw->croph_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int stat, bleftend, cleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bleftend = cap->bounds.left+cap->bounds.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cleft = cptr->hdw->cropl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) *width = cleft < bleftend ? bleftend-cleft : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int stat, btopend, ctop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) btopend = cap->bounds.top+cap->bounds.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ctop = cptr->hdw->cropt_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *height = ctop < btopend ? btopend-ctop : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) *val = cap->bounds.left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) *val = cap->bounds.top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) *val = cap->bounds.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *val = cap->bounds.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) *val = cap->defrect.left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *val = cap->defrect.top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) *val = cap->defrect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) *val = cap->defrect.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *val = cap->pixelaspect.numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int stat = pvr2_hdw_check_cropcap(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (stat != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) *val = cap->pixelaspect.denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Actual maximum depends on the video standard in effect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *vp = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) *vp = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Actual minimum depends on device digitizer type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (cptr->hdw->hdw_desc->flag_has_cx25840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) *vp = 75;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) *vp = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *vp = cptr->hdw->input_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (v < 0 || v > PVR2_CVAL_INPUT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ((1UL << v) & cptr->hdw->input_allowed_mask) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return pvr2_hdw_set_input(cptr->hdw,v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return cptr->hdw->input_dirty != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) cptr->hdw->input_dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned long fv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (hdw->tuner_signal_stale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) fv = hdw->tuner_signal_info.rangehigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (!fv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Safety fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *vp = TV_MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) fv = (fv * 125) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) fv = fv * 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *vp = fv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned long fv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (hdw->tuner_signal_stale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) fv = hdw->tuner_signal_info.rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!fv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Safety fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *vp = TV_MIN_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) fv = (fv * 125) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) fv = fv * 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) *vp = fv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return cptr->hdw->enc_stale != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) cptr->hdw->enc_stale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) cptr->hdw->enc_unsafe_stale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct v4l2_ext_controls cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct v4l2_ext_control c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) memset(&cs,0,sizeof(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) memset(&c1,0,sizeof(c1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) cs.controls = &c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) cs.count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) c1.id = cptr->info->v4l_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) VIDIOC_G_EXT_CTRLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (ret) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) *vp = c1.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct v4l2_ext_controls cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct v4l2_ext_control c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) memset(&cs,0,sizeof(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) memset(&c1,0,sizeof(c1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) cs.controls = &c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) cs.count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) c1.id = cptr->info->v4l_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) c1.value = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) hdw->state_encoder_run, &cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) VIDIOC_S_EXT_CTRLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret == -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Oops. cx2341x is telling us it's not safe to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) this control while we're capturing. Make a note of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) fact so that the pipeline will be stopped the next time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) controls are committed. Then go on ahead and store this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) change anyway. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 0, &cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) VIDIOC_S_EXT_CTRLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!ret) hdw->enc_unsafe_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) hdw->enc_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct v4l2_queryctrl qctrl = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct pvr2_ctl_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) qctrl.id = cptr->info->v4l_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Strip out the const so we can adjust a function pointer. It's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) OK to do this here because we know this is a dynamically created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) control, so the underlying storage for the info pointer is (a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) private to us, and (b) not in read-only storage. Either we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) this or we significantly complicate the underlying control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) implementation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) info = (struct pvr2_ctl_info *)(cptr->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (info->set_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) info->set_value = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!(info->set_value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) info->set_value = ctrl_cx2341x_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return qctrl.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) *vp = cptr->hdw->state_pipeline_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) *vp = cptr->hdw->master_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int result = pvr2_hdw_is_hsm(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) *vp = PVR2_CVAL_HSM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (result) *vp = PVR2_CVAL_HSM_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) *vp = pvr2_hdw_get_detected_std(cptr->hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *vp = cptr->hdw->std_mask_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) v4l2_std_id ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ns = hdw->std_mask_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ns = (ns & ~m) | (v & m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ns == hdw->std_mask_avail) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) hdw->std_mask_avail = ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) char *bufPtr,unsigned int bufSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) unsigned int *len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) const char *bufPtr,unsigned int bufSize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int *mskp,int *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) v4l2_std_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (!pvr2_std_str_to_id(&id, bufPtr, bufSize))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (mskp) *mskp = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (valp) *valp = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) *vp = cptr->hdw->std_mask_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) v4l2_std_id ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ns = hdw->std_mask_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ns = (ns & ~m) | (v & m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (ns == hdw->std_mask_cur) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) hdw->std_mask_cur = ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) hdw->std_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return cptr->hdw->std_dirty != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) cptr->hdw->std_dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) *vp = hdw->tuner_signal_info.signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned int subchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct pvr2_hdw *hdw = cptr->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) subchan = hdw->tuner_signal_info.rxsubchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (subchan & V4L2_TUNER_SUB_MONO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) val |= (1 << V4L2_TUNER_MODE_MONO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (subchan & V4L2_TUNER_SUB_STEREO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) val |= (1 << V4L2_TUNER_MODE_STEREO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (subchan & V4L2_TUNER_SUB_LANG1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val |= (1 << V4L2_TUNER_MODE_LANG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (subchan & V4L2_TUNER_SUB_LANG2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) val |= (1 << V4L2_TUNER_MODE_LANG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) *vp = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define DEFINT(vmin,vmax) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .type = pvr2_ctl_int, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .def.type_int.min_value = vmin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .def.type_int.max_value = vmax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define DEFENUM(tab) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .type = pvr2_ctl_enum, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .def.type_enum.count = ARRAY_SIZE(tab), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .def.type_enum.value_names = tab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define DEFBOOL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .type = pvr2_ctl_bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define DEFMASK(msk,tab) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .type = pvr2_ctl_bitmask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .def.type_bitmask.valid_bits = msk, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .def.type_bitmask.bit_names = tab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define DEFREF(vname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .set_value = ctrl_set_##vname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .get_value = ctrl_get_##vname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .is_dirty = ctrl_isdirty_##vname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .clear_dirty = ctrl_cleardirty_##vname
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define VCREATE_FUNCS(vname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {*vp = cptr->hdw->vname##_val; return 0;} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {return cptr->hdw->vname##_dirty != 0;} \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {cptr->hdw->vname##_dirty = 0;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) VCREATE_FUNCS(brightness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) VCREATE_FUNCS(contrast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) VCREATE_FUNCS(saturation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) VCREATE_FUNCS(hue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) VCREATE_FUNCS(volume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) VCREATE_FUNCS(balance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) VCREATE_FUNCS(bass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) VCREATE_FUNCS(treble)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) VCREATE_FUNCS(mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) VCREATE_FUNCS(cropl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) VCREATE_FUNCS(cropt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) VCREATE_FUNCS(cropw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) VCREATE_FUNCS(croph)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) VCREATE_FUNCS(audiomode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) VCREATE_FUNCS(res_hor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) VCREATE_FUNCS(res_ver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) VCREATE_FUNCS(srate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* Table definition of all controls which can be manipulated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const struct pvr2_ctl_info control_defs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .v4l_id = V4L2_CID_BRIGHTNESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .desc = "Brightness",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .name = "brightness",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .default_value = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) DEFREF(brightness),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) DEFINT(0,255),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .v4l_id = V4L2_CID_CONTRAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .desc = "Contrast",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .name = "contrast",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .default_value = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) DEFREF(contrast),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) DEFINT(0,127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .v4l_id = V4L2_CID_SATURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .desc = "Saturation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .name = "saturation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .default_value = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) DEFREF(saturation),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) DEFINT(0,127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .v4l_id = V4L2_CID_HUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .desc = "Hue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .name = "hue",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .default_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) DEFREF(hue),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) DEFINT(-128,127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .v4l_id = V4L2_CID_AUDIO_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .desc = "Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .name = "volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .default_value = 62000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) DEFREF(volume),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) DEFINT(0,65535),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .v4l_id = V4L2_CID_AUDIO_BALANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .desc = "Balance",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .name = "balance",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .default_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) DEFREF(balance),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) DEFINT(-32768,32767),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .v4l_id = V4L2_CID_AUDIO_BASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .desc = "Bass",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .name = "bass",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .default_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) DEFREF(bass),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) DEFINT(-32768,32767),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .v4l_id = V4L2_CID_AUDIO_TREBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .desc = "Treble",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .name = "treble",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .default_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) DEFREF(treble),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) DEFINT(-32768,32767),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .v4l_id = V4L2_CID_AUDIO_MUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .desc = "Mute",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .name = "mute",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .default_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) DEFREF(mute),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) DEFBOOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .desc = "Capture crop left margin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .name = "crop_left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .internal_id = PVR2_CID_CROPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .default_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) DEFREF(cropl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) DEFINT(-129, 340),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .get_min_value = ctrl_cropl_min_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .get_max_value = ctrl_cropl_max_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .get_def_value = ctrl_get_cropcapdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .desc = "Capture crop top margin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .name = "crop_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .internal_id = PVR2_CID_CROPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .default_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) DEFREF(cropt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) DEFINT(-35, 544),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .get_min_value = ctrl_cropt_min_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .get_max_value = ctrl_cropt_max_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .get_def_value = ctrl_get_cropcapdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .desc = "Capture crop width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .name = "crop_width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .internal_id = PVR2_CID_CROPW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .default_value = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) DEFREF(cropw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) DEFINT(0, 864),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .get_max_value = ctrl_cropw_max_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .get_def_value = ctrl_get_cropcapdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .desc = "Capture crop height",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .name = "crop_height",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .internal_id = PVR2_CID_CROPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .default_value = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) DEFREF(croph),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) DEFINT(0, 576),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .get_max_value = ctrl_croph_max_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .get_def_value = ctrl_get_cropcapdh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .desc = "Capture capability pixel aspect numerator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .name = "cropcap_pixel_numerator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .internal_id = PVR2_CID_CROPCAPPAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .get_value = ctrl_get_cropcappan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .desc = "Capture capability pixel aspect denominator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .name = "cropcap_pixel_denominator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .internal_id = PVR2_CID_CROPCAPPAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .get_value = ctrl_get_cropcappad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .desc = "Capture capability bounds top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .name = "cropcap_bounds_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .internal_id = PVR2_CID_CROPCAPBT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .get_value = ctrl_get_cropcapbt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .desc = "Capture capability bounds left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .name = "cropcap_bounds_left",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .internal_id = PVR2_CID_CROPCAPBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .get_value = ctrl_get_cropcapbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .desc = "Capture capability bounds width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .name = "cropcap_bounds_width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .internal_id = PVR2_CID_CROPCAPBW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .get_value = ctrl_get_cropcapbw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .desc = "Capture capability bounds height",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .name = "cropcap_bounds_height",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .internal_id = PVR2_CID_CROPCAPBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .get_value = ctrl_get_cropcapbh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .desc = "Video Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .name = "input",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .internal_id = PVR2_CID_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .default_value = PVR2_CVAL_INPUT_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .check_value = ctrl_check_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) DEFREF(input),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) DEFENUM(control_values_input),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .desc = "Audio Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .name = "audio_mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .internal_id = PVR2_CID_AUDIOMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .default_value = V4L2_TUNER_MODE_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) DEFREF(audiomode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) DEFENUM(control_values_audiomode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .desc = "Horizontal capture resolution",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .name = "resolution_hor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .internal_id = PVR2_CID_HRES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .default_value = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) DEFREF(res_hor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) DEFINT(19,720),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .desc = "Vertical capture resolution",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .name = "resolution_ver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .internal_id = PVR2_CID_VRES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .default_value = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) DEFREF(res_ver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) DEFINT(17,576),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* Hook in check for video standard and adjust maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) depending on the standard. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .get_max_value = ctrl_vres_max_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .get_min_value = ctrl_vres_min_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .desc = "Audio Sampling Frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .name = "srate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) DEFREF(srate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) DEFENUM(control_values_srate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .desc = "Tuner Frequency (Hz)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .name = "frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .internal_id = PVR2_CID_FREQUENCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .default_value = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .set_value = ctrl_freq_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .get_value = ctrl_freq_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .is_dirty = ctrl_freq_is_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .clear_dirty = ctrl_freq_clear_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) DEFINT(0,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Hook in check for input value (tv/radio) and adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) max/min values accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .get_max_value = ctrl_freq_max_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .get_min_value = ctrl_freq_min_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .desc = "Channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .name = "channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .set_value = ctrl_channel_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .get_value = ctrl_channel_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) DEFINT(0,FREQTABLE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .desc = "Channel Program Frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .name = "freq_table_value",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .set_value = ctrl_channelfreq_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .get_value = ctrl_channelfreq_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) DEFINT(0,0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Hook in check for input value (tv/radio) and adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) max/min values accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .get_max_value = ctrl_freq_max_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .get_min_value = ctrl_freq_min_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .desc = "Channel Program ID",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .name = "freq_table_channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .set_value = ctrl_channelprog_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .get_value = ctrl_channelprog_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) DEFINT(0,FREQTABLE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .desc = "Streaming Enabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .name = "streaming_enabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .get_value = ctrl_streamingenabled_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) DEFBOOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .desc = "USB Speed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .name = "usb_speed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .get_value = ctrl_hsm_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) DEFENUM(control_values_hsm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .desc = "Master State",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .name = "master_state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .get_value = ctrl_masterstate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) DEFENUM(pvr2_state_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .desc = "Signal Present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .name = "signal_present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .get_value = ctrl_signal_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) DEFINT(0,65535),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .desc = "Audio Modes Present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .name = "audio_modes_present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .get_value = ctrl_audio_modes_present_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* For this type we "borrow" the V4L2_TUNER_MODE enum from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) v4l. Nothing outside of this module cares about this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) but I reuse it in order to also reuse the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) control_values_audiomode string table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) (1 << V4L2_TUNER_MODE_STEREO)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) (1 << V4L2_TUNER_MODE_LANG1)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) (1 << V4L2_TUNER_MODE_LANG2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) control_values_audiomode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .desc = "Video Standards Available Mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .name = "video_standard_mask_available",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .internal_id = PVR2_CID_STDAVAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .skip_init = !0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .get_value = ctrl_stdavail_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .set_value = ctrl_stdavail_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .val_to_sym = ctrl_std_val_to_sym,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .sym_to_val = ctrl_std_sym_to_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .type = pvr2_ctl_bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .desc = "Video Standards In Use Mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .name = "video_standard_mask_active",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .internal_id = PVR2_CID_STDCUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .skip_init = !0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .get_value = ctrl_stdcur_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .set_value = ctrl_stdcur_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .is_dirty = ctrl_stdcur_is_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .clear_dirty = ctrl_stdcur_clear_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .val_to_sym = ctrl_std_val_to_sym,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .sym_to_val = ctrl_std_sym_to_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .type = pvr2_ctl_bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .desc = "Video Standards Detected Mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .name = "video_standard_mask_detected",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .internal_id = PVR2_CID_STDDETECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .skip_init = !0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .get_value = ctrl_stddetect_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .val_to_sym = ctrl_std_val_to_sym,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .sym_to_val = ctrl_std_sym_to_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .type = pvr2_ctl_bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) const char *pvr2_config_get_name(enum pvr2_config cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) switch (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) case pvr2_config_empty: return "empty";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) case pvr2_config_mpeg: return "mpeg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) case pvr2_config_vbi: return "vbi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) case pvr2_config_pcm: return "pcm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) case pvr2_config_rawvideo: return "raw video";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return "<unknown>";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return hdw->usb_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return hdw->serial_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return hdw->bus_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return hdw->identifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Set the currently tuned frequency and account for all possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) driver-core side effects of this action. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (hdw->freqSelector) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Swing over to radio frequency selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) hdw->freqSelector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) hdw->freqDirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (hdw->freqValRadio != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) hdw->freqValRadio = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) hdw->freqSlotRadio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) hdw->freqDirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (!(hdw->freqSelector)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* Swing over to television frequency selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) hdw->freqSelector = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) hdw->freqDirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (hdw->freqValTelevision != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) hdw->freqValTelevision = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) hdw->freqSlotTelevision = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) hdw->freqDirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return hdw->unit_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* Attempt to locate one of the given set of files. Messages are logged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) appropriate to what has been found. The return value will be 0 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) greater on success (it will be the index of the file name found) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) fw_entry will be filled in. Otherwise a negative error is returned on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) failure. If the return value is -ENOENT then no viable firmware file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) could be located. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) const struct firmware **fw_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) const char *fwtypename,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) unsigned int fwcount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) const char *fwnames[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) for (idx = 0; idx < fwcount; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = request_firmware(fw_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) fwnames[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) &hdw->usb_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) trace_firmware("Located %s firmware: %s; uploading...",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) fwtypename,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) fwnames[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (ret == -ENOENT) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) "request_firmware fatal error with code=%d",ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) "***WARNING*** Device %s firmware seems to be missing.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) fwtypename);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) "Did you install the pvrusb2 firmware files in their proper location?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (fwcount == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) "request_firmware unable to locate %s file %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) fwtypename,fwnames[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) "request_firmware unable to locate one of the following %s files:",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) fwtypename);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) for (idx = 0; idx < fwcount; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) "request_firmware: Failed to find %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) fwnames[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * pvr2_upload_firmware1().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * Send the 8051 firmware to the device. After the upload, arrange for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * device to re-enumerate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * NOTE : the pointer to the firmware data given by request_firmware()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * is not suitable for an usb transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) const struct firmware *fw_entry = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) void *fw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) unsigned int pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) unsigned int fwsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) u16 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (!hdw->hdw_desc->fx2_firmware.cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) hdw->fw1_state = FW1_STATE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) "Connected device type defines no firmware to upload; ignoring firmware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) hdw->fw1_state = FW1_STATE_FAILED; // default result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) trace_firmware("pvr2_upload_firmware1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) hdw->hdw_desc->fx2_firmware.cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) hdw->hdw_desc->fx2_firmware.lst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) fwsize = fw_entry->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if ((fwsize != 0x2000) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (hdw->hdw_desc->flag_fx2_16kb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) "Wrong fx2 firmware size (expected 8192 or 16384, got %u)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) fwsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) "Wrong fx2 firmware size (expected 8192, got %u)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) fwsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) release_firmware(fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) fw_ptr = kmalloc(0x800, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (fw_ptr == NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) release_firmware(fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* We have to hold the CPU during firmware upload. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) pvr2_hdw_cpureset_assert(hdw,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) chunk. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) for (address = 0; address < fwsize; address += 0x800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) memcpy(fw_ptr, fw_entry->data + address, 0x800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) 0, fw_ptr, 0x800, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) trace_firmware("Upload done, releasing device's CPU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* Now release the CPU. It will disconnect and reconnect later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) pvr2_hdw_cpureset_assert(hdw,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) kfree(fw_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) release_firmware(fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) trace_firmware("Upload done (%d bytes sent)",ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* We should have written fwsize bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (ret == fwsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) hdw->fw1_state = FW1_STATE_RELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * pvr2_upload_firmware2()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * This uploads encoder firmware on endpoint 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) const struct firmware *fw_entry = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) void *fw_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) unsigned int pipe, fw_len, fw_done, bcnt, icnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) int actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) int fwidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const char *fw_files[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) CX2341X_FIRM_ENC_FILENAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) trace_firmware("pvr2_upload_firmware2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ARRAY_SIZE(fw_files), fw_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (ret < 0) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) fwidx = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* Since we're about to completely reinitialize the encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) invalidate our cached copy of its configuration state. Next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) time we configure the encoder, then we'll fully configure it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) hdw->enc_cur_valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Encoder is about to be reset so note that as far as we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) concerned now, the encoder has never been run. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) del_timer_sync(&hdw->encoder_run_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (hdw->state_encoder_runok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) hdw->state_encoder_runok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* First prepare firmware loading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ret |= pvr2_hdw_cmd_deep_reset(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) "firmware2 upload prep failed, ret=%d",ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) release_firmware(fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* Now send firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) fw_len = fw_entry->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (fw_len % sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) "size of %s firmware must be a multiple of %zu bytes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) fw_files[fwidx],sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) release_firmware(fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (fw_ptr == NULL){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) release_firmware(fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) "failed to allocate memory for firmware2 upload");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) fw_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) for (fw_done = 0; fw_done < fw_len;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) bcnt = fw_len - fw_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* Usbsnoop log shows that we must swap bytes... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* Some background info: The data being swapped here is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) firmware image destined for the mpeg encoder chip that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) lives at the other end of a USB endpoint. The encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) chip always talks in 32 bit chunks and its storage is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) organized into 32 bit words. However from the file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) system to the encoder chip everything is purely a byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) stream. The firmware file's contents are always 32 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) swapped from what the encoder expects. Thus the need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) always exists to swap the bytes regardless of the endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) type of the host processor and therefore swab32() makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) the most sense. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) for (icnt = 0; icnt < bcnt/4 ; icnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) &actual_length, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) ret |= (actual_length != bcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (ret) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) fw_done += bcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) trace_firmware("upload of %s : %i / %i ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) fw_files[fwidx],fw_done,fw_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) kfree(fw_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) release_firmware(fw_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) "firmware2 upload transfer failure");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* Finish upload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) "firmware2 upload post-proc failure");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (hdw->hdw_desc->signal_routing_scheme ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) PVR2_ROUTING_SCHEME_GOTVIEW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* Ensure that GPIO 11 is set to output for GOTVIEW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static const char *pvr2_get_state_name(unsigned int st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (st < ARRAY_SIZE(pvr2_state_names)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return pvr2_state_names[st];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return "???";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* Even though we really only care about the video decoder chip at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) this point, we'll broadcast stream on/off to all sub-devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) anyway, just in case somebody else wants to hear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) command... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) (enablefl ? "on" : "off"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (hdw->decoder_client_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* We get here if the encoder has been noticed. Otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) we'll issue a warning to the user (which should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) normally never happen). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (!hdw->flag_decoder_missed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) "***WARNING*** No decoder present");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) hdw->flag_decoder_missed = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) trace_stbit("flag_decoder_missed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) hdw->flag_decoder_missed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return hdw->master_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (!hdw->flag_tripped) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hdw->flag_tripped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) "Clearing driver error status");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) int fl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) LOCK_TAKE(hdw->big_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) fl = pvr2_hdw_untrip_unlocked(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) } while (0); LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (fl) pvr2_hdw_state_sched(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return hdw->state_pipeline_req != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) int ret,st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) LOCK_TAKE(hdw->big_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) pvr2_hdw_untrip_unlocked(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if ((!enable_flag) != !(hdw->state_pipeline_req)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) hdw->state_pipeline_req = enable_flag != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) pvr2_trace(PVR2_TRACE_START_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) "/*--TRACE_STREAM--*/ %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) enable_flag ? "enable" : "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) pvr2_hdw_state_sched(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) } while (0); LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (enable_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) while ((st = hdw->master_state) != PVR2_STATE_RUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (st != PVR2_STATE_READY) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) int fl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) LOCK_TAKE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if ((fl = (hdw->desired_stream_type != config)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) hdw->desired_stream_type = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) hdw->state_pipeline_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) trace_stbit("state_pipeline_config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) hdw->state_pipeline_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) pvr2_hdw_state_sched(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (fl) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) return pvr2_hdw_wait(hdw,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static int get_default_tuner_type(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) int unit_number = hdw->unit_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) int tp = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) tp = tuner[unit_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (tp < 0) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) hdw->tuner_type = tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) hdw->tuner_updated = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) int unit_number = hdw->unit_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) int tp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) tp = video_std[unit_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (tp) return tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) int unit_number = hdw->unit_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) int tp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) tp = tolerance[unit_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* Try a harmless request to fetch the eeprom's address over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) endpoint 1. See what happens. Only the full FX2 image can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) respond to this. If this probe fails then likely the FX2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) firmware needs be loaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) LOCK_TAKE(hdw->ctl_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) result = pvr2_send_request_ex(hdw,HZ*1,!0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) hdw->cmd_buffer,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) hdw->cmd_buffer,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (result < 0) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) } while(0); LOCK_GIVE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) "Probe of device endpoint 1 result status %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) "Probe of device endpoint 1 succeeded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return result == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) struct pvr2_std_hack {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) v4l2_std_id pat; /* Pattern to match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) v4l2_std_id msk; /* Which bits we care about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) v4l2_std_id std; /* What additional standards or default to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* This data structure labels specific combinations of standards from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) tveeprom that we'll try to recognize. If we recognize one, then assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) a specified default standard to use. This is here because tveeprom only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) tells us about available standards not the intended default standard (if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) any) for the device in question. We guess the default based on what has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) been reported as available. Note that this is only for guessing a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) default - which can always be overridden explicitly - and if the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) has otherwise named a default then that default will always be used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) place of this table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static const struct pvr2_std_hack std_eeprom_maps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) { /* PAL(B/G) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .pat = V4L2_STD_B|V4L2_STD_GH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) { /* NTSC(M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .pat = V4L2_STD_MN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .std = V4L2_STD_NTSC_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) { /* PAL(I) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .pat = V4L2_STD_PAL_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .std = V4L2_STD_PAL_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) { /* SECAM(L/L') */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) { /* PAL(D/D1/K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .pat = V4L2_STD_DK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) char buf[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) unsigned int bcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) v4l2_std_id std1,std2,std3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) std1 = get_default_standard(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) pvr2_trace(PVR2_TRACE_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) "Supported video standard(s) reported available in hardware: %.*s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) bcnt,buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) hdw->std_mask_avail = hdw->std_mask_eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) std2 = (std1|std3) & ~hdw->std_mask_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (std2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) pvr2_trace(PVR2_TRACE_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) "Expanding supported video standards to include: %.*s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) bcnt,buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) hdw->std_mask_avail |= std2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (std1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) pvr2_trace(PVR2_TRACE_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) "Initial video standard forced to %.*s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) bcnt,buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) hdw->std_mask_cur = std1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) hdw->std_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (std3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pvr2_trace(PVR2_TRACE_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) "Initial video standard (determined by device type): %.*s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) bcnt, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) hdw->std_mask_cur = std3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) hdw->std_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (std_eeprom_maps[idx].msk ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ((std_eeprom_maps[idx].pat ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) hdw->std_mask_eeprom) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) std_eeprom_maps[idx].msk) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) (std_eeprom_maps[idx].pat !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) hdw->std_mask_eeprom)) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) std_eeprom_maps[idx].std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) pvr2_trace(PVR2_TRACE_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) "Initial video standard guessed as %.*s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) bcnt,buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) hdw->std_mask_cur = std_eeprom_maps[idx].std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) hdw->std_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) static unsigned int pvr2_copy_i2c_addr_list(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) unsigned short *dst, const unsigned char *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) unsigned int dst_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) unsigned int cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (!src) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) while (src[cnt] && (cnt + 1) < dst_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) dst[cnt] = src[cnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) dst[cnt] = I2C_CLIENT_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) for cx25840 causes that module to correctly set up its video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) scaling. This is really a problem in the cx25840 module itself,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) but we work around it here. The problem has not been seen in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ivtv because there VBI is supported and set up. We don't do VBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) here (at least not yet) and thus we never attempted to even set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) it up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) struct v4l2_format fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /* We're not using a cx25840 so don't enable the hack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) "Module ID %u: Executing cx25840 VBI hack",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) hdw->decoder_client_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) memset(&fmt, 0, sizeof(fmt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) vbi, s_sliced_fmt, &fmt.fmt.sliced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) const struct pvr2_device_client_desc *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) const char *fname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) unsigned char mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) unsigned int i2ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) const unsigned char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /* Arbitrary count - max # i2c addresses we will probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) unsigned short i2caddr[25];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) mid = cd->module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (!fname) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) "Module ID %u for device %s has no name? The driver might have a configuration problem.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) mid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) hdw->hdw_desc->description);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) "Module ID %u (%s) for device %s being loaded...",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) mid, fname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) hdw->hdw_desc->description);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ARRAY_SIZE(i2caddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) module_i2c_addresses[mid] : NULL) != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /* Second chance: Try default i2c address list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ARRAY_SIZE(i2caddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (i2ccnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) "Module ID %u: Using default i2c address list",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) mid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (!i2ccnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) "Module ID %u (%s) for device %s: No i2c addresses. The driver might have a configuration problem.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) mid, fname, hdw->hdw_desc->description);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (i2ccnt == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) "Module ID %u: Setting up with specified i2c address 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) mid, i2caddr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) fname, i2caddr[0], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) "Module ID %u: Setting up with address probe list",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) mid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) fname, 0, i2caddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (!sd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) "Module ID %u (%s) for device %s failed to load. Possible missing sub-device kernel module or initialization failure within module.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) mid, fname, hdw->hdw_desc->description);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) /* Tag this sub-device instance with the module ID we know about.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) In other places we'll use that tag to determine if the instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) requires special handling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) sd->grp_id = mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /* client-specific setup... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) switch (mid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) case PVR2_CLIENT_ID_CX25840:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) case PVR2_CLIENT_ID_SAA7115:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) hdw->decoder_client_id = mid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) const struct pvr2_string_table *cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) const struct pvr2_device_client_table *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) int okFl = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) cm = &hdw->hdw_desc->client_modules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) for (idx = 0; idx < cm->cnt; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) request_module(cm->lst[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ct = &hdw->hdw_desc->client_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) for (idx = 0; idx < ct->cnt; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (!okFl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) hdw->flag_modulefail = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) pvr2_hdw_render_useless(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct pvr2_ctrl *cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) int reloadFl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (hdw->hdw_desc->fx2_firmware.cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) if (!reloadFl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) reloadFl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (reloadFl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) "USB endpoint config looks strange; possibly firmware needs to be loaded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (!reloadFl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) reloadFl = !pvr2_hdw_check_firmware(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (reloadFl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) "Check for FX2 firmware failed; possibly firmware needs to be loaded");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (reloadFl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (pvr2_upload_firmware1(hdw) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) "Failure uploading firmware1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) hdw->fw1_state = FW1_STATE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) hdw->force_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (!hdw->hdw_desc->flag_no_powerup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) pvr2_hdw_cmd_powerup(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* Take the IR chip out of reset, if appropriate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) pvr2_issue_simple_cmd(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) FX2CMD_HCW_ZILOG_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) (1 << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ((0) << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) /* This step MUST happen after the earlier powerup step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) pvr2_i2c_core_init(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /* Reset demod only on Hauppauge 160xxx platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) pr_info("%s(): resetting 160xxx demod\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) /* TODO: not sure this is proper place to reset once only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) pvr2_issue_simple_cmd(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) FX2CMD_HCW_DEMOD_RESET_PIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) (1 << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ((0) << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) usleep_range(10000, 10500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) pvr2_issue_simple_cmd(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) FX2CMD_HCW_DEMOD_RESET_PIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) (1 << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ((1) << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) usleep_range(10000, 10500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) pvr2_hdw_load_modules(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) cptr = hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (cptr->info->skip_init) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (!cptr->info->set_value) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) cptr->info->set_value(cptr,~0,cptr->info->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) pvr2_hdw_cx25840_vbi_hack(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) /* Set up special default values for the television and radio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) frequencies here. It's not really important what these defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) are, but I set them to something usable in the Chicago area just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) to make driver testing a little easier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) hdw->freqValTelevision = default_tv_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) hdw->freqValRadio = default_radio_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) // Do not use pvr2_reset_ctl_endpoints() here. It is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) // thread-safe against the normal pvr2_send_request() mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) // (We should make it thread safe).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (hdw->hdw_desc->flag_has_hauppauge_rom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) ret = pvr2_hdw_get_eeprom_addr(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) "Unable to determine location of eeprom, skipping");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) hdw->eeprom_addr = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) pvr2_eeprom_analyze(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) hdw->tuner_updated = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) hdw->std_mask_eeprom = V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (hdw->serial_number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) "sn-%lu", hdw->serial_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) } else if (hdw->unit_number >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) "unit-%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) hdw->unit_number + 'a');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) "unit-??");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) hdw->identifier[idx] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) pvr2_hdw_setup_std(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) if (!get_default_tuner_type(hdw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) "pvr2_hdw_setup: Tuner type overridden to %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) hdw->tuner_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (hdw->hdw_desc->signal_routing_scheme ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) PVR2_ROUTING_SCHEME_GOTVIEW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /* Ensure that GPIO 11 is set to output for GOTVIEW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) pvr2_hdw_commit_setup(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) hdw->vid_stream = pvr2_stream_create();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (hdw->vid_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) idx = get_default_error_tolerance(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) "pvr2_hdw_setup: video stream %p setting tolerance %u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) hdw->vid_stream,idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) PVR2_VID_ENDPOINT,idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) if (!pvr2_hdw_dev_ok(hdw)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) hdw->flag_init_ok = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) pvr2_hdw_state_sched(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) /* Set up the structure and attempt to put the device into a usable state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) This can be a time-consuming operation, which is why it is not done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) internally as part of the create() step. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) pvr2_hdw_setup_low(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (pvr2_hdw_dev_ok(hdw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) if (hdw->flag_init_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) PVR2_TRACE_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) "Device initialization completed successfully.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (hdw->fw1_state == FW1_STATE_RELOAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) PVR2_TRACE_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) "Device microcontroller firmware (re)loaded; it should now reset and reconnect.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) "Device initialization was not successful.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) if (hdw->fw1_state == FW1_STATE_MISSING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) "Giving up since device microcontroller firmware appears to be missing.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) if (hdw->flag_modulefail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) "***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) "You need to resolve the failing condition before this driver can function. There should be some earlier messages giving more information about the problem.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (procreload) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) "Attempting pvrusb2 recovery by reloading primary firmware.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) "If this works, device should disconnect and reconnect in a sane state.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) hdw->fw1_state = FW1_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) pvr2_upload_firmware1(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) "***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) "You might need to power cycle the pvrusb2 device in order to recover.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) /* Perform second stage initialization. Set callback pointer first so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) we can avoid a possible initialization race (if the kernel thread runs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) before the callback has been set). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) void (*callback_func)(void *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) void *callback_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) LOCK_TAKE(hdw->big_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) if (hdw->flag_disconnected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) /* Handle a race here: If we're already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) disconnected by this point, then give up. If we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) get past this then we'll remain connected for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) the duration of initialization since the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) initialization sequence is now protected by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) big_lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) hdw->state_data = callback_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) hdw->state_func = callback_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) pvr2_hdw_setup(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) } while (0); LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return hdw->flag_init_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /* Create, set up, and return a structure for interacting with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) underlying hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) const struct usb_device_id *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) unsigned int idx,cnt1,cnt2,m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) struct pvr2_hdw *hdw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) int valid_std_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) struct pvr2_ctrl *cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) struct usb_device *usb_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) const struct pvr2_device_desc *hdw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) __u8 ifnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) struct v4l2_queryctrl qctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) struct pvr2_ctl_info *ciptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) usb_dev = interface_to_usbdev(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) if (hdw_desc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) "If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) hdw,hdw_desc->description);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) hdw_desc->description);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) if (hdw_desc->flag_is_experimental) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) pvr2_trace(PVR2_TRACE_INFO, "**********");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) pvr2_trace(PVR2_TRACE_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) "***WARNING*** Support for this device (%s) is experimental.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) hdw_desc->description);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) pvr2_trace(PVR2_TRACE_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) "Important functionality might not be entirely working.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) pvr2_trace(PVR2_TRACE_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) "Please consider contacting the driver author to help with further stabilization of the driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) pvr2_trace(PVR2_TRACE_INFO, "**********");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) if (!hdw) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) timer_setup(&hdw->decoder_stabilization_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) pvr2_hdw_decoder_stabilization_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) timer_setup(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) hdw->master_state = PVR2_STATE_DEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) init_waitqueue_head(&hdw->state_wait_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) hdw->tuner_signal_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) cx2341x_fill_defaults(&hdw->enc_ctl_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) /* Calculate which inputs are OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) m |= 1 << PVR2_CVAL_INPUT_DTV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) hdw->input_avail_mask = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) hdw->input_allowed_mask = hdw->input_avail_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) /* If not a hybrid device, pathway_state never changes. So
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) initialize it here to what it should forever be. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) hdw->pathway_state = PVR2_PATHWAY_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) hdw->control_cnt = CTRLDEF_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) hdw->control_cnt += MPEGDEF_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) hdw->controls = kcalloc(hdw->control_cnt, sizeof(struct pvr2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) if (!hdw->controls) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) hdw->hdw_desc = hdw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) for (idx = 0; idx < hdw->control_cnt; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) cptr = hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) cptr->hdw = hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) for (idx = 0; idx < 32; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) cptr = hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) cptr->info = control_defs+idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /* Ensure that default input choice is a valid one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) m = hdw->input_avail_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (!((1UL << idx) & m)) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) hdw->input_val = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) /* Define and configure additional controls from cx2341x module. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) sizeof(*(hdw->mpeg_ctrl_info)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (!hdw->mpeg_ctrl_info) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) cptr = hdw->controls + idx + CTRLDEF_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) ciptr = &(hdw->mpeg_ctrl_info[idx].info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) ciptr->name = mpeg_ids[idx].strid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) ciptr->v4l_id = mpeg_ids[idx].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) ciptr->skip_init = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) ciptr->get_value = ctrl_cx2341x_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) ciptr->is_dirty = ctrl_cx2341x_is_dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) qctrl.id = ciptr->v4l_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) ciptr->set_value = ctrl_cx2341x_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) strscpy(hdw->mpeg_ctrl_info[idx].desc, qctrl.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) sizeof(hdw->mpeg_ctrl_info[idx].desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) ciptr->default_value = qctrl.default_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) switch (qctrl.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) case V4L2_CTRL_TYPE_INTEGER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ciptr->type = pvr2_ctl_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ciptr->def.type_int.min_value = qctrl.minimum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) ciptr->def.type_int.max_value = qctrl.maximum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) case V4L2_CTRL_TYPE_BOOLEAN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) ciptr->type = pvr2_ctl_bool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) case V4L2_CTRL_TYPE_MENU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) ciptr->type = pvr2_ctl_enum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) ciptr->def.type_enum.value_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) ciptr->v4l_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) for (cnt1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) ciptr->def.type_enum.value_names[cnt1] != NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) cnt1++) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) ciptr->def.type_enum.count = cnt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) cptr->info = ciptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) // Initialize control data regarding video standard masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) valid_std_mask = pvr2_std_get_usable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) for (idx = 0; idx < 32; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) if (!(valid_std_mask & (1UL << idx))) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) cnt1 = pvr2_std_id_to_str(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) hdw->std_mask_names[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) sizeof(hdw->std_mask_names[idx])-1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) 1UL << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) hdw->std_mask_names[idx][cnt1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) if (cptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) memcpy(&hdw->std_info_avail,cptr->info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) sizeof(hdw->std_info_avail));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) cptr->info = &hdw->std_info_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) hdw->std_info_avail.def.type_bitmask.bit_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) hdw->std_mask_ptrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) hdw->std_info_avail.def.type_bitmask.valid_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) valid_std_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if (cptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) memcpy(&hdw->std_info_cur,cptr->info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) sizeof(hdw->std_info_cur));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) cptr->info = &hdw->std_info_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) hdw->std_info_cur.def.type_bitmask.bit_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) hdw->std_mask_ptrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) hdw->std_info_cur.def.type_bitmask.valid_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) valid_std_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (cptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) memcpy(&hdw->std_info_detect,cptr->info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) sizeof(hdw->std_info_detect));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) cptr->info = &hdw->std_info_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) hdw->std_info_detect.def.type_bitmask.bit_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) hdw->std_mask_ptrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) hdw->std_info_detect.def.type_bitmask.valid_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) valid_std_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) hdw->cropcap_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) hdw->eeprom_addr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) hdw->unit_number = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) hdw->v4l_minor_number_video = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) hdw->v4l_minor_number_vbi = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) hdw->v4l_minor_number_radio = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if (!hdw->ctl_write_buffer) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if (!hdw->ctl_read_buffer) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if (!hdw->ctl_write_urb) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) if (!hdw->ctl_read_urb) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) "Error registering with v4l core, giving up");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) mutex_lock(&pvr2_unit_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) for (idx = 0; idx < PVR_NUM; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (unit_pointers[idx]) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) hdw->unit_number = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) unit_pointers[idx] = hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) mutex_unlock(&pvr2_unit_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) cnt1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) cnt1 += cnt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) if (hdw->unit_number >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) ('a' + hdw->unit_number));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) cnt1 += cnt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) hdw->name[cnt1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) hdw->unit_number,hdw->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) hdw->tuner_type = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) hdw->flag_ok = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) hdw->usb_intf = intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) hdw->usb_dev = usb_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) usb_set_interface(hdw->usb_dev,ifnum,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) mutex_init(&hdw->ctl_lock_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) mutex_init(&hdw->big_lock_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) return hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) if (hdw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) del_timer_sync(&hdw->quiescent_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) del_timer_sync(&hdw->decoder_stabilization_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) del_timer_sync(&hdw->encoder_run_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) del_timer_sync(&hdw->encoder_wait_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) flush_work(&hdw->workpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) usb_free_urb(hdw->ctl_read_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) usb_free_urb(hdw->ctl_write_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) kfree(hdw->ctl_read_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) kfree(hdw->ctl_write_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) kfree(hdw->controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) kfree(hdw->mpeg_ctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) kfree(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) /* Remove _all_ associations between this driver and the underlying USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) layer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if (hdw->flag_disconnected) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if (hdw->ctl_read_urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) usb_kill_urb(hdw->ctl_read_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) usb_free_urb(hdw->ctl_read_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) hdw->ctl_read_urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) if (hdw->ctl_write_urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) usb_kill_urb(hdw->ctl_write_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) usb_free_urb(hdw->ctl_write_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) hdw->ctl_write_urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) if (hdw->ctl_read_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) kfree(hdw->ctl_read_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) hdw->ctl_read_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if (hdw->ctl_write_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) kfree(hdw->ctl_write_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) hdw->ctl_write_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) hdw->flag_disconnected = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) /* If we don't do this, then there will be a dangling struct device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) reference to our disappearing device persisting inside the V4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) core... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) v4l2_device_disconnect(&hdw->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) hdw->usb_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) hdw->usb_intf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) pvr2_hdw_render_useless(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) vdev->v4l2_dev = &hdw->v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) /* Destroy hardware interaction structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (!hdw) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) flush_work(&hdw->workpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) del_timer_sync(&hdw->quiescent_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) del_timer_sync(&hdw->decoder_stabilization_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) del_timer_sync(&hdw->encoder_run_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) del_timer_sync(&hdw->encoder_wait_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) if (hdw->fw_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) kfree(hdw->fw_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) hdw->fw_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) if (hdw->vid_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) pvr2_stream_destroy(hdw->vid_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) hdw->vid_stream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) v4l2_device_unregister(&hdw->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) pvr2_hdw_disconnect(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) mutex_lock(&pvr2_unit_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) if ((hdw->unit_number >= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) (hdw->unit_number < PVR_NUM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) (unit_pointers[hdw->unit_number] == hdw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) unit_pointers[hdw->unit_number] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) mutex_unlock(&pvr2_unit_mtx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) kfree(hdw->controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) kfree(hdw->mpeg_ctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) kfree(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) return (hdw && hdw->flag_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /* Called when hardware has been unplugged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) LOCK_TAKE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) pvr2_i2c_core_done(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) LOCK_TAKE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) pvr2_hdw_remove_usb_stuff(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) LOCK_GIVE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /* Get the number of defined controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) return hdw->control_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) /* Retrieve a control handle given its index (0..count-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) if (idx >= hdw->control_cnt) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) return hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /* Retrieve a control handle given its index (0..count-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) unsigned int ctl_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) struct pvr2_ctrl *cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) /* This could be made a lot more efficient, but for now... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) for (idx = 0; idx < hdw->control_cnt; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) cptr = hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) i = cptr->info->internal_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) if (i && (i == ctl_id)) return cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) /* Given a V4L ID, retrieve the control structure associated with it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) struct pvr2_ctrl *cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) /* This could be made a lot more efficient, but for now... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) for (idx = 0; idx < hdw->control_cnt; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) cptr = hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) i = cptr->info->v4l_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) if (i && (i == ctl_id)) return cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) /* Given a V4L ID for its immediate predecessor, retrieve the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) structure associated with it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) unsigned int ctl_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) struct pvr2_ctrl *cptr,*cp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) /* This could be made a lot more efficient, but for now... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) cp2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) for (idx = 0; idx < hdw->control_cnt; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) cptr = hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) i = cptr->info->v4l_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) if (!i) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) if (i <= ctl_id) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (cp2 && (cp2->info->v4l_id < i)) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) cp2 = cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) return cp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) switch (tp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) case pvr2_ctl_int: return "integer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) case pvr2_ctl_enum: return "enum";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) case pvr2_ctl_bool: return "boolean";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) case pvr2_ctl_bitmask: return "bitmask";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) return "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) const char *name, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) struct v4l2_control ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) memset(&ctrl, 0, sizeof(ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) ctrl.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) ctrl.value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) std = (v4l2_std_id)hdw->std_mask_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) v4l2_device_call_all(&hdw->v4l2_dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) video, querystd, &std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) return std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) /* Execute whatever commands are required to update the state of all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) sub-devices so that they match our current control values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) static void pvr2_subdev_update(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) pvr2_subdev_update_func fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) if (hdw->tuner_updated || hdw->force_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) struct tuner_setup setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) hdw->tuner_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) if (((int)(hdw->tuner_type)) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) memset(&setup, 0, sizeof(setup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) setup.addr = ADDR_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) setup.type = hdw->tuner_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) setup.mode_mask = T_RADIO | T_ANALOG_TV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) v4l2_device_call_all(&hdw->v4l2_dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) tuner, s_type_addr, &setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) v4l2_device_call_all(&hdw->v4l2_dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) tuner, s_radio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) v4l2_std_id vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) vs = hdw->std_mask_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) v4l2_device_call_all(&hdw->v4l2_dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) video, s_std, vs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) pvr2_hdw_cx25840_vbi_hack(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) hdw->tuner_signal_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) hdw->cropcap_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) struct v4l2_tuner vt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) memset(&vt, 0, sizeof(vt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) vt.audmode = hdw->audiomode_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) if (hdw->freqDirty || hdw->force_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) unsigned long fv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) struct v4l2_frequency freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) fv = pvr2_hdw_get_cur_freq(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) memset(&freq, 0, sizeof(freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) /* ((fv * 1000) / 62500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) freq.frequency = (fv * 2) / 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) freq.frequency = fv / 62500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) /* tuner-core currently doesn't seem to care about this, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) let's set it anyway for completeness. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) freq.type = V4L2_TUNER_RADIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) freq.type = V4L2_TUNER_ANALOG_TV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) freq.tuner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) s_frequency, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) struct v4l2_subdev_format format = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .which = V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) format.format.width = hdw->res_hor_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) format.format.height = hdw->res_ver_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) format.format.code = MEDIA_BUS_FMT_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) format.format.width, format.format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) NULL, &format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) if (hdw->srate_dirty || hdw->force_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) hdw->srate_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) switch (hdw->srate_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) val = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) val = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) val = 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) v4l2_device_call_all(&hdw->v4l2_dev, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) audio, s_clock_freq, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) /* Unable to set crop parameters; there is apparently no equivalent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) for VIDIOC_S_CROP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) id = sd->grp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) fp = pvr2_module_update_functions[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) if (!fp) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) (*fp)(hdw, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) /* Figure out if we need to commit control changes. If so, mark internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) state flags to indicate this fact and return true. Otherwise do nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) else and return false. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) struct pvr2_ctrl *cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) int commit_flag = hdw->force_dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) char buf[100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) unsigned int bcnt,ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) for (idx = 0; idx < hdw->control_cnt; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) cptr = hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) if (!cptr->info->is_dirty) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) if (!cptr->info->is_dirty(cptr)) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) commit_flag = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) cptr->info->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) cptr->info->get_value(cptr,&value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) buf+bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) sizeof(buf)-bcnt,&ccnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) bcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) get_ctrl_typename(cptr->info->type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) pvr2_trace(PVR2_TRACE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) "/*--TRACE_COMMIT--*/ %.*s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) bcnt,buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) if (!commit_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) /* Nothing has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) hdw->state_pipeline_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) pvr2_hdw_state_sched(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) /* Perform all operations needed to commit all control changes. This must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) be performed in synchronization with the pipeline state and is thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) expected to be called as part of the driver's worker thread. Return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) true if commit successful, otherwise return false to indicate that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) commit isn't possible at this time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) struct pvr2_ctrl *cptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) int disruptive_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) if (hdw->input_dirty && hdw->state_pathway_ok &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) hdw->pathway_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) /* Change of mode being asked for... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) hdw->state_pathway_ok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) if (!hdw->state_pathway_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /* Can't commit anything until pathway is ok. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) /* Handle some required side effects when the video standard is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) changed.... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) if (hdw->std_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) int nvres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) int gop_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) if (hdw->std_mask_cur & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) nvres = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) gop_size = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) nvres = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) gop_size = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) /* Rewrite the vertical resolution to be appropriate to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) video standard that has been selected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) if (nvres != hdw->res_ver_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) hdw->res_ver_val = nvres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) hdw->res_ver_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) /* Rewrite the GOP size to be appropriate to the video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) standard that has been selected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) if (gop_size != hdw->enc_ctl_state.video_gop_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) struct v4l2_ext_controls cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) struct v4l2_ext_control c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) memset(&cs, 0, sizeof(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) memset(&c1, 0, sizeof(c1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) cs.controls = &c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) cs.count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) c1.value = gop_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) VIDIOC_S_EXT_CTRLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) /* The broadcast decoder can only scale down, so if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) * res_*_dirty && crop window < output format ==> enlarge crop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * The mpeg encoder receives fields of res_hor_val dots and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) * res_ver_val halflines. Limits: hor<=720, ver<=576.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) hdw->cropw_val = hdw->res_hor_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) hdw->cropw_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) } else if (hdw->cropw_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) hdw->res_hor_dirty = !0; /* must rescale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) hdw->res_hor_val = min(720, hdw->cropw_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) hdw->croph_val = hdw->res_ver_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) hdw->croph_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) } else if (hdw->croph_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) hdw->res_ver_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) hdw->res_ver_val = min(nvres, hdw->croph_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) /* If any of the below has changed, then we can't do the update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) while the pipeline is running. Pipeline must be paused first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) and decoder -> encoder connection be made quiescent before we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) can proceed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) disruptive_change =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) (hdw->std_dirty ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) hdw->enc_unsafe_stale ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) hdw->srate_dirty ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) hdw->res_ver_dirty ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) hdw->res_hor_dirty ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) hdw->cropw_dirty ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) hdw->croph_dirty ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) hdw->input_dirty ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) (hdw->active_stream_type != hdw->desired_stream_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (disruptive_change && !hdw->state_pipeline_idle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) /* Pipeline is not idle; we can't proceed. Arrange to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) cause pipeline to stop so that we can try this again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) later.... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) hdw->state_pipeline_pause = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) if (hdw->srate_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) /* Write new sample rate into control structure since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) * the master copy is stale. We must track srate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) * separate from the mpeg control structure because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) * other logic also uses this value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) struct v4l2_ext_controls cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) struct v4l2_ext_control c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) memset(&cs,0,sizeof(cs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) memset(&c1,0,sizeof(c1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) cs.controls = &c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) cs.count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) c1.value = hdw->srate_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) if (hdw->active_stream_type != hdw->desired_stream_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) /* Handle any side effects of stream config here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) hdw->active_stream_type = hdw->desired_stream_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) if (hdw->hdw_desc->signal_routing_scheme ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) PVR2_ROUTING_SCHEME_GOTVIEW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) u32 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) /* Handle GOTVIEW audio switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) pvr2_hdw_gpio_get_out(hdw,&b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) /* Set GPIO 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) /* Clear GPIO 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) /* Check and update state for all sub-devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) pvr2_subdev_update(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) hdw->tuner_updated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) hdw->force_dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) for (idx = 0; idx < hdw->control_cnt; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) cptr = hdw->controls + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) if (!cptr->info->clear_dirty) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) cptr->info->clear_dirty(cptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) hdw->state_encoder_run) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) /* If encoder isn't running or it can't be touched, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) this will get worked out later when we start the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) encoder. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) if (pvr2_encoder_adjust(hdw) < 0) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) hdw->state_pipeline_config = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) /* Hardware state may have changed in a way to cause the cropping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) capabilities to have changed. So mark it stale, which will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) cause a later re-fetch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) int fl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) LOCK_TAKE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) fl = pvr2_hdw_commit_setup(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) if (!fl) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) return pvr2_hdw_wait(hdw,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) static void pvr2_hdw_worker_poll(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) int fl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) LOCK_TAKE(hdw->big_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) fl = pvr2_hdw_state_eval(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) } while (0); LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) if (fl && hdw->state_func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) hdw->state_func(hdw->state_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) return wait_event_interruptible(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) hdw->state_wait_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) (hdw->state_stale == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) (!state || (hdw->master_state != state)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) /* Return name for this driver instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) return hdw->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) return hdw->hdw_desc->description;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) return hdw->hdw_desc->shortname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) LOCK_TAKE(hdw->ctl_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) result = pvr2_send_request(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) hdw->cmd_buffer,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) hdw->cmd_buffer,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) if (result < 0) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) result = (hdw->cmd_buffer[0] != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) } while(0); LOCK_GIVE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) /* Execute poll of tuner status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) LOCK_TAKE(hdw->big_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) } while (0); LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) if (!hdw->cropcap_stale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) if (hdw->cropcap_stale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) /* Return information about cropping capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) int stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) LOCK_TAKE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) stat = pvr2_hdw_check_cropcap(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) if (!stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) /* Return information about the tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) LOCK_TAKE(hdw->big_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) if (hdw->tuner_signal_stale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) pvr2_hdw_status_poll(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) } while (0); LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /* Get handle to video output stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) return hp->vid_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) int nr = pvr2_hdw_get_unit_number(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) LOCK_TAKE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) pr_info("pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) pvr2_hdw_state_log_state(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) pr_info("pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) /* Grab EEPROM contents, needed for direct method. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) #define EEPROM_SIZE 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) u8 *eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) u8 iadd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) u16 eepromSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) unsigned int offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) int mode16 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) unsigned pcnt,tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) if (!eeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) "Failed to allocate memory required to read eeprom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) trace_eeprom("Value for eeprom addr from controller was 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) hdw->eeprom_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) addr = hdw->eeprom_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) /* Seems that if the high bit is set, then the *real* eeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) address is shifted right now bit position (noticed this in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) newer PVR USB2 hardware) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) if (addr & 0x80) addr >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) /* FX2 documentation states that a 16bit-addressed eeprom is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) expected if the I2C address is an odd number (yeah, this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) strange but it's what they do) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) mode16 = (addr & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) eepromSize = (mode16 ? EEPROM_SIZE : 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) eepromSize, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) mode16 ? 16 : 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) msg[0].addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) msg[0].len = mode16 ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) msg[0].buf = iadd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) msg[1].addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) /* We have to do the actual eeprom data fetch ourselves, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) (1) we're only fetching part of the eeprom, and (2) if we were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) getting the whole thing our I2C driver can't grab it in one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) pass - which is what tveeprom is otherwise going to attempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) pcnt = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) offs = tcnt + (eepromSize - EEPROM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) if (mode16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) iadd[0] = offs >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) iadd[1] = offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) iadd[0] = offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) msg[1].len = pcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) msg[1].buf = eeprom+tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) if ((ret = i2c_transfer(&hdw->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) msg,ARRAY_SIZE(msg))) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) "eeprom fetch set offs err=%d",ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) kfree(eeprom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) return eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) int enable_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) u16 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) unsigned int pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) LOCK_TAKE(hdw->big_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) if ((hdw->fw_buffer == NULL) == !enable_flag) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) if (!enable_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) "Cleaning up after CPU firmware fetch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) kfree(hdw->fw_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) hdw->fw_buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) hdw->fw_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) if (hdw->fw_cpu_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) /* Now release the CPU. It will disconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) and reconnect later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) pvr2_hdw_cpureset_assert(hdw,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) hdw->fw_cpu_flag = (mode != 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) if (hdw->fw_cpu_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) "Preparing to suck out CPU firmware (size=%u)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) hdw->fw_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) if (!hdw->fw_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) hdw->fw_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) /* We have to hold the CPU during firmware upload. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) pvr2_hdw_cpureset_assert(hdw,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) /* download the firmware from address 0000-1fff in 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) (=0x800) bytes chunk. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) "Grabbing CPU firmware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) for(address = 0; address < hdw->fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) address += 0x800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) ret = usb_control_msg(hdw->usb_dev,pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) 0xa0,0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) address,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) hdw->fw_buffer+address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) 0x800,1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) if (ret < 0) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) "Done grabbing CPU firmware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) "Sucking down EEPROM contents");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) if (!hdw->fw_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) "EEPROM content suck failed.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) hdw->fw_size = EEPROM_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) "Done sucking down EEPROM contents");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) } while (0); LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) /* Return true if we're in a mode for retrieval CPU firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) return hdw->fw_buffer != NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) char *buf,unsigned int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) LOCK_TAKE(hdw->big_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) if (!buf) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) if (!cnt) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) if (!hdw->fw_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) if (offs >= hdw->fw_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) "Read firmware data offs=%d EOF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) memcpy(buf,hdw->fw_buffer+offs,cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) pvr2_trace(PVR2_TRACE_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) "Read firmware data offs=%d cnt=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) offs,cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) ret = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) } while (0); LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) enum pvr2_v4l_type index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) default: return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) /* Store a v4l minor device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) enum pvr2_v4l_type index,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) static void pvr2_ctl_write_complete(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) struct pvr2_hdw *hdw = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) hdw->ctl_write_pend_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) if (hdw->ctl_read_pend_flag) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) complete(&hdw->ctl_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) static void pvr2_ctl_read_complete(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) struct pvr2_hdw *hdw = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) hdw->ctl_read_pend_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) if (hdw->ctl_write_pend_flag) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) complete(&hdw->ctl_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) struct hdw_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) struct pvr2_hdw *hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) static void pvr2_ctl_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) struct hdw_timer *timer = from_timer(timer, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) struct pvr2_hdw *hdw = timer->hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) hdw->ctl_timeout_flag = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) if (hdw->ctl_write_pend_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) usb_unlink_urb(hdw->ctl_write_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) if (hdw->ctl_read_pend_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) usb_unlink_urb(hdw->ctl_read_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) /* Issue a command and get a response from the device. This extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) version includes a probe flag (which if set means that device errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) should not be logged or treated as fatal) and a timeout in jiffies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) This can be used to non-lethally probe the health of endpoint 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) unsigned int timeout,int probe_fl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) void *write_data,unsigned int write_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) void *read_data,unsigned int read_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) struct hdw_timer timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) .hdw = hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) if (!hdw->ctl_lock_held) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) "Attempted to execute control transfer without lock!!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) return -EDEADLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) if (!hdw->flag_ok && !probe_fl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) "Attempted to execute control transfer when device not ok");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) if (!probe_fl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) "Attempted to execute control transfer when USB is disconnected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) /* Ensure that we have sane parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) if (!write_data) write_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) if (!read_data) read_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) if (write_len > PVR2_CTL_BUFFSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) "Attempted to execute %d byte control-write transfer (limit=%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) write_len,PVR2_CTL_BUFFSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) if (read_len > PVR2_CTL_BUFFSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) "Attempted to execute %d byte control-read transfer (limit=%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) write_len,PVR2_CTL_BUFFSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) if ((!write_len) && (!read_len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) "Attempted to execute null control transfer?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) hdw->cmd_debug_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) if (write_len && write_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) hdw->cmd_debug_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) hdw->cmd_debug_write_len = write_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) hdw->cmd_debug_read_len = read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) /* Initialize common stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) init_completion(&hdw->ctl_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) hdw->ctl_timeout_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) hdw->ctl_write_pend_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) hdw->ctl_read_pend_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) timer_setup_on_stack(&timer.timer, pvr2_ctl_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) timer.timer.expires = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) if (write_len && write_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) hdw->cmd_debug_state = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) /* Transfer write data to internal buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) for (idx = 0; idx < write_len; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) hdw->ctl_write_buffer[idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) ((unsigned char *)write_data)[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) /* Initiate a write request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) usb_fill_bulk_urb(hdw->ctl_write_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) hdw->usb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) usb_sndbulkpipe(hdw->usb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) PVR2_CTL_WRITE_ENDPOINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) hdw->ctl_write_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) write_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) pvr2_ctl_write_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) hdw->ctl_write_urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) hdw->ctl_write_pend_flag = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) if (usb_urb_ep_type_check(hdw->ctl_write_urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) "Invalid write control endpoint");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) "Failed to submit write-control URB status=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) hdw->ctl_write_pend_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) if (read_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) hdw->cmd_debug_state = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) memset(hdw->ctl_read_buffer,0x43,read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) /* Initiate a read request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) usb_fill_bulk_urb(hdw->ctl_read_urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) hdw->usb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) usb_rcvbulkpipe(hdw->usb_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) PVR2_CTL_READ_ENDPOINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) hdw->ctl_read_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) read_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) pvr2_ctl_read_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) hdw->ctl_read_urb->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) hdw->ctl_read_pend_flag = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) if (usb_urb_ep_type_check(hdw->ctl_read_urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) pvr2_trace(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) "Invalid read control endpoint");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) "Failed to submit read-control URB status=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) hdw->ctl_read_pend_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) /* Start timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) add_timer(&timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) /* Now wait for all I/O to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) hdw->cmd_debug_state = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) wait_for_completion(&hdw->ctl_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) hdw->cmd_debug_state = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) /* Stop timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) del_timer_sync(&timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) hdw->cmd_debug_state = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) if (hdw->ctl_timeout_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) if (!probe_fl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) "Timed out control-write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) if (write_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) /* Validate results of write request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) if ((hdw->ctl_write_urb->status != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) (hdw->ctl_write_urb->status != -ENOENT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) (hdw->ctl_write_urb->status != -ECONNRESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) /* USB subsystem is reporting some kind of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) on the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) status = hdw->ctl_write_urb->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) if (!probe_fl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) "control-write URB failure, status=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) if (hdw->ctl_write_urb->actual_length < write_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) /* Failed to write enough data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) if (!probe_fl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) "control-write URB short, expected=%d got=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) write_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) hdw->ctl_write_urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) if (read_len && read_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) /* Validate results of read request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) if ((hdw->ctl_read_urb->status != 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) (hdw->ctl_read_urb->status != -ENOENT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) (hdw->ctl_read_urb->status != -ECONNRESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) /* USB subsystem is reporting some kind of failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) on the read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) status = hdw->ctl_read_urb->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) if (!probe_fl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) "control-read URB failure, status=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) if (hdw->ctl_read_urb->actual_length < read_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) /* Failed to read enough data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) if (!probe_fl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) "control-read URB short, expected=%d got=%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) read_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) hdw->ctl_read_urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) /* Transfer retrieved data out from internal buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) for (idx = 0; idx < read_len; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) ((unsigned char *)read_data)[idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) hdw->ctl_read_buffer[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) hdw->cmd_debug_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) if ((status < 0) && (!probe_fl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) pvr2_hdw_render_useless(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) destroy_timer_on_stack(&timer.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) int pvr2_send_request(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) void *write_data,unsigned int write_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) void *read_data,unsigned int read_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) return pvr2_send_request_ex(hdw,HZ*4,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) write_data,write_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) read_data,read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) unsigned int cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) unsigned int args = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) LOCK_TAKE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) hdw->cmd_buffer[0] = cmdcode & 0xffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) args = (cmdcode >> 8) & 0xffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) args = (args > 2) ? 2 : args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) if (args) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) cnt += args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) if (args > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) if (pvrusb2_debug & PVR2_TRACE_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) unsigned int ccnt,bcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) char tbuf[50];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) cmdcode &= 0xffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) bcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) ccnt = scnprintf(tbuf+bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) sizeof(tbuf)-bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) "Sending FX2 command 0x%x",cmdcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) bcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) ccnt = scnprintf(tbuf+bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) sizeof(tbuf)-bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) " \"%s\"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) pvr2_fx2cmd_desc[idx].desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) bcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) if (args) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) ccnt = scnprintf(tbuf+bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) sizeof(tbuf)-bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) " (%u",hdw->cmd_buffer[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) bcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) if (args > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) ccnt = scnprintf(tbuf+bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) sizeof(tbuf)-bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) ",%u",hdw->cmd_buffer[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) bcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) ccnt = scnprintf(tbuf+bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) sizeof(tbuf)-bcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) bcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) LOCK_GIVE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) LOCK_TAKE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) hdw->cmd_buffer[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) hdw->cmd_buffer[7] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) LOCK_GIVE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) LOCK_TAKE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) hdw->cmd_buffer[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) hdw->cmd_buffer[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) hdw->cmd_buffer[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) hdw->cmd_buffer[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) hdw->cmd_buffer[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) hdw->cmd_buffer[7] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) LOCK_GIVE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) if (!hdw->flag_ok) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) "Device being rendered inoperable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) if (hdw->vid_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) hdw->flag_ok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) trace_stbit("flag_ok",hdw->flag_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) pvr2_hdw_state_sched(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) ret = usb_reset_device(hdw->usb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) usb_unlock_device(hdw->usb_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) "Failed to lock USB device ret=%d",ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) if (init_pause_msec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) pvr2_trace(PVR2_TRACE_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) "Waiting %u msec for hardware to settle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) init_pause_msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) msleep(init_pause_msec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) char *da;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) unsigned int pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) if (!hdw->usb_dev) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) da = kmalloc(16, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) if (da == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) "Unable to allocate memory to control CPU reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) da[0] = val ? 0x01 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) /* Write the CPUCS register on the 8051. The lsb of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) is the reset bit; a 1 asserts reset while a 0 clears it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) pvr2_trace(PVR2_TRACE_ERROR_LEGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) "cpureset_assert(%d) error=%d",val,ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) pvr2_hdw_render_useless(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) kfree(da);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) "Requesting decoder reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) if (hdw->decoder_client_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) core, reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) pvr2_hdw_cx25840_vbi_hack(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) pvr2_trace(PVR2_TRACE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) "Unable to reset decoder: nothing attached");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) hdw->flag_ok = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) /* Use this for Hauppauge 160xxx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) pr_debug("%s(): resetting demod on Hauppauge 160xxx platform skipped\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) /* Can't reset 160xxx or it will trash Demod tristate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) return pvr2_issue_simple_cmd(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) FX2CMD_HCW_MAKO_SLEEP_PIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) (1 << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) ((onoff ? 1 : 0) << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) return pvr2_issue_simple_cmd(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) FX2CMD_HCW_DEMOD_RESETIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) (1 << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) ((onoff ? 1 : 0) << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) hdw->flag_ok = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) return pvr2_issue_simple_cmd(hdw,(onoff ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) FX2CMD_ONAIR_DTV_POWER_ON :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) FX2CMD_ONAIR_DTV_POWER_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) return pvr2_issue_simple_cmd(hdw,(onoff ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) FX2CMD_ONAIR_DTV_STREAMING_ON :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) FX2CMD_ONAIR_DTV_STREAMING_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) int cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) /* Compare digital/analog desired setting with current setting. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) they don't match, fix it... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) if (cmode == hdw->pathway_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) /* They match; nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) switch (hdw->hdw_desc->digital_control_scheme) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) if (cmode == PVR2_PATHWAY_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) /* If moving to analog mode, also force the decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) to reset. If no decoder is attached, then it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) ok to ignore this because if/when the decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) attaches, it will reset itself at that time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) pvr2_hdw_cmd_decoder_reset(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) case PVR2_DIGITAL_SCHEME_ONAIR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) /* Supposedly we should always have the power on whether in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) digital or analog mode. But for now do what appears to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) work... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) pvr2_hdw_untrip_unlocked(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) hdw->pathway_state = cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) /* change some GPIO data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) * note: bit d7 of dir appears to control the LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) * so we shut it off here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) if (onoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) typedef void (*led_method_func)(struct pvr2_hdw *,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) static led_method_func led_methods[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) /* Toggle LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) unsigned int scheme_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) led_method_func fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) if ((!onoff) == (!hdw->led_on)) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) hdw->led_on = onoff != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) scheme_id = hdw->hdw_desc->led_scheme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) if (scheme_id < ARRAY_SIZE(led_methods)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) fp = led_methods[scheme_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) fp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) if (fp) (*fp)(hdw,onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) /* Stop / start video stream transport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) /* If we're in analog mode, then just issue the usual analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) return pvr2_issue_simple_cmd(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) (runFl ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) FX2CMD_STREAMING_ON :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) FX2CMD_STREAMING_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) /*Note: Not reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) /* Whoops, we don't know what mode we're in... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) /* To get here we have to be in digital mode. The mechanism here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) is unfortunately different for different vendors. So we switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) on the device's digital scheme attribute in order to figure out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) what to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) switch (hdw->hdw_desc->digital_control_scheme) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) return pvr2_issue_simple_cmd(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) (runFl ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) FX2CMD_HCW_DTV_STREAMING_ON :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) FX2CMD_HCW_DTV_STREAMING_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) case PVR2_DIGITAL_SCHEME_ONAIR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) ret = pvr2_issue_simple_cmd(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) (runFl ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) FX2CMD_STREAMING_ON :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) FX2CMD_STREAMING_OFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) if (ret) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) /* Evaluate whether or not state_pathway_ok can change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) if (hdw->state_pathway_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) /* Nothing to do if pathway is already ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) if (!hdw->state_pipeline_idle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) /* Not allowed to change anything if pipeline is not idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) hdw->state_pathway_ok = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) /* Evaluate whether or not state_encoder_ok can change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) if (hdw->state_encoder_ok) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) if (hdw->flag_tripped) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) if (hdw->state_encoder_run) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) if (hdw->state_encoder_config) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) if (hdw->state_decoder_run) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) if (hdw->state_usbstream_run) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) if (pvr2_upload_firmware2(hdw) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) hdw->flag_tripped = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) trace_stbit("flag_tripped",hdw->flag_tripped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) hdw->state_encoder_ok = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) /* Evaluate whether or not state_encoder_config can change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) static int state_eval_encoder_config(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) if (hdw->state_encoder_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) if (hdw->state_encoder_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) if (hdw->state_pipeline_req &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) !hdw->state_pipeline_pause) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) hdw->state_encoder_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) hdw->state_encoder_waitok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) /* paranoia - solve race if timer just completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) del_timer_sync(&hdw->encoder_wait_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) if (!hdw->state_pathway_ok ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) !hdw->state_encoder_ok ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) !hdw->state_pipeline_idle ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) hdw->state_pipeline_pause ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) !hdw->state_pipeline_req ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) !hdw->state_pipeline_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) /* We must reset the enforced wait interval if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) anything has happened that might have disturbed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) the encoder. This should be a rare case. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) if (timer_pending(&hdw->encoder_wait_timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) del_timer_sync(&hdw->encoder_wait_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) if (hdw->state_encoder_waitok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) /* Must clear the state - therefore we did
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) something to a state bit and must also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) return true. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) hdw->state_encoder_waitok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) trace_stbit("state_encoder_waitok",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) hdw->state_encoder_waitok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) if (!hdw->state_encoder_waitok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) if (!timer_pending(&hdw->encoder_wait_timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) /* waitok flag wasn't set and timer isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) running. Check flag once more to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) a race then start the timer. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) the point when we measure out a minimal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) quiet interval before doing something to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) the encoder. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) if (!hdw->state_encoder_waitok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) hdw->encoder_wait_timer.expires =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) jiffies + msecs_to_jiffies(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) TIME_MSEC_ENCODER_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) add_timer(&hdw->encoder_wait_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) /* We can't continue until we know we have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) quiet for the interval measured by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) pvr2_encoder_configure(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) trace_stbit("state_encoder_config",hdw->state_encoder_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) /* Return true if the encoder should not be running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) if (!hdw->state_encoder_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) /* Encoder isn't healthy at the moment, so stop it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) if (!hdw->state_pathway_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) /* Mode is not understood at the moment (i.e. it wants to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) change), so encoder must be stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) switch (hdw->pathway_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) case PVR2_PATHWAY_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) if (!hdw->state_decoder_run) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) /* We're in analog mode and the decoder is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) running; thus the encoder should be stopped as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) well. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) case PVR2_PATHWAY_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) if (hdw->state_encoder_runok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) /* This is a funny case. We're in digital mode so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) really the encoder should be stopped. However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) if it really is running, only kill it after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) runok has been set. This gives a chance for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) onair quirk to function (encoder must run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) briefly first, at least once, before onair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) digital streaming can work). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) /* Unknown mode; so encoder should be stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) /* If we get here, we haven't found a reason to stop the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) encoder. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) /* Return true if the encoder should be running. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) if (!hdw->state_encoder_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) /* Don't run the encoder if it isn't healthy... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) if (!hdw->state_pathway_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) /* Don't run the encoder if we don't (yet) know what mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) we need to be in... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) switch (hdw->pathway_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) case PVR2_PATHWAY_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) if (hdw->state_decoder_run && hdw->state_decoder_ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) /* In analog mode, if the decoder is running, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) run the encoder. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) case PVR2_PATHWAY_DIGITAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) if ((hdw->hdw_desc->digital_control_scheme ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) PVR2_DIGITAL_SCHEME_ONAIR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) !hdw->state_encoder_runok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) /* This is a quirk. OnAir hardware won't stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) digital until the encoder has been run at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) once, for a minimal period of time (empiricially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) measured to be 1/4 second). So if we're on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) OnAir hardware and the encoder has never been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) run at all, then start the encoder. Normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) state machine logic in the driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) automatically handle the remaining bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) /* For completeness (unknown mode; encoder won't run ever) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) /* If we get here, then we haven't found any reason to run the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) encoder, so don't run it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) /* Evaluate whether or not state_encoder_run can change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) static int state_eval_encoder_run(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) if (hdw->state_encoder_run) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) if (!state_check_disable_encoder_run(hdw)) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) if (hdw->state_encoder_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) del_timer_sync(&hdw->encoder_run_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) if (pvr2_encoder_stop(hdw) < 0) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) hdw->state_encoder_run = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) if (!state_check_enable_encoder_run(hdw)) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) if (pvr2_encoder_start(hdw) < 0) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) hdw->state_encoder_run = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) if (!hdw->state_encoder_runok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) hdw->encoder_run_timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) add_timer(&hdw->encoder_run_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) trace_stbit("state_encoder_run",hdw->state_encoder_run);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) /* Timeout function for quiescent timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) static void pvr2_hdw_quiescent_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) struct pvr2_hdw *hdw = from_timer(hdw, t, quiescent_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) hdw->state_decoder_quiescent = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) hdw->state_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) schedule_work(&hdw->workpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) /* Timeout function for decoder stabilization timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) struct pvr2_hdw *hdw = from_timer(hdw, t, decoder_stabilization_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) hdw->state_decoder_ready = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) hdw->state_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) schedule_work(&hdw->workpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) /* Timeout function for encoder wait timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) static void pvr2_hdw_encoder_wait_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_wait_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) hdw->state_encoder_waitok = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) hdw->state_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) schedule_work(&hdw->workpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) /* Timeout function for encoder run timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) static void pvr2_hdw_encoder_run_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_run_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) if (!hdw->state_encoder_runok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) hdw->state_encoder_runok = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) hdw->state_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) schedule_work(&hdw->workpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) /* Evaluate whether or not state_decoder_run can change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) static int state_eval_decoder_run(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) if (hdw->state_decoder_run) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) if (hdw->state_encoder_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) if (hdw->state_pipeline_req &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) !hdw->state_pipeline_pause &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) hdw->state_pathway_ok) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) if (!hdw->flag_decoder_missed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) pvr2_decoder_enable(hdw,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) hdw->state_decoder_quiescent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) hdw->state_decoder_run = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) /* paranoia - solve race if timer(s) just completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) del_timer_sync(&hdw->quiescent_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) /* Kill the stabilization timer, in case we're killing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) encoder before the previous stabilization interval has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) been properly timed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) del_timer_sync(&hdw->decoder_stabilization_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) hdw->state_decoder_ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) if (!hdw->state_decoder_quiescent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) if (!timer_pending(&hdw->quiescent_timer)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) /* We don't do something about the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) quiescent timer until right here because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) we also want to catch cases where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) decoder was already not running (like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) after initialization) as opposed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) knowing that we had just stopped it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) The second flag check is here to cover a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) race - the timer could have run and set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) this flag just after the previous check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) but before we did the pending check. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) if (!hdw->state_decoder_quiescent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) hdw->quiescent_timer.expires =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) jiffies + msecs_to_jiffies(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) TIME_MSEC_DECODER_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) add_timer(&hdw->quiescent_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) /* Don't allow decoder to start again until it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) been quiesced first. This little detail should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) hopefully further stabilize the encoder. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) if (!hdw->state_pathway_ok ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) !hdw->state_pipeline_req ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) hdw->state_pipeline_pause ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) !hdw->state_pipeline_config ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) !hdw->state_encoder_config ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) !hdw->state_encoder_ok) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) del_timer_sync(&hdw->quiescent_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) if (hdw->flag_decoder_missed) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) hdw->state_decoder_quiescent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) hdw->state_decoder_ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) hdw->state_decoder_run = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) hdw->decoder_stabilization_timer.expires =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) jiffies + msecs_to_jiffies(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) TIME_MSEC_DECODER_STABILIZATION_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) add_timer(&hdw->decoder_stabilization_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) hdw->state_decoder_ready = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) trace_stbit("state_decoder_run",hdw->state_decoder_run);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) /* Evaluate whether or not state_usbstream_run can change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) if (hdw->state_usbstream_run) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) int fl = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) fl = (hdw->state_encoder_ok &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) hdw->state_encoder_run);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) (hdw->hdw_desc->flag_digital_requires_cx23416)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) fl = hdw->state_encoder_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) if (fl &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) hdw->state_pipeline_req &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) !hdw->state_pipeline_pause &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) hdw->state_pathway_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) pvr2_hdw_cmd_usbstream(hdw,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) hdw->state_usbstream_run = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) if (!hdw->state_pipeline_req ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) hdw->state_pipeline_pause ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) !hdw->state_pathway_ok) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) if (!hdw->state_encoder_ok ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) !hdw->state_encoder_run) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) (hdw->hdw_desc->flag_digital_requires_cx23416)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) if (!hdw->state_encoder_ok) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) if (hdw->state_encoder_run) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) if (hdw->hdw_desc->digital_control_scheme ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) PVR2_DIGITAL_SCHEME_ONAIR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) /* OnAir digital receivers won't stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) unless the analog encoder has run first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) Why? I have no idea. But don't even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) try until we know the analog side is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) known to have run. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) if (!hdw->state_encoder_runok) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) hdw->state_usbstream_run = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) /* Attempt to configure pipeline, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) if (hdw->state_pipeline_config ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) hdw->state_pipeline_pause) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) pvr2_hdw_commit_execute(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) /* Update pipeline idle and pipeline pause tracking states based on other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) inputs. This must be called whenever the other relevant inputs have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) static int state_update_pipeline_state(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) int updatedFl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) /* Update pipeline state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) st = !(hdw->state_encoder_run ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) hdw->state_decoder_run ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) hdw->state_usbstream_run ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) (!hdw->state_decoder_quiescent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) if (!st != !hdw->state_pipeline_idle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) hdw->state_pipeline_idle = st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) updatedFl = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) hdw->state_pipeline_pause = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) updatedFl = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) return updatedFl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) typedef int (*state_eval_func)(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) /* Set of functions to be run to evaluate various states in the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) static const state_eval_func eval_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) state_eval_pathway_ok,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) state_eval_pipeline_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) state_eval_encoder_ok,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) state_eval_encoder_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) state_eval_decoder_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) state_eval_encoder_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) state_eval_usbstream_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) /* Process various states and return true if we did anything interesting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) int state_updated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) int check_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) if (!hdw->state_stale) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) if ((hdw->fw1_state != FW1_STATE_OK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) !hdw->flag_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) hdw->state_stale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) return !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) /* This loop is the heart of the entire driver. It keeps trying to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) evaluate various bits of driver state until nothing changes for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) one full iteration. Each "bit of state" tracks some global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) aspect of the driver, e.g. whether decoder should run, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) pipeline is configured, usb streaming is on, etc. We separately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) evaluate each of those questions based on other driver state to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) arrive at the correct running configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) check_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) state_update_pipeline_state(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) /* Iterate over each bit of state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) if ((*eval_funcs[i])(hdw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) check_flag = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) state_updated = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) state_update_pipeline_state(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) } while (check_flag && hdw->flag_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) hdw->state_stale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) trace_stbit("state_stale",hdw->state_stale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) return state_updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) static unsigned int print_input_mask(unsigned int msk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) char *buf,unsigned int acnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) unsigned int idx,ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) unsigned int tcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) if (!((1UL << idx) & msk)) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) ccnt = scnprintf(buf+tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) acnt-tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) "%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) (tcnt ? ", " : ""),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) control_values_input[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) tcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) return tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) static const char *pvr2_pathway_state_name(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) case PVR2_PATHWAY_ANALOG: return "analog";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) case PVR2_PATHWAY_DIGITAL: return "digital";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) default: return "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) char *buf,unsigned int acnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) return scnprintf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) buf,acnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) "driver:%s%s%s%s%s <mode=%s>",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) (hdw->flag_ok ? " <ok>" : " <fail>"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) (hdw->flag_disconnected ? " <disconnected>" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) " <connected>"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) (hdw->flag_tripped ? " <tripped>" : ""),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) (hdw->flag_decoder_missed ? " <no decoder>" : ""),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) pvr2_pathway_state_name(hdw->pathway_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) return scnprintf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) buf,acnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) "pipeline:%s%s%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) (hdw->state_pipeline_idle ? " <idle>" : ""),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) (hdw->state_pipeline_config ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) " <configok>" : " <stale>"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) (hdw->state_pipeline_req ? " <req>" : ""),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) (hdw->state_pipeline_pause ? " <pause>" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) return scnprintf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) buf,acnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) "worker:%s%s%s%s%s%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) (hdw->state_decoder_run ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) (hdw->state_decoder_ready ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) "<decode:run>" : " <decode:start>") :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) (hdw->state_decoder_quiescent ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) "" : " <decode:stop>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) (hdw->state_decoder_quiescent ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) " <decode:quiescent>" : ""),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) (hdw->state_encoder_ok ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) "" : " <encode:init>"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) (hdw->state_encoder_run ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) (hdw->state_encoder_runok ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) " <encode:run>" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) " <encode:firstrun>") :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) (hdw->state_encoder_runok ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) " <encode:stop>" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) " <encode:virgin>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) (hdw->state_encoder_config ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) " <encode:configok>" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) (hdw->state_encoder_waitok ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) "" : " <encode:waitok>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) (hdw->state_usbstream_run ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) " <usb:run>" : " <usb:stop>"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) (hdw->state_pathway_ok ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) " <pathway:ok>" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) return scnprintf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) buf,acnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) "state: %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) pvr2_get_state_name(hdw->master_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) case 4: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) unsigned int tcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) unsigned int ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) ccnt = scnprintf(buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) acnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) "Hardware supported inputs: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) tcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) tcnt += print_input_mask(hdw->input_avail_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) buf+tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) acnt-tcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) if (hdw->input_avail_mask != hdw->input_allowed_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) ccnt = scnprintf(buf+tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) acnt-tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) "; allowed inputs: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) tcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) tcnt += print_input_mask(hdw->input_allowed_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) buf+tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) acnt-tcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) return tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) case 5: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) struct pvr2_stream_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) if (!hdw->vid_stream) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) pvr2_stream_get_stats(hdw->vid_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) &stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) return scnprintf(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) buf,acnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) "Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) stats.bytes_processed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) stats.buffers_in_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) stats.buffers_in_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) stats.buffers_in_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) stats.buffers_processed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) stats.buffers_failed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) case 6: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) unsigned int id = hdw->ir_scheme_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) (id >= ARRAY_SIZE(ir_scheme_names) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) "?" : ir_scheme_names[id]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) /* Generate report containing info about attached sub-devices and attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) i2c clients, including an indication of which attached i2c clients are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) actually sub-devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) char *buf, unsigned int acnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) unsigned int tcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) unsigned int ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) const char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) tcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) id = sd->grp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) if (id < ARRAY_SIZE(module_names)) p = module_names[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) tcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) ccnt = scnprintf(buf + tcnt, acnt - tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) " (unknown id=%u):", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) tcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) if (client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) ccnt = scnprintf(buf + tcnt, acnt - tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) " %s @ %02x\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) tcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) ccnt = scnprintf(buf + tcnt, acnt - tcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) " no i2c client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) tcnt += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) return tcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) char *buf,unsigned int acnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) unsigned int bcnt,ccnt,idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) bcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) LOCK_TAKE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) for (idx = 0; ; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) if (!ccnt) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) bcnt += ccnt; acnt -= ccnt; buf += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) if (!acnt) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) buf[0] = '\n'; ccnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) bcnt += ccnt; acnt -= ccnt; buf += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) bcnt += ccnt; acnt -= ccnt; buf += ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) return bcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) char buf[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) unsigned int idx, ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) unsigned int lcnt, ucnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) for (idx = 0; ; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) if (!ccnt) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) pr_info("%s %.*s\n", hdw->name, ccnt, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) if (ccnt >= sizeof(buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) ccnt = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) ucnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) while (ucnt < ccnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) lcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) lcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) pr_info("%s %.*s\n", hdw->name, lcnt, buf + ucnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) ucnt += lcnt + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) /* Evaluate and update the driver's current state, taking various actions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) as appropriate for the update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) int state_updated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) int callback_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) int analog_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) pvr2_trace(PVR2_TRACE_STBITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) "Drive state check START");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) if (pvrusb2_debug & PVR2_TRACE_STBITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) pvr2_hdw_state_log_state(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) /* Process all state and get back over disposition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) state_updated = pvr2_hdw_state_update(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) /* Update master state based upon all other states. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) if (!hdw->flag_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) st = PVR2_STATE_DEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) } else if (hdw->fw1_state != FW1_STATE_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) st = PVR2_STATE_COLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) } else if ((analog_mode ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) hdw->hdw_desc->flag_digital_requires_cx23416) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) !hdw->state_encoder_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) st = PVR2_STATE_WARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) } else if (hdw->flag_tripped ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) (analog_mode && hdw->flag_decoder_missed)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) st = PVR2_STATE_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) } else if (hdw->state_usbstream_run &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) (!analog_mode ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) (hdw->state_encoder_run && hdw->state_decoder_run))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) st = PVR2_STATE_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) st = PVR2_STATE_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) if (hdw->master_state != st) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) pvr2_trace(PVR2_TRACE_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) "Device state change from %s to %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) pvr2_get_state_name(hdw->master_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) pvr2_get_state_name(st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) hdw->master_state = st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) state_updated = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) callback_flag = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) if (state_updated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) /* Trigger anyone waiting on any state changes here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) wake_up(&hdw->state_wait_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) if (pvrusb2_debug & PVR2_TRACE_STBITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) pvr2_hdw_state_log_state(hdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) pvr2_trace(PVR2_TRACE_STBITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) "Drive state check DONE callback=%d",callback_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) return callback_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) /* Cause kernel thread to check / update driver state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) if (hdw->state_stale) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) hdw->state_stale = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) trace_stbit("state_stale",hdw->state_stale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) schedule_work(&hdw->workpoll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) u32 cval,nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) if (~msk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) if (ret) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) nval = (cval & ~msk) | (val & msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) pvr2_trace(PVR2_TRACE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) msk,val,cval,nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) nval = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) pvr2_trace(PVR2_TRACE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) "GPIO direction changing to 0x%x",nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) u32 cval,nval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) if (~msk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) if (ret) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) nval = (cval & ~msk) | (val & msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) pvr2_trace(PVR2_TRACE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) msk,val,cval,nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) nval = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) pvr2_trace(PVR2_TRACE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) "GPIO output changing to 0x%x",nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) memset(vtp, 0, sizeof(*vtp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) hdw->tuner_signal_stale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) /* Note: There apparently is no replacement for VIDIOC_CROPCAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) using v4l2-subdev - therefore we can't support that AT ALL right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) now. (Of course, no sub-drivers seem to implement it either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) But now it's a a chicken and egg problem...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) vtp->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) vtp->signal, vtp->rxsubchans, vtp->capability,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) vtp->rangelow, vtp->rangehigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) /* We have to do this to avoid getting into constant polling if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) there's nobody to answer a poll of cropcap info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) hdw->cropcap_stale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) return hdw->input_avail_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) return hdw->input_allowed_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) if (hdw->input_val != v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) hdw->input_val = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) hdw->input_dirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) /* Handle side effects - if we switch to a mode that needs the RF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) tuner, then select the right frequency choice as well and mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) it dirty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) hdw->freqSelector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) hdw->freqDirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) hdw->freqSelector = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) hdw->freqDirty = !0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) unsigned int change_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) unsigned int change_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) unsigned int nv,m,idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) LOCK_TAKE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) nv = hdw->input_allowed_mask & ~change_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) nv |= (change_val & change_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) nv &= hdw->input_avail_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) if (!nv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) /* No legal modes left; return error instead. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) ret = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) hdw->input_allowed_mask = nv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) if ((1UL << hdw->input_val) & hdw->input_allowed_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) /* Current mode is still in the allowed mask, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) we're done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) /* Select and switch to a mode that is still in the allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) if (!hdw->input_allowed_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) /* Nothing legal; give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) m = hdw->input_allowed_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) if (!((1UL << idx) & m)) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) pvr2_hdw_set_input(hdw,idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) LOCK_GIVE(hdw->big_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) /* Find I2C address of eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) LOCK_TAKE(hdw->ctl_lock); do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) result = pvr2_send_request(hdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) hdw->cmd_buffer,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) hdw->cmd_buffer,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) if (result < 0) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) result = hdw->cmd_buffer[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) } while(0); LOCK_GIVE(hdw->ctl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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