^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005 Mike Isely <isely@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __PVRUSB2_HDW_INTERNAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __PVRUSB2_HDW_INTERNAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) This header sets up all the internal structures and definitions needed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) track and coordinate the driver's interaction with the hardware. ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) source files which actually implement part of that whole circus should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) including this header. Higher levels, like the external layers to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) various public APIs (V4L, sysfs, etc) should NOT ever include this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) private, internal header. This means that pvrusb2-hdw, pvrusb2-encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) etc will include this, but pvrusb2-v4l should not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "pvrusb2-hdw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pvrusb2-io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/drv-intf/cx2341x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/i2c/ir-kbd-i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "pvrusb2-devattr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Legal values for PVR2_CID_HSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PVR2_CVAL_HSM_FAIL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PVR2_CVAL_HSM_FULL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PVR2_CVAL_HSM_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PVR2_VID_ENDPOINT 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PVR2_UNK_ENDPOINT 0x86 /* maybe raw yuv ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PVR2_VBI_ENDPOINT 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PVR2_CTL_BUFFSIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FREQTABLE_SIZE 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LOCK_TAKE(x) do { mutex_lock(&x##_mutex); x##_held = !0; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LOCK_GIVE(x) do { x##_held = 0; mutex_unlock(&x##_mutex); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) typedef int (*pvr2_ctlf_is_dirty)(struct pvr2_ctrl *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) typedef void (*pvr2_ctlf_clear_dirty)(struct pvr2_ctrl *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) typedef int (*pvr2_ctlf_check_value)(struct pvr2_ctrl *,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) typedef int (*pvr2_ctlf_get_value)(struct pvr2_ctrl *,int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) typedef int (*pvr2_ctlf_set_value)(struct pvr2_ctrl *,int msk,int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) typedef int (*pvr2_ctlf_val_to_sym)(struct pvr2_ctrl *,int msk,int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) char *,unsigned int,unsigned int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) typedef int (*pvr2_ctlf_sym_to_val)(struct pvr2_ctrl *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const char *,unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int *mskp,int *valp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) typedef unsigned int (*pvr2_ctlf_get_v4lflags)(struct pvr2_ctrl *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* This structure describes a specific control. A table of these is set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) in pvrusb2-hdw.c. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct pvr2_ctl_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Control's name suitable for use as an identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Short description of control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Control's implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pvr2_ctlf_get_value get_value; /* Get its value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pvr2_ctlf_get_value get_def_value; /* Get its default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pvr2_ctlf_get_value get_min_value; /* Get minimum allowed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pvr2_ctlf_get_value get_max_value; /* Get maximum allowed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pvr2_ctlf_set_value set_value; /* Set its value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pvr2_ctlf_check_value check_value; /* Check that value is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pvr2_ctlf_val_to_sym val_to_sym; /* Custom convert value->symbol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pvr2_ctlf_sym_to_val sym_to_val; /* Custom convert symbol->value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pvr2_ctlf_is_dirty is_dirty; /* Return true if dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pvr2_ctlf_clear_dirty clear_dirty; /* Clear dirty state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pvr2_ctlf_get_v4lflags get_v4lflags;/* Retrieve v4l flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Control's type (int, enum, bitmask) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum pvr2_ctl_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Associated V4L control ID, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int v4l_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Associated driver internal ID, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int internal_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Don't implicitly initialize this control's value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int skip_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Starting value for this control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int default_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Type-specific control information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct { /* Integer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) long min_value; /* lower limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) long max_value; /* upper limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } type_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct { /* enumerated control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int count; /* enum value count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const char * const *value_names; /* symbol names */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } type_enum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct { /* bitmask control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int valid_bits; /* bits in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const char **bit_names; /* symbol name/bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } type_bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Same as pvr2_ctl_info, but includes storage for the control description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PVR2_CTLD_INFO_DESC_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct pvr2_ctld_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pvr2_ctl_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) char desc[PVR2_CTLD_INFO_DESC_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pvr2_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct pvr2_ctl_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pvr2_hdw *hdw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Disposition of firmware1 loading situation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define FW1_STATE_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FW1_STATE_MISSING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define FW1_STATE_FAILED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FW1_STATE_RELOAD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FW1_STATE_OK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* What state the device is in if it is a hybrid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PVR2_PATHWAY_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PVR2_PATHWAY_ANALOG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PVR2_PATHWAY_DIGITAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) typedef int (*pvr2_i2c_func)(struct pvr2_hdw *,u8,u8 *,u16,u8 *, u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PVR2_I2C_FUNC_CNT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* This structure contains all state data directly needed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) manipulate the hardware (as opposed to complying with a kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) interface) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct pvr2_hdw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Underlying USB device handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct usb_device *usb_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct usb_interface *usb_intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Our handle into the v4l2 sub-device architecture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_device v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Device description, anything that must adjust behavior based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) device specific info will use information held here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct pvr2_device_desc *hdw_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Kernel worker thread handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct work_struct workpoll; /* Update driver state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Video spigot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct pvr2_stream *vid_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Mutex for all hardware state control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct mutex big_lock_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int big_lock_held; /* For debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* This is a simple string which identifies the instance of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) driver. It is unique within the set of existing devices, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) there is no attempt to keep the name consistent with the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) physical device each time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* This is a simple string which identifies the physical device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) instance itself - if possible. (If not possible, then it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) based on the specific driver instance, similar to name above.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) The idea here is that userspace might hopefully be able to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) this recognize specific tuners. It will encode a serial number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) char identifier[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* I2C stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct i2c_adapter i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct i2c_algorithm i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pvr2_i2c_func i2c_func[PVR2_I2C_FUNC_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i2c_cx25840_hack_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int i2c_linked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* IR related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int ir_scheme_active; /* IR scheme as seen from the outside */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct IR_i2c_init_data ir_init_data; /* params passed to IR modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Frequency table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int freqTable[FREQTABLE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int freqProgSlot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Stuff for handling low level control interaction with device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct mutex ctl_lock_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ctl_lock_held; /* For debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct urb *ctl_write_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct urb *ctl_read_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned char *ctl_write_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned char *ctl_read_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int ctl_write_pend_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int ctl_read_pend_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ctl_timeout_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct completion ctl_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned char cmd_buffer[PVR2_CTL_BUFFSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int cmd_debug_state; // Low level command debugging info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned char cmd_debug_code; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int cmd_debug_write_len; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int cmd_debug_read_len; //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Bits of state that describe what is going on with various parts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) of the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int state_pathway_ok; /* Pathway config is ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int state_encoder_ok; /* Encoder is operational */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int state_encoder_run; /* Encoder is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int state_encoder_config; /* Encoder is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int state_encoder_waitok; /* Encoder pre-wait done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int state_encoder_runok; /* Encoder has run for >= .25 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int state_decoder_run; /* Decoder is running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int state_decoder_ready; /* Decoder is stabilized & streamable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int state_usbstream_run; /* FX2 is streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int state_decoder_quiescent; /* Decoder idle for minimal interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int state_pipeline_config; /* Pipeline is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int state_pipeline_req; /* Somebody wants to stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int state_pipeline_pause; /* Pipeline must be paused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int state_pipeline_idle; /* Pipeline not running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* This is the master state of the driver. It is the combined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) result of other bits of state. Examining this will indicate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) overall state of the driver. Values here are one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PVR2_STATE_xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int master_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* True if device led is currently on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int led_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* True if states must be re-evaluated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int state_stale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) void (*state_func)(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void *state_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Timer for measuring required decoder settling time before we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) allowed to fire it up again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct timer_list quiescent_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Timer for measuring decoder stabilization time, which is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) amount of time we need to let the decoder run before we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) trust its output (otherwise the encoder might see garbage and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) then fail to start correctly). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct timer_list decoder_stabilization_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Timer for measuring encoder pre-wait time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct timer_list encoder_wait_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Timer for measuring encoder minimum run time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct timer_list encoder_run_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Place to block while waiting for state changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) wait_queue_head_t state_wait_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int force_dirty; /* consider all controls dirty if true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int flag_ok; /* device in known good state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int flag_modulefail; /* true if at least one module failed to load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int flag_disconnected; /* flag_ok == 0 due to disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int flag_init_ok; /* true if structure is fully initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int fw1_state; /* current situation with fw1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int pathway_state; /* one of PVR2_PATHWAY_xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int flag_decoder_missed;/* We've noticed missing decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int flag_tripped; /* Indicates overall failure to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int decoder_client_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) // CPU firmware info (used to help find / save firmware data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) char *fw_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int fw_cpu_flag; /* True if we are dealing with the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Tuner / frequency control stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int tuner_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int tuner_updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int freqValTelevision; /* Current freq for tv mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int freqValRadio; /* Current freq for radio mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int freqSlotTelevision; /* Current slot for tv mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int freqSlotRadio; /* Current slot for radio mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int freqSelector; /* 0=radio 1=television */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int freqDirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Current tuner info - this information is polled from the I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct v4l2_tuner tuner_signal_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int tuner_signal_stale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Cropping capability info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct v4l2_cropcap cropcap_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int cropcap_stale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Video standard handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) v4l2_std_id std_mask_eeprom; // Hardware supported selections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) v4l2_std_id std_mask_avail; // Which standards we may select from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) v4l2_std_id std_mask_cur; // Currently selected standard(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int std_enum_cur; // selected standard enumeration value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int std_dirty; // True if std_mask_cur has changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct pvr2_ctl_info std_info_enum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct pvr2_ctl_info std_info_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct pvr2_ctl_info std_info_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct pvr2_ctl_info std_info_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) // Generated string names, one per actual V4L2 standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const char *std_mask_ptrs[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) char std_mask_names[32][16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int unit_number; /* ID for driver instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long serial_number; /* ID for hardware itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) char bus_info[32]; /* Bus location info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Minor numbers used by v4l logic (yes, this is a hack, as there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) should be no v4l junk here). Probably a better way to do this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int v4l_minor_number_video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int v4l_minor_number_vbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int v4l_minor_number_radio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Bit mask of PVR2_CVAL_INPUT choices which are valid for the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int input_avail_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Bit mask of PVR2_CVAL_INPUT choices which are currently allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int input_allowed_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Location of eeprom or a negative number if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int eeprom_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) enum pvr2_config active_stream_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) enum pvr2_config desired_stream_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Control state needed for cx2341x module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct cx2341x_mpeg_params enc_cur_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct cx2341x_mpeg_params enc_ctl_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* True if an encoder attribute has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int enc_stale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* True if an unsafe encoder attribute has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int enc_unsafe_stale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* True if enc_cur_state is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int enc_cur_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Control state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define VCREATE_DATA(lab) int lab##_val; int lab##_dirty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) VCREATE_DATA(brightness);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) VCREATE_DATA(contrast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) VCREATE_DATA(saturation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) VCREATE_DATA(hue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) VCREATE_DATA(volume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) VCREATE_DATA(balance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) VCREATE_DATA(bass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) VCREATE_DATA(treble);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) VCREATE_DATA(mute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) VCREATE_DATA(cropl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) VCREATE_DATA(cropt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) VCREATE_DATA(cropw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) VCREATE_DATA(croph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) VCREATE_DATA(input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) VCREATE_DATA(audiomode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) VCREATE_DATA(res_hor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) VCREATE_DATA(res_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) VCREATE_DATA(srate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #undef VCREATE_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct pvr2_ctld_info *mpeg_ctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct pvr2_ctrl *controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int control_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* This function gets the current frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) void pvr2_hdw_status_poll(struct pvr2_hdw *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #endif /* __PVRUSB2_HDW_INTERNAL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags