Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *  Copyright (C) 2007 Michael Krufky <mkrufky@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _PVRUSB2_FX2_CMD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _PVRUSB2_FX2_CMD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define FX2CMD_MEM_WRITE_DWORD  0x01u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FX2CMD_MEM_READ_DWORD   0x02u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define FX2CMD_HCW_ZILOG_RESET  0x10u /* 1=reset 0=release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FX2CMD_MEM_READ_64BYTES 0x28u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FX2CMD_REG_WRITE        0x04u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FX2CMD_REG_READ         0x05u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FX2CMD_MEMSEL           0x06u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FX2CMD_I2C_WRITE        0x08u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FX2CMD_I2C_READ         0x09u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FX2CMD_GET_USB_SPEED    0x0bu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FX2CMD_STREAMING_ON     0x36u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FX2CMD_STREAMING_OFF    0x37u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FX2CMD_FWPOST1          0x52u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* These 2 only exist on Model 160xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FX2CMD_HCW_DEMOD_RESET_PIN 0xd4u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FX2CMD_HCW_MAKO_SLEEP_PIN  0xd5u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FX2CMD_POWER_OFF        0xdcu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FX2CMD_POWER_ON         0xdeu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FX2CMD_DEEP_RESET       0xddu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FX2CMD_GET_EEPROM_ADDR  0xebu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FX2CMD_GET_IR_CODE      0xecu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FX2CMD_HCW_DEMOD_RESETIN       0xf0u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FX2CMD_HCW_DTV_STREAMING_ON    0xf1u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FX2CMD_HCW_DTV_STREAMING_OFF   0xf2u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FX2CMD_ONAIR_DTV_STREAMING_ON  0xa0u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FX2CMD_ONAIR_DTV_STREAMING_OFF 0xa1u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FX2CMD_ONAIR_DTV_POWER_ON      0xa2u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FX2CMD_ONAIR_DTV_POWER_OFF     0xa3u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif /* _PVRUSB2_FX2_CMD_H_ */