Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Hauppauge HD PVR USB driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008      Janne Grunau (j@jannau.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <media/i2c/ir-kbd-i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define HDPVR_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define HDPVR_I2C_MAX_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Define these values to match your devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HD_PVR_VENDOR_ID	0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HD_PVR_PRODUCT_ID	0x4900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HD_PVR_PRODUCT_ID1	0x4901
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define HD_PVR_PRODUCT_ID2	0x4902
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HD_PVR_PRODUCT_ID4	0x4903
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HD_PVR_PRODUCT_ID3	0x4982
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define UNSET    (-1U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define NUM_BUFFERS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define HDPVR_FIRMWARE_VERSION		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define HDPVR_FIRMWARE_VERSION_AC3	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HDPVR_FIRMWARE_VERSION_0X12	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define HDPVR_FIRMWARE_VERSION_0X15	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define HDPVR_FIRMWARE_VERSION_0X1E	0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* #define HDPVR_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) extern int hdpvr_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MSG_INFO	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MSG_BUFFER	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct hdpvr_options {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u8	video_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u8	video_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8	audio_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8	bitrate;	/* in 100kbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u8	peak_bitrate;	/* in 100kbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u8	bitrate_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u8	gop_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	enum v4l2_mpeg_audio_encoding	audio_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u8	brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u8	contrast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u8	hue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u8	saturation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u8	sharpness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* Structure to hold all of our device specific stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) struct hdpvr_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/* the v4l device for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct video_device	video_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* the control handler for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* the usb device for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct usb_device	*udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* v4l2-device unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct v4l2_device	v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct { /* video mode/bitrate control cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		struct v4l2_ctrl *video_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		struct v4l2_ctrl *video_bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		struct v4l2_ctrl *video_bitrate_peak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* v4l2 format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	uint width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* the max packet size of the bulk endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	size_t			bulk_in_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* the address of the bulk in endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	__u8			bulk_in_endpointAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* holds the current device status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	__u8			status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* holds the current set options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct hdpvr_options	options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	v4l2_std_id		cur_std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct v4l2_dv_timings	cur_dv_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	uint			flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* synchronize I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct mutex		io_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* available buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct list_head	free_buff_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* in progress buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct list_head	rec_buff_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* waitqueue for buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	wait_queue_head_t	wait_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* waitqueue for data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	wait_queue_head_t	wait_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/**/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct work_struct	worker;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* current stream owner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct v4l2_fh		*owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* I2C adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct i2c_adapter	i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* I2C lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct mutex		i2c_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* I2C message buffer space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	char			i2c_buf[HDPVR_I2C_MAX_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* For passing data to ir-kbd-i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct IR_i2c_init_data	ir_i2c_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* usb control transfer buffer and lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct mutex		usbc_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u8			*usbc_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8			fw_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline struct hdpvr_device *to_hdpvr_dev(struct v4l2_device *v4l2_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return container_of(v4l2_dev, struct hdpvr_device, v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* buffer one bulk urb of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct hdpvr_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct list_head	buff_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct urb		*urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct hdpvr_device	*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	uint			pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	__u8			status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct hdpvr_video_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u16	width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u16	height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u8	fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	bool	valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	STATUS_UNINITIALIZED	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	STATUS_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	STATUS_STARTING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	STATUS_SHUTTING_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	STATUS_STREAMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	STATUS_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	STATUS_DISCONNECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	HDPVR_FLAG_AC3_CAP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	BUFSTAT_UNINITIALIZED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	BUFSTAT_AVAILABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	BUFSTAT_INPROGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	BUFSTAT_READY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CTRL_START_STREAMING_VALUE	0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CTRL_STOP_STREAMING_VALUE	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CTRL_BITRATE_VALUE		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CTRL_BITRATE_MODE_VALUE		0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CTRL_GOP_MODE_VALUE		0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CTRL_VIDEO_INPUT_VALUE		0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CTRL_VIDEO_STD_TYPE		0x1700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CTRL_AUDIO_INPUT_VALUE		0x2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CTRL_BRIGHTNESS			0x2900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CTRL_CONTRAST			0x2a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CTRL_HUE			0x2b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CTRL_SATURATION			0x2c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CTRL_SHARPNESS			0x2d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CTRL_LOW_PASS_FILTER_VALUE	0x3100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CTRL_DEFAULT_INDEX		0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* :0 s 38 01 1000 0003 0004 4 = 0a00ca00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * BITRATE SETTING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 *   1st and 2nd byte (little endian): average bitrate in 100 000 bit/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 *                                     min: 1 mbit/s, max: 13.5 mbit/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 *   3rd and 4th byte (little endian): peak bitrate in 100 000 bit/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 *                                     min: average + 100kbit/s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 *                                      max: 20.2 mbit/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* :0 s 38 01 1200 0003 0001 1 = 02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * BIT RATE MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 *  constant = 1, variable (peak) = 2, variable (average) = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* :0 s 38 01 1300 0003 0001 1 = 03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * GOP MODE (2 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 *    low bit 0/1: advanced/simple GOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 *   high bit 0/1: IDR(4/32/128) / no IDR (4/32/0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* :0 s 38 01 1700 0003 0001 1 = 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * VIDEO STANDARD or FREQUENCY 0 = 60hz, 1 = 50hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* :0 s 38 01 3100 0003 0004 4 = 03030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * FILTER CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 *   1st byte luma low pass filter strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 *   2nd byte chroma low pass filter strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 *   3rd byte MF enable chroma, min=0, max=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 *   4th byte n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* :0 s 38 b9 0001 0000 0000 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* :0 s 38 d3 0000 0000 0001 1 = 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*		ret = usb_control_msg(dev->udev, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*				      usb_sndctrlpipe(dev->udev, 0), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*				      0xd3, 0x38, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*				      0, 0, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*				      "\0", 1, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*				      1000); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*		info("control request returned %d", ret); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*		msleep(5000); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* :0 s b8 81 1400 0003 0005 5 <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * :0 0 5 = d0024002 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * QUERY FRAME SIZE AND RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 *   1st and 2nd byte (little endian): horizontal resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 *   3rd and 4th byte (little endian): vertical resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 *   5th byte: frame rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	/* :0 s b8 81 1800 0003 0003 3 <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 * :0 0 3 = 030104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 * QUERY SIGNAL AND DETECTED LINES, maybe INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enum hdpvr_video_std {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	HDPVR_60HZ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	HDPVR_50HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum hdpvr_video_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	HDPVR_COMPONENT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	HDPVR_SVIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	HDPVR_COMPOSITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	HDPVR_VIDEO_INPUTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) enum hdpvr_audio_inputs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	HDPVR_RCA_BACK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	HDPVR_RCA_FRONT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	HDPVR_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	HDPVR_AUDIO_INPUTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enum hdpvr_bitrate_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	HDPVR_CONSTANT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	HDPVR_VARIABLE_PEAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	HDPVR_VARIABLE_AVERAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enum hdpvr_gop_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	HDPVR_ADVANCED_IDR_GOP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	HDPVR_SIMPLE_IDR_GOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	HDPVR_ADVANCED_NOIDR_GOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	HDPVR_SIMPLE_NOIDR_GOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void hdpvr_delete(struct hdpvr_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*========================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* hardware control functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int hdpvr_set_options(struct hdpvr_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int hdpvr_set_bitrate(struct hdpvr_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int hdpvr_set_audio(struct hdpvr_device *dev, u8 input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		    enum v4l2_mpeg_audio_encoding codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int hdpvr_config_call(struct hdpvr_device *dev, uint value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		      unsigned char valbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int get_video_info(struct hdpvr_device *dev, struct hdpvr_video_info *vid_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* :0 s b8 81 1800 0003 0003 3 < */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* :0 0 3 = 0301ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int get_input_lines_info(struct hdpvr_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*========================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* v4l2 registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int hdpvr_register_videodev(struct hdpvr_device *dev, struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			    int devnumber);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int hdpvr_cancel_queue(struct hdpvr_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*========================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* i2c adapter registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int hdpvr_register_i2c_adapter(struct hdpvr_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct i2c_client *hdpvr_register_ir_i2c(struct hdpvr_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*========================================================================*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* buffer management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int hdpvr_free_buffers(struct hdpvr_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int hdpvr_alloc_buffers(struct hdpvr_device *dev, uint count);